Questions tagged [clock-speed]

Anything related to clock signal frequency (a.k.a. clock speed) issues in digital systems.

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5answers
285 views

Why is modifying (by adding extra gates) clock inputs undesirable?

I am taking a course in digital electronics at university. I am second year mechanical engineering student, but I felt like it was important to understand some electronics. The lecturer in one of the ...
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4answers
1k views

How does VCO in PLL in computer processor work?

In todays personal computers and notebooks, what is usually used as a Voltage-Controlled Oscillator for generating clock signal for processor? Is that a crystal rather than RC circuit? Is it tuned by ...
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1answer
66 views

Timing specifications: can a spec be converted from units of +/- ms to parts per million?

I have a test specification that requires time base uncertainty of +/- X ppm or less. I understand that ppm is a common way to specify crystal accuracy. But in the performance specification for my ...
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2answers
574 views

Nanosecond interrupt accuracy on a 64MHz microprocessor

I am currently designing a PCB with a 64MHz nRF52832 bluetooth MCU. I have an interrupt connected to this MCU which needs to be detected with 1-3 nanosecond accuracy. Unfortunately, the 64MHz MCU has ...
2
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2answers
346 views

Does clock speed matter when recovering from I2C bus lock up?

When there is I2C lock caused by slave device driving the SDA line low you need to manually generate a few clock signals by doing a simple bit banging on the SCL pin. I thought that this need to be ...
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2answers
264 views

IS heat the only thing keeping CPUs from a faster clock rate? [closed]

Is heat the only thing that keeps CPUs from having a faster clock cycle or are there other limiting physical factors which keeps CPUs under 3~5GHz?
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1answer
556 views

What kind of use cases require a 2GHz, 4GHz, 6GHz, 30GHz or 100GHz oscilloscope? [closed]

I have been thinking of buying some oscilloscope for the work I do with Arduino. In my case it would be partly because of some usefulness and partly because it would give me a chance to learn an ...
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1answer
321 views

How do I calculate to get the correct timing for SPI

I am having an issue with sending the correct HEX registers over SPI to a slave device. I am finally able to see my issue by decoding the SPI using a scope. What I see is random HEX during my test. ...
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3answers
2k views

Computer clock technology?

Let's say I have a computer running at 4 GHz. I would say it means I need a way to measure increments of time of about 0.25 ns. How does a computer do that? My question is both: Technological: what ...
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1answer
276 views

What is the real speed of my system implemented on FPGA? How to check this value?

I created an FPGA system on ModelSim (a simple algorithm that calculate an equation and save on-chip), synthesized with Quartus Prime, then downloaded to my DE1-SOC. My intention is to compare my ...
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0answers
78 views

How to know the speed and energy of a particular Digital Design in Quartus-II and DE1-SOC FPGA (Altera)

I did a digital design in Quartus II and my board DE1-SOC FPGA, now I want to read 3 factors: general speed that digital design takes to finish the application, area of the design if it would be a ...
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0answers
47 views

Best values for R and C for LCD driver

This is a circuit I incorporated in my major project to drive an LCD. For C1, I used a 2.2nF ceramic disc capacitor and the resistor is 100K which based on a basic RC calculator, works out to be about ...
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2answers
88 views

Can i use a slower clock rate for a CPU or a Microcontroller than the one it is supposed to use?

Say i have a CPU or a Microcontroller with a clock rate of 1 GHz, can i use a 1 kHz instead?
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0answers
605 views

Difference between Clock and Operating Frequency

I am very new to embedded world. I am trying to design a transreciever system based on RF MCU. I am looking at ATMEGA64RZAV-10PU from Atmel. The datasheet says the clock frequency as 10MHz but ...
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3answers
497 views

Reading data from digital pressure sensor (Pressure sensor SPD100GD)

We need to read the digital output from a Pressure sensor SPD100GD with an AVR micro (Atmega128). According to the datasheet we must estimate transmission speed. The datasheet is saying: The ...
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2answers
405 views

Implementing a derived clock in a FPGA

Preparing a lab excercise, where we are tasked to generate a 1 Hz clock out of the 50 Mhz system clock of a FPGA. This should be achieved without using any libraries besides ieee.std_logic_1164 and ...
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2answers
599 views

Why asynchronous counters can not work at high clock frequencies?

Asynchronous counters can not work at high clock frequencies and cause problems with decoding circuits. What does this mean in terms of timing and operation of the circuit? Why a “re-synchronizing” ...
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4answers
4k views

Why do we use negative edge trigger Flip Flop instead of positive edge triggered?

The glitches due to race condition can be avoided by using a negative-edge triggered flip-flop instead of the positive-edge-triggered flip-flop used. What does this mean? Source: http://www.zeepedia....
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3answers
173 views

How to discover reliable speed to use a logic gate?

It seems to be very hard to get consistent numbers for the performance of logic chips. I am interested in using the SN74F574 component (8 bit register). Looking at DigiKey, when I search for the ...
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0answers
195 views

How much does the clock drift for the Arduino Pro Mini board?

How much does the clock drift (at most) for the Arduino Pro Mini board? I don't need to correct it on the board, just need to know the specifications, such that I can take the necessary precautions ...
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3answers
800 views

(TDC) Time to Digital Converter for (TOF) Time of Flight Applications. 66.6Picosecond sample

Hello. My question is in regards to dynamic range of short time period TDC's. or alternative solutions to a time to digital application. if further information is required, please ask. Notes ...
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3answers
2k views

Capacitive load - Matching Right Crystal and Caps for oscillator circuit - DS1302 RTC - cut and trim

CL = (C1 * C2) / (C1 + C2) + Cstray I have a 12.5pf crystal. DS1302 is happy with 6pf. what is trim capacitors to make him happy using 12.5pf? 12.5-6=6.5pf (6.5*6.5) / (6.5+6.5) + cstray= 3.25pf + ...
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1answer
231 views

What does ECLK rate mean?

I'm reading a spec doc on some CPU and I didn't get what does this mean: The CPU core requires only a single clock input at the ECLK rate What does ECLK abbreviation stand for? What does ECLK rate ...
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3answers
3k views

Maximum SPI clock speed specified in data sheet

For integrated circuits that use SPI interface, they specify maximum clock frequency in their datasheets such as attached below. The question is that if the datasheet speficies the maximum frequency ...
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1answer
329 views

ATtiny13A cannot be programmed anymore with Arduino as ISP at 500 Hz

My ATtiny13A fuses are set to use the internal 128 kHz clock without clock divided by 8. I found online an ArduinoISP sketch that allows me to program it with that clock speed. But then I uploaded ...
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2answers
520 views

ATtiny power consumption with clock prescaler

I'm designing a battery-powered radio-linked sensor device which requires a long lifetime. Due to the project requirements I have very little onboard energy to work with; a single coin cell is the ...
2
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1answer
568 views

PIC32MX can't get 80 MHz Clock from Internal RC OSC

I am using PIC32MX795F512L with the internal RC oscillator. By changing the settings of the config, I can get to 60 MHz max. But I can't get to 80 MHz. When I change the config for 80&#...
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1answer
553 views

Clock with varying time period System verilog [closed]

I needed help in writing a test bench with a varying clock time period. need to invoke the clock using a task in the test bench.
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4answers
623 views

Is Transmission Line Reflection Frequency Dependent?

I'm currently sending high speed serial over a coax cable. I've got an oscilloscope hooked up (on the load end) trying to watch the clock pulse signal. I've got a 10 ft coax cable with a 12.5 Mhz ...
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3answers
776 views

ATmega - Why is the prescaler factory defaulted to 8?

Why do ATmega (e.g. 328P or 644P) have CKDIV8 (or CLKPS = 0011) factory programmed along with a default internal 8 MHz ...
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1answer
503 views

what is the frequency required to have all harmonics which have more than 10% DC value when we have 250 MHz clock?

A Digital board has a Unipolar square clock of 250 MHz. If the clock on the board at all places should have all the harmonic components which have more than 10% of DC value, the board has to be ...
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1answer
71 views

Programmable clock generator IC and reference circuit

I need a clock source for some data converters (DAC, ADC), and I would like the clock frequency to be as configurable as possible. I assume this would involve some kind of clock multiplier/divider, ...
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2answers
677 views

When would be occasions to use a lower clock given that high speed would always be preferable?

I am using STM32F0 MCU and STM32 CubeMX configurator. I encountered the clock configuration below When would be occasions to use a lower clock speed? Wouldn't faster always be preferable?
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1answer
286 views

PIC10F200 internal clock

I am trying to calibrate the internal clock to turn on a output once for 3 seconds every 7 days within a few minutes accuracy. I was able to accomplish this using the OSCCAL register in the chip. The ...
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1answer
3k views

STM32F4 : Floating point instructions too slow

I'm working on an audio application on the Nucleo F411RE and I've noticed that my processing was too slow, making the application skip some samples. Looking at my disassembly I figured given the ...
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1answer
4k views

Power failure and digital clocks [closed]

I'm asking this here in the interest of figuring out why this happened, and how to fix it. Feel free to suggest different tags, or a different stack. That said... The power went out the other day. No ...
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1answer
146 views

Full-wave rectification for clock signal from wall power

I have built this power supply and clock signal extractor exactly as shown: http://electronics.howstuffworks.com/gadgets/clocks-watches/digital-clock4.htm I have double-checked this and the rest of ...
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3answers
382 views

Regarding CPU speed required for USB applications

I am working on a project for developing a USB keyboard, and I am new to USB protocol and I did initial study regarding basics of data transmissions through USB. I am now checking for USB supported ...
7
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1answer
567 views

pic32 maximum external frequency while running from internal 8MHz RC oscillator

I am completely new to PICs and I have never worked with a part as complex as this. In particular, I'm wondering if it is possible to generate a reference clock (REFCLKO in the datasheet) at 11.2896 ...
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1answer
556 views

Error while running linker am using TIVA C TM4C123G and IAR

I am trying to change and read my TM4C123G launchpad clock frequency to 80 MHZ using TIVAWARE libraries so here is my code: ...
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1answer
362 views

How to find minimum frequency in an asynchronous design?

I want to know what all factors contribute in deciding minimum frequency of asynchronous domains.Also do mention the cases in which minimum frequency concept is required and why.
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3answers
2k views

What does an MCU need to be capable of USB 3.0 communication?

USB 3.0 has been around for quite some time, since it was released in 2008. But you don't see any simple microcontrollers with an internal peripheral that can do USB 3.0. The Atmega32u4, a simple ...
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1answer
862 views

calculate clock cycle of ripple Carry and lookahead adder

How would you find the number of clock cycles it takes to produce sum, the carry out, and overflow flag using ripple carry or lookahead adder. Can someone please explain me how would we go on finding ...
2
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1answer
113 views

LPC1110 confusion about default system clock and uart baud rate

I'm trying to get acquainted with ARMs on example of LPC1110 device. And there is some confusion about selecting baud rate for UART. I suppose it is running at ...
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2answers
16k views

Verilog: Slow Clock Geneator Module (1Hz from 50Mhz)

I wrote clock generator module, i dont know if it is true but the problem is in my reg module. The error is: ERROR:HDLCompilers:246 - "UpDownCounter.v" line 74 Reference to scalar reg 'clk_1Hz' is ...
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2answers
769 views

Figuring out mininum/maximum clock frequency [VHDL]

I made my first design in VHDL with arctgs and sums and now I'm trying to synthesize it into an FPGA. However, before that I need to understand more about: How to discover how many clock cycles my ...
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1answer
3k views

Why ATMega328 can't run SPI at full clock speed

Two part question: In the datasheet on page 168, the best SCK frequency one get get on SPI is \$\dfrac{f_{osc}}{2}\$, why can't this be \$f_{osc}\$? Also from the datasheet: "When the SPI is ...
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2answers
621 views

Problem with connecting clock divider generated by CORE Generator to I2S design for Spartan 6

I'm trying to connect clock divider generated by CORE Generator to I2S receiver and I2S transmitter on Spartan 6. The PLL_BASE is connected via ODDR2 module, as adviced. Both receiver and transmitter ...
5
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3answers
3k views

How do I know if my microcontroller clock frequency is fast enough?

I've been using ARM microcontrollers from NXP in commercial products with great success for the last 2 years. In most of my projects I don't use the PLL to increase the oscillator frequency because ...
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3answers
186 views

Cheapest timer for radio trilateration

I'm building a device that must find its own position on a field (400x400m). Since there will be lot of devices on the field I could not send them their position individually and I want them to be ...