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Questions tagged [clock]

A digital signal that goes high and low at a specific frequency.

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1answer
75 views

circuit to detect chess clock toggle change to fire BT button

I was looking for simple circuit: (SamGibson's idea to add a 2nd reed switch proved possible, see update below.) to detect transition to flat 0 V when player B's clock is running. to detect ...
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25 views

VLSI design question on slack

In the image below I would like to know what happens to the "slack value of clk A and clk B" if clk A becomes -ve edge triggered and clk B becomes +ve edge triggered. Assuming clock of 20ps and 0 ...
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3answers
185 views

Circuit for converting 48kHz to 12MHz

I want to synchronize multiple Behringer U-Phoria UM2 (that are at different locations) via GPS clock. These interfaces are used by musicians to make music together in "real-time" over the internet (...
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26 views

AT91SAM7S512 Oscillator, GPIO, & Reset questions

I just need some clarification of my circuit Oscillator: So for my circuit I want to be able to program it via USB, the datasheet gets a bit confusing to me tho. If I read the datasheet correctly I ...
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5answers
3k views

How can I estimate the speed of this code section for this microcontroller?

I'm using an ATmega328P to read the state of a digital input by using the following code section written in C (there can be alternative ways, but this is an example). ...
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2answers
34 views

pic16f877a problem in timers with proteus simulation

I used PIC16f877A at proteus to do timer interrupt. The code is pretty simple it has nothing to do rather than setting the timer1 registers , the while(1) loop is ...
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1answer
58 views

What circuit will output a short latch pulse when the clock input pauses?

I'm transmitting serial data across a cable to a shift register. I transmit data in discrete packets, where different packets have different bit lengths. The clock frequency is about 20 MHz while ...
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4answers
8k views

How to reset a 4026 counter IC when it reaches 6 for electronic dice

I'm trying to build a circuit to simulate a dice roll using a 555 in astable as it's heart. The output pulses are counted by a 4026 and then fed into a 4511 BCD to 7 segment decoder. It works ...
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1answer
60 views

Why does it take 2 clock cycles to move to the RESET state in my state machine?

I'm writing a finite sequence encoder in Verilog. Basically, an output Z will be activated if the input W is on for at least four clock cycles, or if its off for at least 4 clock cycles. See the ...
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1answer
167 views

Generate clock jitter in a testbench

How would you generate clock jitter in a testbench? I have seen these two ways, but I am not sure if they are the best ways: ...
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3answers
258 views

4 quadrature clock vs 2 quadrature clock + falling edges

I started a digital design - a high precision time counter actually - that will be implemented on a Xilinx FPGA. I will describe it in VHDL. I read several papers about this subject and I found about ...
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1answer
42 views

How to compute clock cycle time from given frequency

let's say I have a processor runs at 100MHZ frequency how can I compute from this it's clock time for each cycle? I know that Frequency = 1 / Clock Time but I am having trouble to fully understand how ...
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1answer
52 views

1 Hz Clock Signal With CD4060 vs CD4521

I am building DIY digital clocks as a school side project. I need to generate a 1 hZ clock signal. I currently have some 32.768kHz crystals but I need to choose an IC. I don’t want to build the ...
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1answer
107 views

Why pick 262144 Hz oscillator frequency?

Some Bulova watches (for example the Precisionist collection) use 262144 Hz crystal oscillators instead of the usual 32768 Hz. What are the true advantages of this higher frequency, if they even exist?...
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2answers
2k views

How to overcome clock stretching on I2C

I have the clock stretching issue on my I2C line, attached is the below snapshot of it.. I have a Kinetis K64 board communicating to a MAX7304 port expander at 400 Khz. Should I get the driver ...
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82 views

Crystal oscillator using 7404 is unstable

I am currently building a small Z80 microprocessor system and require some kind of clock generation. It is not my first design: Earlier I used an Arduino pin that generated a slow clock or a 555 timer....
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1answer
297 views

How to generate a continuous clock from one that periodically turns off?

I have a LVDS clock signal that is gated about ever 30us. This is a MIPI D-PHY clock that switches from HS mode to LP mode when the data lanes go to LP mode (and are auto-clocked). The problem is that ...
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1answer
142 views

Timing Constraints for Forwarded Generated Center-Sampled Clocks?

Problem Description I am trying to figure out the "correct" way to constrain (in .xdc format - this is in Vivado) a forwarded source-synchronous clock that is generated (by division) from the ...
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1answer
539 views

How do I know if I fried my Z80?

I'm working on a free-running circuit like the one here: http://www.z80.info/z80test0.htm The only differences are that I'm using a 4049 clock circuit with a 1 uf cap, and I've added an extra LED at ...
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1answer
210 views

Crystal reference and capacitors for w5500

I'm selecting the caps for the crystal oscillator of the wiznet W5500. The standard Load Capacitance for 25Mhz crystals is 18pF. I found out that the hardware guideline claims for a Load Capacitance ...
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2answers
47 views

Novice question about setting system clock in microcontrollers

This is a novice question. I see that for every embdded project system clock is set by using PLL multipliers. But what determines the system clock value? Why not always max system clock is used? Can ...
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0answers
38 views

Turn a positive clock edge into a negative pulse to make a 74LS170/670 register file synchronous

This is a follow-up o Why did they make the 74x170 (670) register file asychronous, no CLK input?. I want to use that "register file" for my project, but I need to make it behave properly as a ...
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2answers
87 views

Syntax and/or best practice for buffering a vector in Verilog or VHDL

I have a Verilog block (Block A) that samples a serial signal with a relatively slow clock and then puts data in several registers based on the contents of the serial data. Ultimately, these data ...
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1answer
176 views

How would you design a clock in order to play triplets?

If you take a master clock (e.g. 1 Hz) it is easy to get the quarter notes (every pulse), the half notes (every two pulses), and the whole notes (every four pulses) to build a simple drum machine. ...
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1answer
46 views

Is an unlocked PLL an open-loop clock? And is a locked PLL a closed-loop clock?

What is the difference between an open-loop clock and a closed-loop clock? Is a PLL with an oscillator lock a closed loop clock? Is a PLL without an oscillator lock an open-loop clock?
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92 views

I2C data sampling is done at clock edge or level

I am trying to understand I2C data bus from this document. It explains the START-SLAVEADRESS-R/W-ACK-DATA.. as the master-slave take turns to get hold of the shared bus for mutual communication. One ...
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33 views

Does an ISP clock interfere with the on-board clock when programming via ISP?

I am planning to use ISP programmer to program my new AVR board. I use an 8 MHz crystal on my PCB to clock the micro (atmega328p-au). Now, as I understand the ISP programmer will provide its own clock ...
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1answer
104 views

MachXO2 DDR and PCLK routing issue

I'm doing a project in which I use DDR interfaces to transmit and receive data between different FPGAs. The FPGA transmitter will send data at 125 MHz and the receiver will use 250 MHz to sample the ...
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1answer
56 views

4-bit memory serial to parallel memory register circuit question

I am building a 4-bit serial to parallel memory register and I feel like so far I have gotten things right, but I'm unsure of where to connect the CLR connections. Could someone have a look at my ...
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80 views

Increasing system clock frequency on STM32F303 drops I2C clock proportionately - why?

I'm trying to figure out a weird little issue I've discovered while debugging another element of my code. I've got a STM32F303K8 reading and writing to an I2C peripheral. The I2C clock speed is ...
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46 views

Capacitor on clock line of TFT display

Short version (can provide more information if wanted) we have a display (TFT with TTL driver) that we control via PIC32 and Epson Display IC. The supplier changed their driver which should have been ...
22
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4answers
4k views

How to communicate faster than the system clock

I was reading about the new (ish) Thunderbolt 3 today, and was very impressed by the specced speed of 40Gbps. Then I looked at Intel's latest i9 processor speed... about 4.2GHz max. How can a system ...
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How can I test wether my OCXO VCO is working fine?

I recently bought a PTOC32227 OCXO (datasheet) from eBay (secondhand). It is supposed to output a square wave at 10MHz. However, it is a part of a bigger circuit that is not working properly and it ...
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2answers
177 views

Digital Alarm Clock in Multisim. (Home Work/ Final)

I apologize for the schematic. I know it is not the prettiest to look at. My clock runs slow. I know this is because of my 555 timer. I was off somewhere in my calculations and ended up with a 70hz ...
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1answer
135 views

How to make sure a clocked operation happens just once in Vhdl

title may be a bit confusing but what I try to do is to take data from ram/modify it and put that data back to the ram. I want all of this to happen just for the operation(Brightness/Contrast) time ...
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6answers
2k views

1 kHz clock over long wire

I will have a wire that will run up to 1000 m with many nodes connected to it. The wire will run along a CAN bus and a ground wire and must transport a 1 kHz square wave 50% duty-cycle clock signal to ...
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2answers
167 views

Determining which pulse came first on an FPGA

I try to determine which of two asynchronous pulses came first (after a synchronous reset) using an FPGA. The pulses are asynchronous because they are generated from ring oscillators (running on the ...
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1answer
70 views

What's wrong with my timing diagram?

I have made this simple timing diagram that presents the triggering way of D flip flop. The flip flop is triggered by clock's rising edges. I am convinced that the diagram is correct signal-wise. ...
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1answer
74 views

Mystery bug while programming Atmel micro

I'm programming an ATSAME51J20 micro on a custom board with a J-link Plus compact programmer using the SWD protocol. It is successful for small programs, but fails more frequently for larger programs. ...
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4answers
167 views

Positive Level Shift a Clock Output using Diode?

I need to level shift a 26mhz 1.8v clock output by .7v on both the high and low side (so clock swings from .7v to 2.5v on output). Would a simple diode/resistor setup like below work for this? ...
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1answer
60 views

Ethernet PHY clock and sync

I have a general question about reference clocks for ethernet PHYs. The PHYs I have seen so far require an external clock source like a xtal or other singleended clock (in addition to the clk lines ...
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2answers
159 views

High frequency clock from clocked RS latch

We were taught that this circuit is not of much use as when CLK=1, J=1 & K=1, Q toggles at a very high rate. So suppose I want to make a high-frequency clock, can I use this? Of course, the ...
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1answer
17 views

Logisim Flashing button

How can i create a button with a clock that is connected to a LED that the LED turns on when the button is pressed but even if you keep holding it it will turn off
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1answer
143 views

Cascade shift registers driven by single-cycle microcontroller

I'm trying to make a unit in which 4 digits can be updated in a small amount of time from a single-cycle microcontroller (preferably all digits updated within 5uS) My circuit is setup in the ...
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1answer
231 views

Poor man's clock MUX with an LVDS input

I want to send two different 10MHz clock signals to a device. My board have tight volume and power constraints and I would rather not use a complicated clock buffer/PLL/MUX IC. The first source have ...
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27 views

comparing between different phase detectors

I implemented two architectures of phase-frequency detectors and I'm interested to compare between them. (I'm open for extra architectures that might solve problems that I'm not discussing here) I'...
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1answer
48 views

Clock Multiplier / Clock Boosting

I was reading this paper "A 10 b, 20 Msample/s, 35 mW Pipeline A/D Converter" by Cho and Gray from 1995. https://ieeexplore.ieee.org/document/364429 In it, they describe a clock multiplier circuit ...
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54 views

Rising edge detector behavior

I was looking at this StackExchange question: Why does this rising edge detector using a capacitor and a resistor work? I ran the simulation and I'm confused by the behavior. On the rising edge of ...
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0answers
42 views

Programming an ATmega644 with 32.768 kHz external clock and USBTinyISP

I accidentally changed the fuse bits on my ATmega644PA chip so that it is expecting a 32.768 kHz signal in the XTAL1/XTAL2 inputs. I am using the a USBTiny programmer (the Sparkfun AVR Pocket ...
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2answers
5k views

Introduce delay on a single bit signal w.r.t. input clock

I have seen this question and removed the "#.." part of my code to introduce delay, since my code will ultimately run on hardware. Anyway, I am trying with counters and not able to introduce the ...