Questions tagged [clock]

A digital signal that goes high and low at a specific frequency.

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2answers
62 views

How to get a 1 clock period pulse from a constant signal clock input on every 64 clocks?

I would like to "extract" a one period pulse from a constant clock signal on every 64 clocks. This pulse signal is to be used for reset. What kind of logic circuit should I be looking for? ...
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57 views

Clock Generation with PWM?

I'm designing a device with a central MCU/MPU and two external peripherals. The MCU has an internal clock frequency of 110 MHz. I'd like to use the MCU to generate separate clock outputs for each of ...
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Why do some microcontrollers have numerous oscillators (and what are their functions)?

Currently I am reading through the Arm based ATSAM4L series datasheet, and in the sections BSCIF and SCIF I have encountered at least 8 different oscillators/clocks (see image below). I understand ...
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3answers
100 views

Analogue clock position sensing

I want to control an analogue clock movement with a microcontroller. A Lavet motor is used to advance the hands. The issue is detecting where the hands are. I noticed that some radio controlled clocks ...
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1answer
291 views

4-bit memory serial to parallel memory register circuit question

I am building a 4-bit serial to parallel memory register and I feel like so far I have gotten things right, but I'm unsure of where to connect the CLR connections. Could someone have a look at my ...
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21 views

Determining jitter for Vivado clocking wizard?

I have an Artix-7 FPGA AC701 board. In the documentation, it says that it has a 2.5V LVDS differential 200 MHz oscillator (model name: SiT9102AI-243N25E200.00000). I went into SiT9102 datasheet and it ...
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1answer
46 views

Why would a CD4060BE produce a copy of an input clock signal?

I am making a CMOS logic clock and I have a problem with the 1Hz signal generator (see schematic below). When I connect up the CD4060BE chip to a crystal the output on Q8 of the second chip does not ...
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1answer
603 views

Generate clock jitter in a testbench

How would you generate clock jitter in a testbench? I have seen these two ways, but I am not sure if they are the best ways: ...
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1answer
339 views

How to generate a continuous clock from one that periodically turns off?

I have a LVDS clock signal that is gated about ever 30us. This is a MIPI D-PHY clock that switches from HS mode to LP mode when the data lanes go to LP mode (and are auto-clocked). The problem is that ...
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4answers
119 views

Problem mapping VHDL onto development board

I have a very frustrating problem and would really appreciate some help. I am trying to test a RAM block using the switches and LED's on board the Nexys A7-100T FPGA development board. My code is ...
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1answer
46 views

Reference clock in FM receiver chips (si4735)

The datasheet is mentioning a 32678 Hz "reference clock" (RCLK) input. It appears to be a well known thing in this type of ICs because it's highlighted in the list of features. I guess ...
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1answer
63 views

T_hold and T_setup help me understand?

My exam is tomorrow and there is something I don't understand in the material, so I really hope to get some help with this. Giving the following circuit: And giving that both FF are connected to the ...
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4answers
100 views

Crystal tolerances and what that means for timer interrupts

I'm developing a system that needs to periodically wake up and perform a process. We're currently targeting for an hourly wake up (give or take, this spec is very loose). The key here is the unit cost ...
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How can I run a 12 volt car clock on C or D batteries?

I have an old vehicle that I use a battery shut-off on so the clock doesn't tell the correct time. I would like to figure out how to run it on alkaline batteries instead. I have no idea how to do that....
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3answers
806 views

How can I avoid a clock glitch?

I have a clock with a 50% duty cycle, driving a 3-bit ripple counter. When Q2 is high, external lines such as address are stable. I want to generate a short read pulse between 50% and 75% of the Q2 ...
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2answers
149 views

D-Flip-Flop Hold and Setup Timing Requirements

Update: The answer is 28ns for sure Giving the following circuit and timing table: Question: It's known that the time between positive-edge and negative-edge of the clock (which comes after) is ...
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1answer
313 views

Crystal reference and capacitors for w5500

I'm selecting the caps for the crystal oscillator of the wiznet W5500. The standard Load Capacitance for 25Mhz crystals is 18pF. I found out that the hardware guideline claims for a Load Capacitance ...
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1answer
32 views

SPI Timing of WIZ850io

I can't understand the SPI timing diagram, I had search through various websites for timing diagram but I have no idea how to interpret this timing diagram of WIZ850io. I am currently trying to form a ...
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1answer
83 views

D-Flip-Flop Hold and Setup Timing

I am solving some question to prepare for my exam but got stuck on this one and need your help. Giving the following circuit: Where input x gets updated 10ns after ...
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1answer
198 views

Timing Constraints for Forwarded Generated Center-Sampled Clocks?

Problem Description I am trying to figure out the "correct" way to constrain (in .xdc format - this is in Vivado) a forwarded source-synchronous clock that is generated (by division) from the ...
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3answers
254 views

Using a counter to count how many clock cycles a signal is high using Verilog

I want to use a counter to count how many clock cycles an input signal is high. The issue I am running into is that once the input signal returns back to zero, my counter resets which causes my output ...
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0answers
42 views

How to set SPI clock speed for MT7623N

first I must say, I am new to the HW programming, but I really enjoy it. My first project is writing a library for MT7623N (BananaPi R2) that handles GPIO pins. I got the GPIO part done and I can set ...
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58 views

I need to write a verilog code to generate a signal which goes high for one clock pulse after every tenth clock pulse

I need to write verilog code wherein I need a signal which goes high for one clock pulse after every tenth clock pulse. I tried something this way, ...
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8answers
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Why do Microcontrollers need a Clock

Why do instructions need to be processed at set time intervals (i.e. with the use of a clock)? Can't they be executed sequentially - immediately after the previous instruction has completed? An ...
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2answers
91 views

FPGA - synchronise “very close” clock from signal

This is more of a learning question, I can solve the problem but it would be good to know how to do it - can a clock be reconstructed from a signal, and is it easier when the frequency of the clock is ...
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1answer
100 views

Clock domain crossing between OV7670 interface and AXI4-Stream

Update 1: My first approach is to use the xpm_cdc_handshake macro in the following way: ...
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2answers
190 views

pic16f877a problem in timers with proteus simulation

I used PIC16f877A at proteus to do timer interrupt. The code is pretty simple it has nothing to do rather than setting the timer1 registers , the while(1) loop is ...
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2answers
112 views

Need to implement a phase locked frequency converter from 32768Hz to 36000Hz. How would I go about it?

I am building a timecode-related application and need to generate a square-wave clock pulse of 36000 which is integer-dividable down to 24,25 and 30. My source clock is 32768Hz which does not divide ...
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2answers
91 views

Maximum data rate that can be achieved between PIC and FPGA

We are looking at PIC24FJ256GA705 here. It is connected to an FPGA and the FPGA must transfer a few kB of data as fast as possible. I assume that parallel transfer is the best option here, parallel ...
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1answer
311 views

Clock jitter - ppm, ui, ps

I using Xilinx FPGA and need to use its PLL (MMCM or Clk Wizard) I have on my board LVDS 200MHz clock with 50 ppm frequency jitter, I took this and go to some converted I can find on the internet and ...
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2answers
69 views

Capacitor for triggering negative edge J-K Flip Flop's Clock

I have some SN74LS73AN Flip-Flops which, if I understanding well, are triggered by the negative (falling) edge signal of a clock. I wish to use a simple pushbutton as a clock, and I am aware that, for ...
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1answer
29 views

Low impedance complementary negative level shifter for a BBD

I'm trying to clock a BBD (Bucket Brigade Device) circuit (for example the MN3007) from a microcontroller output. However, the circuit requires a complementary negative clock, i.e. CP1 is \$-12V\$ to \...
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1answer
138 views

MachXO2 DDR and PCLK routing issue

I'm doing a project in which I use DDR interfaces to transmit and receive data between different FPGAs. The FPGA transmitter will send data at 125 MHz and the receiver will use 250 MHz to sample the ...
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2answers
83 views

How deos this clock generator work?

This circuit shows a clock generator, where a capacitor is charged to a certain voltage for half a period (phi opening switches S1 and S2). The same voltage but with negative polarity will be shown to ...
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51 views

VHDL state machine using different clocks

I have a state machine inside a process. I want to base the process on two different clocks. Is it possible to use clock1 to clock state1 and clock2 to clock state2?
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1answer
46 views

How is clock signal edge detection done / pros and cons of different approaches? [closed]

I'm currently learning about flip-flops, and I'm curious about the different ways in which the clock signal is handled. So far I've come across 3 different techniques: AND-ing the clock signal with ...
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1answer
77 views

What exactly are the tradeoffs between terminating a transmission line carrying a digital signal in 50 ohms versus high impedance?

I have a black box that outputs a 1.28 MHz clock signal that I need to buffer and distribute. If that signal is terminated into 50 ohms the voltage is so slow <1.5V it won't register as high for ...
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1answer
167 views

How to make sure a clocked operation happens just once in Vhdl

title may be a bit confusing but what I try to do is to take data from ram/modify it and put that data back to the ram. I want all of this to happen just for the operation(Brightness/Contrast) time ...
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0answers
20 views

Impact of reduction on Dynamic energy and dynamic power in microprocessors

A microprocessor has been designed to have a dynamic switch which reduces power consumption when the loading reduces. Assuming a reduction of 20% in voltage reduces clock frequency by 20%. Calculate ...
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40 views

Clock line of SDIO bus has worse rise/fall time than rest of bus

I have an ATWILC3000 wifi module connected to a Raspberry Pi Compute Module 3+ over 4-bit SDIO. It's throwing a lot of bus errors at higher frequencies (currently running at 1 MHz for stability when ...
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1answer
55 views

Input Voltage LM8560

I am currently building a digital clock using the LM8560. In the datasheet it says the maximum voltage at each Pin should not exceed +0.3V or -15V. The IC uses the line frequency of 50/60Hz, which is ...
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2answers
459 views

Digital Alarm Clock in Multisim. (Home Work/ Final)

I apologize for the schematic. I know it is not the prettiest to look at. My clock runs slow. I know this is because of my 555 timer. I was off somewhere in my calculations and ended up with a 70hz ...
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28 views

Logic.ly JK Flip Flop Input Error

I am trying to stimulate a JK Flip Flop in Logic.ly But, when the input is 0 in the circuit shown below, there is an error, which I cannot pinpoint. How do I fix this? This is the initial circuit: ...
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2answers
70 views

Why do we use a low resistors on Data lines for an ADC for example or a clock?

Why do we use a low resistors on Data lines for an ADC for example or a clock ?
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1answer
316 views

Difference between clock cycle, machine cycle and instruction cycle of the CPU

There is a lot of ambiguity between the definition of these three terms. So, I wanted to know what is the intuition behind these terms and how all three are connected to each other.
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1answer
46 views

programmable timer / clock generator

I need to generate a square wave / clock with configurable frequency between say 60 to 500Hz. There are not stringent requirements on the frequency stability. I need to be able to modulate this ...
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1answer
257 views

Understand an I2C clock line implementation

I am trying to understand a C function from a legacy project which is supposed to manage the clock line for an I2C interface. It basically does as follow: Set pin to output: ...
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2answers
291 views

High frequency clock from clocked RS latch

We were taught that this circuit is not of much use as when CLK=1, J=1 & K=1, Q toggles at a very high rate. So suppose I want to make a high-frequency clock, can I use this? Of course, the ...
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1answer
104 views

How to create a cycling clock circuit from scratch?

I'm thinking about doing a project where I have basic components (hex inverter chips, breadboards, jumper wires, transistors, capacitors, etc.) and I create a simple computer. I've been trying to ...
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3answers
2k views

Why is a 15 stage binary counter/divider so cumbersome?

There seem to be many ways to take a 32.768kHz signal and turn it into 1Hz. I can use a CD4060, but still have to add a flip-flop... so 2 "large" chips with excess (potentially) unused functions ...

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