Questions tagged [clock]

A digital signal that goes high and low at a specific frequency.

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3answers
118 views

How does one get ticks of a clock from an atomic clock's microwave signal?

I understand that in an atomic clock there is a microwave signal that is locked to the frequency of the atomic rotation. However, if one wants to extract time ticks from the microwave signal (shown ...
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1answer
44 views

Can you have different clocks working at different intervals to operate a flip flop?

Is it possible to have two clock signals driving a JK toggling flip flop, in which both signals are connected by a XOr gate so that the flip flop only works on either edge of either clock? If possible,...
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2answers
33 views

MIC1557 clock frequency constantly increases. Why?

I'm trying to get a 19.2 KHz frequency out of the MIC1557 clock generator. I managed to get close enough (enough for my application) to this frequency with off the shelf components. The shematic is ...
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1answer
100 views

Ethernet PHY clock and sync

I have a general question about reference clocks for ethernet PHYs. The PHYs I have seen so far require an external clock source like a xtal or other singleended clock (in addition to the clk lines ...
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2answers
95 views

20MHz clock signal over several PCBs

I am running a 3.3V 20MHz clock signal for LED drivers over 10 PCBs that are connected to each other over short cables. Overall, the clock signal must travel 1m. Is this even possible with a 20MHz ...
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1answer
22 views

Doubt regarding static timing analysis - setup time check

I was reading J.Bhasker's STATIC TIMING ANALYSIS book. In that book, he tells that when launch flip flop launches the data & while capture flip flop is capturing data, he says that We now ...
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1answer
1k views

How to Sycnhronize STM32F4 Clock with PC Clock

I'm using 3 STM32F401RE to synchronize their clocks. My desired accuracy is of 1ms and even lesser like 0.1ms. This device is connected to PC via USB port. Question 1 : So I would like to know if I ...
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0answers
87 views

Equipment and approach for performing a long-term measurement of clock signals

This is a follow up question for the circuit I designed with the inspiration from here. The circuit works but over time there appears to be some clock jitter or skew. I am interested in an approach to ...
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1answer
113 views

MachXO2 DDR and PCLK routing issue

I'm doing a project in which I use DDR interfaces to transmit and receive data between different FPGAs. The FPGA transmitter will send data at 125 MHz and the receiver will use 250 MHz to sample the ...
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3answers
62 views

Is a typical register rising edge or falling edge? [closed]

I'm using Logisim to build a 1-bit CPU. However, I am having issues with timing the registers up with the clock. In a CPU, should registers be rising edge or falling edge? Or, could they be something ...
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1answer
82 views

Verilog finite state machine won't reset (asynchronous) current state to initial state (shows xx)

I have mostly worked on VHDL and I have recently started learning Verilog. I wrote a Moore Finite State Machine (FSM). The FSM is not resetting properly as current state upon reset doesn't go into ...
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2answers
225 views

Digital Alarm Clock in Multisim. (Home Work/ Final)

I apologize for the schematic. I know it is not the prettiest to look at. My clock runs slow. I know this is because of my 555 timer. I was off somewhere in my calculations and ended up with a 70hz ...
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0answers
22 views

How to pick clock speeds for a CS4270 codec?

I'm in the process of designing a circuit which includes a Cirrus CS4270 codec and a STM32F405 running as a DSP. I'm trying to define my max usable settings, which would be running at Fs = 192kHz. I'...
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1answer
140 views

How to make sure a clocked operation happens just once in Vhdl

title may be a bit confusing but what I try to do is to take data from ram/modify it and put that data back to the ram. I want all of this to happen just for the operation(Brightness/Contrast) time ...
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2answers
106 views

Why does it take 2 clock cycles to move to the RESET state in my state machine?

I'm writing a finite sequence encoder in Verilog. Basically, an output Z will be activated if the input W is on for at least four clock cycles, or if its off for at least 4 clock cycles. See the ...
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4answers
201 views

Crystal oscillator using 7404 is unstable

I am currently building a small Z80 microprocessor system and require some kind of clock generation. It is not my first design: Earlier I used an Arduino pin that generated a slow clock or a 555 timer....
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49 views

Unexpected result reading pin on clock rising interrupt

What I try to achieve is a simple one-way communication between two MCU's (ATTiny85's to be exact) at 16Mhz. This is just a start, to figure out it can be useful, very basic and needs to be very basic....
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5answers
2k views

Why is this clock signal connected to a capacitor to gnd?

I am trying to understand the following circuit: My problem is to understand why the CLK signal is connected to the capacitor (C7). The bottom side of C7 is connected with a resistor to GND. This ...
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2answers
134 views

How do computers execute instructions spanning multiple clock cycles?

There are some(or most) instructions in a computer that simply cannot be executed in a single clock cycle. But there lies a problem. How does the program counter in the computer know when an ...
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2answers
2k views

Measuring the HSE frequency of an STM32F2

I am programming an STM32F2 (manual here). I am having clock problems and would like to check every clock using an oscilloscope. The first clock I want to check is HSE, which stands for: High Speed ...
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2answers
41 views

Clock Issues from Buffer

I'm testing a board that is having clock issues. The design uses a 40 MHz oscillator, which outputs a clipped sine wave. The clock goes into an inverter buffer to get a 3.3V, 40 MHz sine wave. When ...
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2answers
45 views

soc clock domain questions

Those days there have so many different protocols in the soc which basically means different clock rate. In a Soc system, there have CPU which run at some clock speed, then there have memory(dram) to ...
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3answers
96 views

Internal oscillator drift and its effect on UART

I am eager to know whether a 150kHz drift of internal oscilator clock (mentioned in a STM32 MCU operating with 8MHz internal clock) could destroy a UART connection?
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1answer
53 views

Changing frequency of input clock port (FPGA)

I', using xilinx ultrascale FPGA (xcku025-ffva-1-a) I am referring to application notes provided by xilinx. I am going to use the reference code provided in xapp1315. In this reference code, an ...
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0answers
75 views

Produce a clock out (5 MHz) with a counter and a clock in (50 MHz)

I'm trying to solve previous years' tests in logic design and there's this question that I can't really solve.. So, it gives me an 8-bit counter and a clock in (clk_in) of 50 MHz and it asks to ...
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1answer
210 views

Cascade shift registers driven by single-cycle microcontroller

I'm trying to make a unit in which 4 digits can be updated in a small amount of time from a single-cycle microcontroller (preferably all digits updated within 5uS) My circuit is setup in the ...
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1answer
299 views

Why Op-amp pulse generator circuit do not providing any output?

I'm trying to design a clock with 1.8V CMOS. I've designed the Op-amp and individually it works fine (simulated with up to 10MHz pulse input) . But when I use this opamp to draw the feedback circuit ,...
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1answer
248 views

Poor man's clock MUX with an LVDS input

I want to send two different 10MHz clock signals to a device. My board have tight volume and power constraints and I would rather not use a complicated clock buffer/PLL/MUX IC. The first source have ...
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2answers
191 views

High frequency clock from clocked RS latch

We were taught that this circuit is not of much use as when CLK=1, J=1 & K=1, Q toggles at a very high rate. So suppose I want to make a high-frequency clock, can I use this? Of course, the ...
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1answer
39 views

Accessing same variables in Verilog on different clocks

I have a 50Mhz master clock clk and from that I have a derived baudClock clock which runs at 9600bps. I have a transmitter module that I want to follow a state machine flow every baudClock. The ...
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3answers
72 views

Circuit with two clocks

Most digital circuits can be built in more than one way. However, the easiest way I've seen to build an edge-triggered D flip-flop is with a pair of D latches. One has ...
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4answers
88 views

Digital clock source

I'm currently on an adventure into digital electronics. I've built a bunch of logic, but to test it I need a clock source. Is there a way I can “easily” construct a square-wave oscilator adjustable ...
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1answer
64 views

ATtiny13 at 16MHz? Why not?

How exactly are you supposed to run the ATtiny13 at 16MHz or higher if you really have to? What is the method and what external circuitry do you need to add? Is it altogether more hassle than using ...
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2answers
55 views

Unpowered clock divider

I am not a professional in this area, so I hope I am asking questions correctly. I have a 5V clock pulse with 50-200Hz (square wave) and would like to build a simple unpowered clock divider. Output ...
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3answers
296 views

4 quadrature clock vs 2 quadrature clock + falling edges

I started a digital design - a high precision time counter actually - that will be implemented on a Xilinx FPGA. I will describe it in VHDL. I read several papers about this subject and I found about ...
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2answers
293 views

Crystals, capacitors and W5100

Background: I have built a number of devices based on the W5100 chip, all them were (are) working more or less decently. However last batch currently in testing show faulty behavior - almost all of ...
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1answer
61 views

How do I implement the clock into this testbench?

I am trying to write a testbench for an adder/subtractor but when it compiles the clock does not shift. Here is the verilog for the adder/subtractor: ...
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0answers
83 views

Clock divide by 5 - All ICs obsolete?

I've got an obsolete part in a design (SY100S839VZG) that is being used to take a single 100MHz clk and divide it down into two PECL p/n pairs. For the life of me, I cannot seem to find a single ...
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1answer
83 views

circuit to detect chess clock toggle change to fire BT button

I was looking for simple circuit: (SamGibson's idea to add a 2nd reed switch proved possible, see update below.) to detect transition to flat 0 V when player B's clock is running. to detect ...
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3answers
215 views

Circuit for converting 48kHz to 12MHz

I want to synchronize multiple Behringer U-Phoria UM2 (that are at different locations) via GPS clock. These interfaces are used by musicians to make music together in "real-time" over the internet (...
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0answers
26 views

AT91SAM7S512 Oscillator, GPIO, & Reset questions

I just need some clarification of my circuit Oscillator: So for my circuit I want to be able to program it via USB, the datasheet gets a bit confusing to me tho. If I read the datasheet correctly I ...
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5answers
3k views

How can I estimate the speed of this code section for this microcontroller?

I'm using an ATmega328P to read the state of a digital input by using the following code section written in C (there can be alternative ways, but this is an example). ...
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2answers
53 views

pic16f877a problem in timers with proteus simulation

I used PIC16f877A at proteus to do timer interrupt. The code is pretty simple it has nothing to do rather than setting the timer1 registers , the while(1) loop is ...
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1answer
61 views

What circuit will output a short latch pulse when the clock input pauses?

I'm transmitting serial data across a cable to a shift register. I transmit data in discrete packets, where different packets have different bit lengths. The clock frequency is about 20 MHz while ...
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4answers
8k views

How to reset a 4026 counter IC when it reaches 6 for electronic dice

I'm trying to build a circuit to simulate a dice roll using a 555 in astable as it's heart. The output pulses are counted by a 4026 and then fed into a 4511 BCD to 7 segment decoder. It works ...
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1answer
262 views

Generate clock jitter in a testbench

How would you generate clock jitter in a testbench? I have seen these two ways, but I am not sure if they are the best ways: ...
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1answer
44 views

How to compute clock cycle time from given frequency

let's say I have a processor runs at 100MHZ frequency how can I compute from this it's clock time for each cycle? I know that Frequency = 1 / Clock Time but I am having trouble to fully understand how ...
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1answer
98 views

1 Hz Clock Signal With CD4060 vs CD4521

I am building DIY digital clocks as a school side project. I need to generate a 1 hZ clock signal. I currently have some 32.768kHz crystals but I need to choose an IC. I don’t want to build the ...
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1answer
127 views

Why pick 262144 Hz oscillator frequency?

Some Bulova watches (for example the Precisionist collection) use 262144 Hz crystal oscillators instead of the usual 32768 Hz. What are the true advantages of this higher frequency, if they even exist?...
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2answers
2k views

How to overcome clock stretching on I2C

I have the clock stretching issue on my I2C line, attached is the below snapshot of it.. I have a Kinetis K64 board communicating to a MAX7304 port expander at 400 Khz. Should I get the driver ...

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