Questions tagged [clock]

A digital signal that goes high and low at a specific frequency.

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104 views

How to accurately measure 16MHz clock with Oscilloscope

I have a small problem trying to make a 16 MHz signal with a scope with 100 MHz 1 GS/s. I can't seem to be able to read the square wave from the MCU clock, see results on the attached picture. I ...
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51 views

RTC time is not kept in Stm32f103 by vbat

I am using stm32f103c8 and External Clock Crystal (LSE). I connected the Vbat with a 1220 coin battery. But when I turn off VDD and turn on the micro again, the time and date are all zero. Why time is ...
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1answer
66 views

Need to level shift, buffer, and distribute a long distance, a 1.28 MHz signal

Not sure how to tackle this issue. I have a 1.28 MHz digital clock signal with 0 = 0V, 1 = 1.5V. I need to buffer it and split it for distribution, some of the outputs will travel approximately 100 ...
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2answers
65 views

Custom waveform in hardware

I need to create a custom square wave at the hardware level. It's a 3.3 V signal at 100 kHz but the high portion of the form needs to be 9.78 MicroSeconds and the low portion needs to be 220 ...
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13 views

System clock reference input path for AD9544

According to the datasheet of AD9544, I have made the following schematic for the system clock input: R1 = 150R R2 = 330R However, I discovered that my TCXO deliver an 0.2Vdd - 0.8Vdd output (https://...
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51 views

What is the difference between source-synchronous and source clocked signals in DDR4?

Main signals comes under the source-synchronous group are data, ECC and strobe lines. My understanding about source-synchronous signal is that all of these signals would be latched on both edges of ...
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1answer
25 views

Microcontroller internal Clock frequency tolerances [duplicate]

I am having this microcontroller - S32K142 64 Pin 5V Core voltage Microcontroller Reference Manual I want to use the FIRC and want to see the frequency tolerance of the FIRC. Can someone help to find ...
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36 views

SPI connection is not working

I am trying to establish an SPI connection using the Nucleo-F030R8 board but there's no signal coming out. How do you start the connection? I did the configurations using STM32CUBE MX software and ...
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43 views

What is the simplest (standard?) way to add a second clock phase that *precedes* the main clock by 90°?

My saga with the 74LS670 4 x 4-bit dual ported level triggered latches continues. I used to have a simple clock which I could run with either a tunable astable multivibrator, or with in single-step ...
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1answer
51 views

VHDL: How to only update register at rising edge of the clock?

I have a counter called lastelem_reg. At the rising edge of each clock, it should check whether another signal enqueue is HIGH. If it is, then lastelem_reg will be incremented by 1 in the next clock, ...
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3answers
84 views

Positive edge detection triggers on negative edge too

I have 74LS170s and 74LS670 register files which have the trouble that they are not edge triggered but like SRAM accept data for the entire duration of the write gate being low. So, I have the ...
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1answer
29 views

LTC2311 CMOS SPI connection with STM32

I am currently using LTC2311 as ADC with CMOS setting in my circuit. However, I cannot seem to get any output out in the microcontroller (I use the STM32 Nucleo development board). My question is that ...
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3answers
101 views

Which libs to use with a STM32F103C6 microcontroller? [closed]

I'm very new with ARM microcontrollers and I've been doing a lite lecture of about 4 books to know how to configure this devices to start programming them. First I did a reading an how to use mbed but ...
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1answer
74 views

What is Symbol Clock Frequency?

I came across the term Symbol Clock Frequency in this Intel programmer reference manual (P131). I could not find what the symbol clock frequency actually is in the manual or online and thought it ...
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3answers
135 views

Why does my crystal resonate at 4 times the specified frequency?

I have been experimenting with oscillators this week. And building a computer clock. I got two crystals, one at 2 MHz another at 4 MHz. simulate this circuit – Schematic created using ...
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2answers
78 views

50MHz clock level shifting from 1.8V to 3.3V using IC

I have a 50MHz 2ppm TCXO that I need level shifting from 1.8V to 3.3V. I looked for solutions here and decided to use a single IC solution rather than using a mosfets because I'm not confident enough ...
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2answers
76 views

Running VHDL process off an input clock higher than the FPGA clock?

I have the following dev FPGA board: Altera Cyclone II EP2C5T144 FPGA Dev Board This FPGA has a 50mhz clock. However I want to interface with an external FTDI device that runs at 60mhz. I am driving ...
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SDC: constraining same source, different frequency clocks

Let's say I have a master clock ("m_clk"), which is divided by 2 (using enable to a clk-gater), giving generated clock: "d2_clk". Both clocks go to separate muxes, with different ...
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17 views

Trinket M0 PWM ValueError: duty_cycle must be between 0 and 65535 inclusive (16 bit resolution)

I'm trying to control a servo motor from a Trinket M0. My circuitpython code is: ...
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1answer
66 views

Does dividing a clock increase its jitter?

I want to have my microcontroller and ADC using a clock derived from the same source in an effort to avoid intermodulation effects. All clocks are under 50 MHz. The maximum SNR out of an ADC is ...
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1answer
33 views

Outputting correct data on shift register with clocks tied from microcontroller

I want to be able to output correct data from the microcontroller to the 74HC595 shift register without using the clock lines separately. This schematic matches my ideas for 16 bits of data: The ...
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1answer
35 views

SyncE over wireless?

Doesn't look like "Synchronous Ethernet" exist over wireless like it does on wired. Is there any technical reason for it not existing? On wired, Synchronous Ethernet transfers a 125 MHz master clock ...
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1answer
40 views

Parallel Diode in RC charging circuit

When button is pushed , active low RES pin is activated till Vc reaches 2.5 Volts. I have two questions here 1. What is the role of Diode which is connected reversed biased? 2. Which loop capacitor ...
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400 views

Ways to observe clock signal of an STM32 MCU

Is there a nice way to be able to observe the clock signal in an oscilloscope to validate my settings for clock speed? After setting it to 168 MHz with PLL for an STM32F407VGT6 MCU let's say.
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29 views

TIVA TM4C123G check clock frequency with oscilloscope

I'm trying to configure system clock in the TIVA TM4C123g board. I'm aware that this clock signal goes to a pin called OSC0 which, according to this, is the pin ...
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1answer
75 views

Difference between always @ block and @ statement in SystemVerilog

I am new to SystemVerilog. I have not across the statement @(posedge clk) before. I would like to know how this statement is different from the ...
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2answers
79 views

Hardware-Software synchonization with clock in a microcontroller

From what I understand, there is a clock in a micro-controller, and every little task is executed at a clock pulse. Can two or more actions be performed simultaneously (In the same clock pulse)? For ...
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29 views

How to choose between different equivalent PLL/divider configurations?

If there are multiple ways to get the required clocks for a given CODEC, how do you choose between them? For example, if a CODEC can accept 64fs, 128fs, 256fs, and has an internal PLL that can ...
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1answer
132 views

PROTEUS 8.9 version Error: No model specified for CLOCK#000C. (Fast help pls.)

I did everything on my project, but I am getting these errors. How can I fix it? ...
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2answers
36 views

Timing specifications in a communication protocol

I am having this I2C EEPROM Chip from Onsemi - CAT24C In table 6, AC Characteristics of the datasheet, only the Minimum time is provided for the SCL clock low and high period. My questions : Not ...
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34 views

STM32WB - sensor data sent via BLE and saved on SD card (SPI)

I have an STM32WB and I am trying to get the data from some pressure, temperature and humidity sensors through DMA and send them to my Android via BT, while at the same time saving it as well on a SD ...
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70 views

How many devices can be daisy chained via SPI/I2C?

How can we determine how many devices can be daisy chained from a datasheet
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1answer
30 views

VPX Radial Clock Vs Bussed Clock

I'm learning some concepts about OpenVPX. One thing I am a bit confused about is the notion of a radial clock versus a bussed clock. I'm not getting many helpful google hits. Can someone explain the ...
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1answer
41 views

How does a micro interpret high freq rf signals from an antenna

If an antenna is receiving a frequency higher than the clock speed of the cpu, then how is the cpu able to interpret the data being received by its antenna?
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Accessing odd address memory locations in 8086

I am a beginner in microprocessors. Apologies if my question is too naive. The memory section of the 8086 processor is divided into two segments: even and odd to allow the CPU to fetch 16 bits in one ...
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1answer
80 views

Calculate C and R in a CMOS Crystal Oscillator

I stumbled over this simple solution to drive a crystal oscillator, but I need to connect a 25.17MHz crystal instead of the 10MHz in this schematic. How do I calculate R1 and C for a given frequency f(...
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1answer
53 views

What is the Purpose of the Clock?

There are many examples of logic circuits that have the clock signal, such as the JK flip flop and the clocked SR NOR Latch, but I still wonder what is the purpose of the clock. Why do people think of ...
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146 views

Does a personal computer have just one clock and where is it?

I want to check my understanding which I have gleaned from several sources, many of which seem to be out of date and many of which are conflicting. My understanding is that there is just ONE CLOCK ...
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1answer
41 views

Clock generation on FPGA pin

I am trying to interface an FPGA to a DAC device. The DAC has a JESD204B interface so the data clock is embedded in the serial data lane (it uses the 8B/10B encoding). The DAC still needs a clock ...
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2answers
68 views

Can an FPGA PLL lose lock if it is supplied with a stable input clock signal?

In an FPGA (Intel) design I have a PLL that is provided with a stable clock from a clock module on the PCB. The design is as shown on the figure below. The PLL has a lock indication. After the FPGA ...
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3answers
59 views

crystal oscillator as backup (or with sync)

I have a device that generates a 49.152MHz frequency, but depending on its status it can cut it off from time to time. This frequency synchronizes my MCU's audio devices, but it must never be stopped. ...
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56 views

Driving a Seiko Slave Clock

I recently acquired a Seiko slave clock, like the ones used on ships. It has 2 coils, one for advance and one for retard. I'm intending on making a master clock for this out of an RPi or ESP32 or ...
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2answers
36 views

Master-slave flip flop without gate delay?

It seems like a master-slave flipflop always has around a 2-gate delay between the Master and Slave sections of the flip flop. For example: My question is what would happen if, theoretically, there ...
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143 views

How does one get ticks of a clock from an atomic clock's microwave signal?

I understand that in an atomic clock there is a microwave signal that is locked to the frequency of the atomic rotation. However, if one wants to extract time ticks from the microwave signal (shown ...
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1answer
45 views

Can you have different clocks working at different intervals to operate a flip flop?

Is it possible to have two clock signals driving a JK toggling flip flop, in which both signals are connected by a XOr gate so that the flip flop only works on either edge of either clock? If possible,...
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2answers
36 views

MIC1557 clock frequency constantly increases. Why?

I'm trying to get a 19.2 KHz frequency out of the MIC1557 clock generator. I managed to get close enough (enough for my application) to this frequency with off the shelf components. The shematic is ...
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1answer
32 views

Doubt regarding static timing analysis - setup time check

I was reading J.Bhasker's STATIC TIMING ANALYSIS book. In that book, he tells that when launch flip flop launches the data & while capture flip flop is capturing data, he says that We now ...
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106 views

20MHz clock signal over several PCBs

I am running a 3.3V 20MHz clock signal for LED drivers over 10 PCBs that are connected to each other over short cables. Overall, the clock signal must travel 1m. Is this even possible with a 20MHz ...
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85 views

Is a typical register rising edge or falling edge? [closed]

I'm using Logisim to build a 1-bit CPU. However, I am having issues with timing the registers up with the clock. In a CPU, should registers be rising edge or falling edge? Or, could they be something ...
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How to pick clock speeds for a CS4270 codec?

I'm in the process of designing a circuit which includes a Cirrus CS4270 codec and a STM32F405 running as a DSP. I'm trying to define my max usable settings, which would be running at Fs = 192kHz. I'...

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