Questions tagged [clock]

A digital signal that goes high and low at a specific frequency.

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Increasing system clock frequency on STM32F303 drops I2C clock proportionately - why?

I'm trying to figure out a weird little issue I've discovered while debugging another element of my code. I've got a STM32F303K8 reading and writing to an I2C peripheral. The I2C clock speed is ...
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1answer
42 views

Acceptable designing two clock generators using single package?

The circuit I usually use is Pierce oscillator: (pic source) I have always had single system clock in the system, built on single HCU04 chip. Now I need two: 6*NTSC and 4*PAL - frequencies not ...
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2answers
293 views

Crystals, capacitors and W5100

Background: I have built a number of devices based on the W5100 chip, all them were (are) working more or less decently. However last batch currently in testing show faulty behavior - almost all of ...
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1answer
113 views

MachXO2 DDR and PCLK routing issue

I'm doing a project in which I use DDR interfaces to transmit and receive data between different FPGAs. The FPGA transmitter will send data at 125 MHz and the receiver will use 250 MHz to sample the ...
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71 views

Intermittent control signal injection clock sync

I have a big challenge in my design to overcome: I need clock frequency accuracy of <0.2ppm with incredibly low power consumption. What we are doing currently is, using a 3G transceiver' baseband ...
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1answer
611 views

PIC32MX can't get 80 MHz Clock from Internal RC OSC

I am using PIC32MX795F512L with the internal RC oscillator. By changing the settings of the config, I can get to 60 MHz max. But I can't get to 80 MHz. When I change the config for 80&#...
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32 views

Driving a Seiko Slave Clock

I recently acquired a Seiko slave clock, like the ones used on ships. It has 2 coils, one for advance and one for retard. I'm intending on making a master clock for this out of an RPi or ESP32 or ...
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23 views

How to pick clock speeds for a CS4270 codec?

I'm in the process of designing a circuit which includes a Cirrus CS4270 codec and a STM32F405 running as a DSP. I'm trying to define my max usable settings, which would be running at Fs = 192kHz. I'...
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87 views

Equipment and approach for performing a long-term measurement of clock signals

This is a follow up question for the circuit I designed with the inspiration from here. The circuit works but over time there appears to be some clock jitter or skew. I am interested in an approach to ...
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75 views

Produce a clock out (5 MHz) with a counter and a clock in (50 MHz)

I'm trying to solve previous years' tests in logic design and there's this question that I can't really solve.. So, it gives me an 8-bit counter and a clock in (clk_in) of 50 MHz and it asks to ...
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83 views

Clock divide by 5 - All ICs obsolete?

I've got an obsolete part in a design (SY100S839VZG) that is being used to take a single 100MHz clk and divide it down into two PECL p/n pairs. For the life of me, I cannot seem to find a single ...
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29 views

How can I test wether my OCXO VCO is working fine?

I recently bought a PTOC32227 OCXO (datasheet) from eBay (secondhand). It is supposed to output a square wave at 10MHz. However, it is a part of a bigger circuit that is not working properly and it ...
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2answers
78 views

Delay a clock to give time for the input to settle?

I have a numerical keypad that I want to feed into a shift register to display the last three numbers I have pushed. My numeric keypad has ten lines, each of which connects to a common on a button ...
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2answers
228 views

Digital Alarm Clock in Multisim. (Home Work/ Final)

I apologize for the schematic. I know it is not the prettiest to look at. My clock runs slow. I know this is because of my 555 timer. I was off somewhere in my calculations and ended up with a 70hz ...
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1answer
268 views

Generate clock jitter in a testbench

How would you generate clock jitter in a testbench? I have seen these two ways, but I am not sure if they are the best ways: ...
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1answer
155 views

Timing Constraints for Forwarded Generated Center-Sampled Clocks?

Problem Description I am trying to figure out the "correct" way to constrain (in .xdc format - this is in Vivado) a forwarded source-synchronous clock that is generated (by division) from the ...
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72 views

Differential Clocking resistor and capacitor choices

I am working on generating a 2MHz differential clock signal for a DDS chip. I have been given a PCB with a design that I am unsure can work or what the thought was behind it. If anyone could help with ...
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1answer
233 views

Crystal reference and capacitors for w5500

I'm selecting the caps for the crystal oscillator of the wiznet W5500. The standard Load Capacitance for 25Mhz crystals is 18pF. I found out that the hardware guideline claims for a Load Capacitance ...
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106 views

LVDS CLK Input Appropriate Here?

I'm working with an MCP37231/21-200 that requires a differential input for the clock. I need to know if I can use an LVDS input to drive my clock. The output clock is specified to have LVDS ...
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917 views

Clock Frequency for 4 digit 7 segment display in VHDL

I am using basys 3 and VHDL to create a stopwatch and I need to do it for both the 7 segment display of the basys3 itself and for a external 4 digit 7 segment display. I am given the clock divider ...
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1answer
299 views

How to generate a continuous clock from one that periodically turns off?

I have a LVDS clock signal that is gated about ever 30us. This is a MIPI D-PHY clock that switches from HS mode to LP mode when the data lanes go to LP mode (and are auto-clocked). The problem is that ...
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237 views

STM32F4 OC Clock Jitter

I am using STM32CubeMX to configure an STM32F4 to output a clock signal using Timer 3, Channel 4 on PC9. I have read in the datasheet PLL section that jitter shouldn't be more than 15ps RMS but I am ...
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182 views

pragma directives to set frequency for dsPIC33

currently I set the frequency of my dsPIC33EV with following code: ...
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99 views

TDF transmitter to arduino

1) I have a project to build a time clock based on the TDF signal on 162kHz, from Allouis, France. The time coding is similar to DCF-77 so I will send it to an Arduino with proper code. I managed to ...
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159 views

PCB layout help for MEMS oscillators and clock drivers

I have this SIT8009 MEMS oscillator at 125MHz frequency (also the same with an OSC52 from SiWard at 25MHz) followed by a 1-to-4 clock driver to distrubute the clock to multiple ICs. When layouting, I ...
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155 views

Can't get PIC16F1764 to run at 32 MHz INTOSC

I have a problem with a PIC microcontroller. I can't get it to run at 32 MHz. Via page 78 of it's datasheet (document number DS40001775B). The steps for selecting 32 MHz FOSC operation are clearly ...
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300 views

Nordic Nrf51822. Where to get the clock source for external SPI Slave

I need to connect an external SPI device . Cannot figure out where do get the Clock source for Nrf51822. The datasheet says: "The GPIOs used for each SPI interface line can be chosen from any GPIO on ...
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200 views

Transformerless Realtime Clock Issue

I have an issue with designing a Real Time Clock by using Transformerless power supply. I don't use RTC IC but I use Microchip PIC instead and 32kHz clock. I use battery of 3.3V for backup supply. The ...
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785 views

Why am I unable to use a pin marked as GCLK in the datasheet as a clock resource, when an identically-marked pin works, on a Spartan-3E?

I am trying to create a sequential circuit on a development board with a Xilinx Spartan3E XC3S500E in an FT256 package. The board has a 50MHz crystal oscillator connected to pin B8, which is marked as ...
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1k views

Atmega32 can't verify after setting correct fuses for external crystal. HELP

I am having trouble with some Atmega32A's purchased off from eBay. The MCU's does not seem to be fake as they are functioning properly. I am experiencig the following problem: I want to use external ...
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332 views

Frequency locked loop for input jitter rejection

I have an application where I want to multiply from a xtal oscillator at 32KHz to a system clock of 40MHz. A standard PLL isn't going to do the job, because the 32KHz jitter is measured in ns. Since ...
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2k views

stm32f2xx HSI configuration does not work correctly

I'm using below settings (in SystemInit function) to configure a STM32F215RG MCU to work at maximum speed (120MHZ) with USB support: ...
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891 views

8284 Clock Generator

I am studying the 8284 clock generator and see how it works with the 8086. But before I connect the two chips together, I want to verify the 8284 first. So I placed the 8284 on the breadboard as ...
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1answer
22 views

Doubt regarding static timing analysis - setup time check

I was reading J.Bhasker's STATIC TIMING ANALYSIS book. In that book, he tells that when launch flip flop launches the data & while capture flip flop is capturing data, he says that We now ...
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50 views

Unexpected result reading pin on clock rising interrupt

What I try to achieve is a simple one-way communication between two MCU's (ATTiny85's to be exact) at 16Mhz. This is just a start, to figure out it can be useful, very basic and needs to be very basic....
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1answer
53 views

Changing frequency of input clock port (FPGA)

I', using xilinx ultrascale FPGA (xcku025-ffva-1-a) I am referring to application notes provided by xilinx. I am going to use the reference code provided in xapp1315. In this reference code, an ...
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26 views

AT91SAM7S512 Oscillator, GPIO, & Reset questions

I just need some clarification of my circuit Oscillator: So for my circuit I want to be able to program it via USB, the datasheet gets a bit confusing to me tho. If I read the datasheet correctly I ...
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2answers
53 views

pic16f877a problem in timers with proteus simulation

I used PIC16f877A at proteus to do timer interrupt. The code is pretty simple it has nothing to do rather than setting the timer1 registers , the while(1) loop is ...
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49 views

Turn a positive clock edge into a negative pulse to make a 74LS170/670 register file synchronous

This is a follow-up o Why did they make the 74x170 (670) register file asychronous, no CLK input?. I want to use that "register file" for my project, but I need to make it behave properly as a ...
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1answer
78 views

4-bit memory serial to parallel memory register circuit question

I am building a 4-bit serial to parallel memory register and I feel like so far I have gotten things right, but I'm unsure of where to connect the CLR connections. Could someone have a look at my ...
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52 views

Capacitor on clock line of TFT display

Short version (can provide more information if wanted) we have a display (TFT with TTL driver) that we control via PIC32 and Epson Display IC. The supplier changed their driver which should have been ...
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1answer
25 views

Logisim Flashing button

How can i create a button with a clock that is connected to a LED that the LED turns on when the button is pressed but even if you keep holding it it will turn off
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30 views

comparing between different phase detectors

I implemented two architectures of phase-frequency detectors and I'm interested to compare between them. (I'm open for extra architectures that might solve problems that I'm not discussing here) I'...
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58 views

Rising edge detector behavior

I was looking at this StackExchange question: Why does this rising edge detector using a capacitor and a resistor work? I ran the simulation and I'm confused by the behavior. On the rising edge of ...
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1answer
54 views

Clock Multiplier / Clock Boosting

I was reading this paper "A 10 b, 20 Msample/s, 35 mW Pipeline A/D Converter" by Cho and Gray from 1995. https://ieeexplore.ieee.org/document/364429 In it, they describe a clock multiplier circuit ...
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Programming an ATmega644 with 32.768 kHz external clock and USBTinyISP

I accidentally changed the fuse bits on my ATmega644PA chip so that it is expecting a 32.768 kHz signal in the XTAL1/XTAL2 inputs. I am using the a USBTiny programmer (the Sparkfun AVR Pocket ...
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56 views

CS5340 does not generate clock signals correctly

I am trying to build a sound input for Raspberry Pi 3B using CS5340-CZZ as an ADC. I am basically using it according to the typical connection diagram in its datasheet, where I have a signal from a ...
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61 views

Choosing clock buffering circuit

The modular 5V-powered design's module is having two output clocks (21 MHz and 3.5 MHz) to other modules in the system. I am looking for the best way for buffering these signals so that they would be ...
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110 views

CLK signal on DAT0 line on SD protocol?

I'm facing some problems in the initialization stage of the SD protocol on a custom board, specifically when sending the ACMD51 command and reading the Status Card ...
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1answer
42 views

Pulse train profile generator for stepper drive step/dir input

All, I am trying to create a circuit to control a stepper drive step/dir input. I'd like to generate pulses starting at 1kHz and ramp up to a 10kHz peak, then decelerate to 1kHz until motion is ...