Questions tagged [clock]

A digital signal that goes high and low at a specific frequency.

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1answer
130 views

Why double synchronizer alone is not enough for multi byte transfer between two clock domains?

When one bit information is transferred between two different clock domains, we use 2 Flip-flops or double synchronizers. But when we transfer multi bit signals across two different clock domains, why ...
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1answer
40 views

Relationships between instruction execution and clock cycle in modern CPUs

I have some misunderstanding about what clock cycle really is. I generally understand a schema how CPU processes an instruction. Intel manual describes the schema for Intel NetBurst architecture as ...
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4answers
4k views

Two wire vs. three wire serial interface for RTC

I'm looking to choose an RTC for a project I have in mind. I have the following options (linked to datasheet): DS1307 DS1302 The main difference seems to be the communication protocol. The DS1307 ...
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3answers
141 views

Is it possible to get complementary clock output from a clock generator such as a 555 timer using simple digital logic?

I'd like to get complementary output from a 555 timer. I've seen previous suggestions of using a D Flip Flop, which is a fine suggestion, however that halves the frequency at the outputs of the flip ...
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1answer
34 views

TLC5926IPWPR Clock width

I'm using the TLC5926IPWPR in a design. It uses an SPI interface. The TLC5926IPWPR chip is on a separate PCB than the MCU that is controlling it. The Clock and SDO pin must go through a cable about a ...
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1answer
3k views

Why does this rising edge detector using a capacitor and a resistor work?

So in this video from Ben Eater he makes a rising edge detector using a capacitor and a resistor like the one below. simulate this circuit – Schematic created using CircuitLab In the video Ben ...
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1answer
41 views

Pulse train profile generator for stepper drive step/dir input

All, I am trying to create a circuit to control a stepper drive step/dir input. I'd like to generate pulses starting at 1kHz and ramp up to a 10kHz peak, then decelerate to 1kHz until motion is ...
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0answers
211 views

Frequency divider in Verilog

I am trying to implement a clock divider with a 2^8 bit different frequencies. I understand that i need a counter that will count and once it elapses change some variable state and based on that ...
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1answer
60 views

Digital sample and hold synced with a CLK

So I though this should be pretty straightforward, but apparently it's not. Supposed we have a digital async input signal and a CLK. I want to sample the given input signal on every rising (or ...
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3answers
129 views

Is there a low voltage LED alternative?

I am trying to create a tiny little watch that is supposed to run off a coin cell (because it is so tiny) and basically just a microcontroller with a 30ppm 1Mhz oscillator that counts upwards. The ...
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3answers
186 views

What's wrong with my interpretation of what should happen in the circuit and what's happening? [closed]

Here is what I expected to happen: A B C D 0 0 0 0 1 0 0 0 1 1 0 0 1 1 1 0 1 1 1 1 0 0 0 0 ... Initially, suppose all flip flops have output 0. Then, Q' of the ...
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3answers
157 views

Build a nearly 50% duty cycle, adjustable oscillator using D-FF

Starting from an example circuit, I'd like to simulate and physically realize a D-FF circuit that generates a 50% duty-cycle clock. Scope of this: Clock generator for a test circuit Out 0-5v I don'...
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48 views

PIC I2C clock related problem

I am trying to make an I2C communication with a device by using PIC18F26K83. I use 8 MHz MCU clock. While trying to set I2C clock these options: Use 8 MHz MCU clock & HFINTOSC for I2CxCLK ...
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0answers
48 views

Strange CLK-similar signal

I'm reverse-engineering the data bus inside a projection clock to find out how to drive the projection without the clock. I use PulseView with a logic analyzer. What I (think to) know so far: It ...
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1answer
136 views

Full Adder driven by clock [FPGA/VHDL]

I've got Ripple Carry adder (26bit) made from scratch. ...
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2answers
417 views

555 timer digital clock

How would you go about connecting a 555 timer to a circuit with a 16x2 LCD display, which is already connected, to create a digital clock that counts the time? Do you have a sample of how this code ...
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5answers
4k views

Why is there a PLL in CPU?

I read that PLL are used in CPU to generate the clock, but I can't understand why. I don't really have any guess of why this is.
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4answers
654 views

Resetting two CD4017 counters simultaneously, only one resets

I am working on a simple 24-hour clock based on the CD4017. To reset when the clock reaches the 24th hour, two diodes are used to produce an "and" logic when the 2 digit and 4 digit LEDs receive a ...
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0answers
31 views

Can I use a single clock line for 6 parallel addressable rgb data lines?

I am making a PCB with the dimensions of about 60 (height) mm by 320 mm (width). The PCB contains 5 Letters and 1 logo. The idea is to have 6 datelines in parallel. This way I can have different ...
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2answers
141 views

Why Positive-going clock transitions used in certain ICs

Why do certain ICs like 74ALS174 use an inverter so as to make a Positive-going clock transitions occur instead of Negative-going ? Why can't we just save expense of an inverter by removing it and ...
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1answer
75 views

Can I bridge output IO's from an FPGA that is driving a clock source to drive longer tracks?

Scenario I have a motherboard and a daughterboard that couple through two headers. The motherboard has a 16x16 array of ultrasound speakers each with their own drivers, that works. I drive them ...
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1answer
298 views

Does this clipped-sine oscillator need a buffer?

I'm considering using an Abracon VCTCXO, the ASVTX-11-121-19.200MHz-T to run an AT89LP428. I'm trying to make sure that they're interoperable, but the Abracon device doesn't say anything about the ...
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1answer
90 views

Clock synchronised to pulse

I'm thinking about 1Mhz clock signal synchronised to external random pulses (eg. rising edge). Before pulse event clock can be running or stopped. After every pulse, it should run in same fixed phase ...
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158 views

Frequency multiplier from kHz to MHz

I'm not familiar with electronics at all, and would like to get some ideas to implement frequency multiplication of LVCMOS. I want to multiply the frequency in the range of 250 kHz by a factor of 10 ...
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2answers
6k views

DDRx Memory: Memory Clock vs I/O Bus Clock?

When referring to DDR/DDR2/DDR3/DDR4 memories, I am not able to understand the difference between memory clock and I/O clock. As per: https://en.wikipedia.org/wiki/Double_data_rate DDR-200 - Memory ...
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2answers
111 views

STM32F405 Setting Clock Freq Less than Max 168 MHz

For STM32F405 the max system clock frequency is 168 MHz. I want to run it at marginally lower frequency only for the sake of safety and reliability because my application will run non-stop through out ...
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0answers
26 views

Tracking ADC Control Logic Not Counting down, only up?

I'm working on trying to build a "tracking" type ADC from individual components. Shown below is my schematic using the parts available in Multisim. The design is based on the 74LS191N 4-bit Up/Down ...
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3answers
91 views

Deciding which assembly is more common positive edge detector

I know of two circuits which can act as edge detector: A clock connected as a voltage source across a RC component where resistance is composed of a diode and a resistor and this in series with ...
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0answers
45 views

AES Sub Byte subsitution in four clock cycles

I am trying to implement AES in verilog using 32-bit data path, but I am not able to subsitute the 128-bit in just four clock cycles, my code requires five clock cylces, Here is the small portion of ...
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1answer
71 views

Zero-R Resistor on XTAL pins

Looking at the schematics of the STM32F4-Discovery board page 28, whose screenshot is attached below.. there is a Zero Ohms resistor 'R25' which is shown in the circuit with the Crystal. And there is ...
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1answer
109 views

MASTER Clock output from one micro to another vs independent clock src

I have a Small STM32 Nucleo board where the on-board ST-Link debugger has an 8mhz crystal for the debugging microcontroller. That microcontroller is set up to output its MASTER clock, in other words ...
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2answers
201 views

ATmega328 - two clock outputs

I'm using an ATmega328P to provide a software-selectable 2, 4 or 8 MHz clock to my home made SBC. This works just fine. However, I am adding a programmable sound generator (PSG) to the board and it ...
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3answers
334 views

Simplest shift register test circuit - clock

I'm looking for the simplest way to test the operation of a 74HC595 shift register without complex circuitry. Currently (on a breadboard) I have a 47K SIP resistor in a pull-up fashion connected to ...
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3answers
224 views

Why include frequency dividers in this PLL circuit?

I found replicated in few sites this PLL diagram and I'm wondering why the authors included frequency dividers on the input and output signal, since the two signals to be compared have the same ...
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3answers
648 views

555 Clock Circuit - how to choose resistor value? [closed]

I need to design a 555 clock circuit to output a clock pulse of a specific frequency. The circuit I'm using is this one (from here): I've used this circuit before and it works fine but the website ...
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4answers
588 views

What is the meaning when we say power of circuit having a clock frequency 100Hz is 2W?

When we say clock frequency is 100Hz, then there are 100 clock pulses in one second. So when we say power is 2W, is it 2W for 100 cycles or one cycle ? Or is it anything else?
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2answers
51 views

What does an internal or external loop filter do for this clock IC?

For the CDCE62005 clock generator IC, what does the internal or external loop filter accomplish? Thanks in advance for any input. Page 44 of datasheet, and pages 1-2 and 6 or the eval board user ...
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1answer
121 views

Can I use an unmodified ST Nucleo-F303RE to develop USB devices?

I want to use my Nucleo-F303RE to develop firmware for a USB HID. The stm32f303ve data sheet states in section 3.25 that for the USB peripheral to work, the MCU needs a HSE crystal oscillator. ...
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1answer
146 views

SPI clock selection

Using STM32l476 controller. Master is running at 30 MHz and slave is running 15 MHz. In SPImaster, clock should be system clock/2. In slave, clock should be system clock/4. Question: My ...
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2answers
572 views

How to use 1PPS to Synchronize ESP32 Clocks and Peripherals

I've read a few posts (example) about what the 1PPS signal is and how it can be used at a high-level, but I'm still not sure how to actually implement it on a PCB schematic to sync up with my ...
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3answers
175 views

Getting CPU clock signal out of computer (as to measure externally) [closed]

I've been searching on the internet some clock generator module capable of reaching up to 1GHz, when I just realized that the machine I'm using to search has one CPU with its own 2.5-3.0 GHz clock... ...
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2answers
103 views

Are there still programmable clock synthesizers with single ended TTL output leves (in 2019)?

I'm looking for a clock synthesizer IC that can drive my vintage 5V NMOS CPU in the range of 5 - 50MHz. The granularity would preferably be in the range of 100kHz or less. All I can find when ...
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3answers
1k views

Estimate electrical frequency from clock shift

About 6 months ago I installed a solar power system with 2 Tesla Powerwalls for backup. Today, we got to test out the system with a power outage from an ice storm in the southeast. (We are still on ...
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1answer
175 views

Pausing a clock signal generated by 555 timer

I am planning to make a simple integer adder/multiplier which needs a variable frequency, comparatively slow clock (around 1 to 200 Hz) for demonstration purposes. I used the following generic 555 ...
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3answers
271 views

Inverter feedback when converting clipped sine oscillator signal to square wave

I inherited a design that uses the following circuit to generate a 40MHz square wave clock signal: KT2520K is a TCXO that outputs a clipped sine wave and the inverter has a peak output voltage of 3....
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3answers
8k views

How do GPS satellites refresh their clocks

How do GPS satellites keep their on board clocks accurate? I assume that they need to get update from a base station. But how do you make sure that after the update all the satellites are synchronized,...
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2answers
157 views

Are there special rules for voltage division of a high speed clock?

High speed signals require special care in PCB layout to prevent high speed effects like ringing and overshoot. This obviously applies to clock signals as well. Provided that one has a high voltage ...
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5answers
2k views

Can wireless communciation be synchronous?

I understand that in synchronous communication, the sender and receiver need a common clock. Is it possible that wireless communication be synchronous? Can some common clocking element be there for ...
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2answers
66 views

Can I use MCU's internal oscillator when communicating with GPS and cellular modules?

Can I use MCU's internal oscillator when communicating with GPS and cellular modules? I want to avoid connecting external crystals for the MCU since they generate noise, extra components, extra costs, ...
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1answer
83 views

What happen to a dff(flip flop) without input?

I have this question but I don't know what happen to a dff without an input is it always 0 ?? like this picture below the 2nd dff hasn't any d ??? Also, if someone can draw the answer of the question ?...

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