Questions tagged [clock]

A digital signal that goes high and low at a specific frequency.

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Overshoot and undershoot on clock signal

I have created a 50% duty cycle, 8 MHz clock signal on the ATmega32, 0V to 1V. What I see when measuring this clock signal with the oscilloscope is overshoot and undershoot of about +0.2V on both ...
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In clock recovery, how is the recovered clock used to recover data?

I've been refreshing my memory on clock recovery, and I've hit some issues trying to understand how the recovered clock can be practically used to latch data bits from the input data stream. For ...
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Reconstructing Clock for Serial Signal

Suppose that I have a serial signal (example below), which is transmitted without an accompanying clock signal, I would like find a circuit (using discrete components / ICs, possibly an FPGA, but not ...
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Why does `RCC_GetClocksFreq` return different results than I expect?

I have a STM32F427 MCU with a 8MHz HSE crystal. I am setting up the clock as follows: ...
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1answer
200 views

I2S Clock in Audio Codec on dev board, how is this working?

I'm using a dev board, the keil mcb4300. In the schematic, the audio codec UDA1380HN has the BCKI going to the SYSCLOCK. According to the codec data sheet: BCKI: bit clock input SYSCLOCK: system ...
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Generating i2s Clock Signals

I am trying to design a Pi Hat to integrate my Raspberry Pi 3 for use as an automotive head unit. I have a Texas Instruments TAS6424 and some supporting components, and am trying to design a DAC PCB ...
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473 views

Using both clock edges in an FPGA design

So, after getting some advice from some good people here, I managed to put together my first (very modest) FPGA design. It is basically just a few registers and counters, and only runs at a few MHz, ...
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Odd number frequency divider

Important note: You are not helping me do my homework. This is for a competition for engineering students, that encourages you to "use your network" ;) I've got this pattern for a frequency divider ...
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736 views

How to set external clock value for STM32F1?

I creating a project with the microcontroller STM32F101C8t. This microcontroller has an internal clock of 36MHz. My question is how to correctly set the external clock value, ie what crystal value ...
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Divide clock frequency by 3 with 50% duty cycle by using a Karnaugh Map?

In this document, On semiconductor describe how to design a divide by 3 system using a Karnaugh Map: ...
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493 views

Frequency and Period of a JK flip-flop circuit [duplicate]

Reposting this question from Electric Engineering. Wouldn't normally do this but I have to figure out this concept by tomorrow. Thanks in advance for any answers. I am currently working through the ...
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Jitter in 'ppm' and 'ns'

In many datasheets clock tolerance is in ppm and in some other it is in ns or ps. What is the difference in giving clock tolerance in ppm and ns/ps. How it can be converted from one unit to another?
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When a VHDL code with a rising edge clock is synthesized, what happens at the falling edge?

I'm a newbie to VHDL and I'd really be grateful if someone could help me solving this question which has been bugging over the last few days. I don't have a code for this. Assuming, if there's a code ...
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How do processors control their clock speed?

I recently came across an STM processor with 2 oscillators on the circuit - I suppose one for high-speed operation and the other for low power. For something like a desktop processor where the clock ...
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89 views

Easy circuit for “nested” triggering

I need a trigger circuit that gives several high pulses for an "out_0". After 5-6 pulses from out_0, it then gives one high pulse for an "out_1". I don't need any circuit that's large or has high ...
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Create a pulse that is active from ~0.3 to 0.4 times the clock period

I'm sorry if the phrasing is somewhat weird, but the question is hard to articulate. I've created an IC Sample-and-Hold where I have a hold capacitor at the output. I want to charge this capacitor ...
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2answers
404 views

Correct terminology for 'clock' that doesn't oscillate?

What would be the correct term for a clock input that isn't made to oscillate per se? In an attempt to only allow input A to have any effect on a circuit at a chosen time, one could AND it with ...
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1answer
53 views

Is a good practice assigning clk to a signal before component instanciation in FPGAs?

I am working with VHDL for Xilinx FPGAs and I am trying to create some hierarchical components. When instantiating a component B inside another component A, what clk is expected to pass to the ...
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246 views

How to connect a 4-pin OSC (crystal oscillator) to an IMU (BNO055) with only 2 pins dedicated to an external clock?

I am using the BNO055 : https://cdn-shop.adafruit.com/datasheets/BST_BNO055_DS000_12.pdf and I can't seem to figure out how to connect a standard external oscillator clock to the chip. As suggested, ...
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106 views

LVDS CLK Input Appropriate Here?

I'm working with an MCP37231/21-200 that requires a differential input for the clock. I need to know if I can use an LVDS input to drive my clock. The output clock is specified to have LVDS ...
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2answers
2k views

clock frequency divide by 5 vhdl

i want to get the clock frequency divide by 5, can i do it with integer type or i need something else to run the decimal number? ...
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2answers
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PCI-E throughput calculation

could someone please do for me the calculation of total throughput of PCI-E? The best material I could find was a Xilinx pdf that mentioned 2.5Gbps as reference value and somewhat awkward formula that ...
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549 views

GPIO and clock configuration of STM32F427VG

I am very new in STM32 projects and it is my first time writing a program with STM32. I used to program with AVR and now I should progress to STM32. I have a board with STM32F427VG on it without any ...
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Crystal oscillator on custom ATMega2560 board is at the wrong frequency

I have designed a custom board using an ATMega2560. The board works fine when configured to use the internal oscillator. The board stops working when I configure it to use the the external 16MHz ...
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230 views

Enabling external reference to HP/Agilent Signal Generator (8648C)

What is the proper way to use an external 10 MHz clock signal for an HP/Agilent signal generator (in my case: 8648C)? With my Tektronix, Rohde & Schwarz devices, internal/external reference has ...
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Clock impulse through push button [closed]

I need to store 4 bits in a shift register giving input through a push button. For which I also want to generate a clock pulse with the same push button with some delay(<100ms) so that the clock ...
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Can I use a common Clock pin on my micro-controller project instead of separate clock pins?

In my Propeller project, I have the following devices, with the related pins: DS1302 RTC SClk - IO - CE Micro SD Card SClk - CD - CS - DI - DO SPI SRAM x 2 SClk - SO - SI - CE PS2 Mouse ...
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Signal Integrity and clock waveform measurement

Where do you probe and measure the signal quality of a clock signal that has series termination? Do you probe at the end of the series resistor that is pointed towards the load? Or do you measure at ...
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237 views

How to correct voltage overshoot in clock divider output?

I am trying to make a quadrature phase divide-by-6 clock divider circuit in cadence. I managed to complete the circuit and obtained the correct waveform; however, due to some reason I am getting a ...
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1answer
110 views

How to match two clock signal's phases which are physically apart in two locations?

Suppose, I have one Tx and one Rx physically separated by the long distance with clock signals CLK1 and CLK2 as shown in fig. (say both of 50MHz). I wish to align them in phases. By that I mean, ...
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156 views

Active high, rising edge circuits update state when, exactly?

I'm very new to electrical engineering. On a recent exam, we had a circuit with two JK flip-flops connected in series with one another. The circuit is beside the point, however. Both flip-flops were ...
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resistor at external clock source line [duplicate]

im reading a arm based mcu board schematic and there is 100R resistor (R30) at external 25MHz oscillator source. What is the main reason of using serial resistor at clock line ?
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How to drive four nixie tubes with arduino?(in-14/clock)

I'm looking to build a nixie clock. I have looked online, I found some guides but many used expensive nixie clock kits or custom pcbs. I came across some threads about driving a single nixie tube with ...
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335 views

How to create discrete high voltage oscillator?

I need to increase 24 V DC to 1.5 kV DC. Using a voltage multiplier would require over 60 stages. I am considering using a few stages of a voltage multiplier, say 8, to increase the voltage to about ...
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215 views

Clock generator is not oscillating on the given XTAL's frequency

I created a PCB which needs to have a solid and precious clock source. For this purpose I used a Dual Inverter with Schmitt trigger (NC7WZ14). Now CLKI seems to generate 66kHz square signals (...
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What is the purpose of a tri-state pin in a Oscillator

I'm trying to interface this clock (32.768kHz Ceramic Surface Mount Crystal Oscillator datasheet), but I'm confused as to what to do with the tri-state pin. What is it's purpose in the oscillator and ...
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113 views

Capacitor to limit AC current, block DC current

I am interested in making a 'life' indicator for my uC, as in, "Is the clock running?". As it has a clock output pin, I was thinking of attaching this schematic to it. simulate this circuit – ...
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Potato battery not powering clock

So for a school project where we have to make a lesson plan for kids to learn stuff out of "lame" experiments, I was assigned potato clock. I could not for the life of me find a simple 1.5 volt led ...
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Serbia, Kosovo power grid row delays European clocks. Why?

According to this article (and a lot more published today on the same topic), Kosovo electricity net production balance has decreased during the last weeks. This has led to a small deviation of the ...
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Faster 8051 not taking the slower 8051 pin status correctly

I'm trying to do a rather simple data transaction between two 8051 microcontrollers using a variant of the SPI protocol. The large one is a slave and the small one is a master. The documentation for ...
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1answer
311 views

Differences between flip-flop control inputs and clock inputs

I'm studying clocked flip-flops (FFs). However, I cannot differentiate between the two terms control inputs and clock inputs. Can you tell me the differences between those two types of inputs, or ...
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287 views

How stable are temperature controlled crystal oscillators?

This question is not as obvious as it might seem. Consider this, concerning Rubidium clocks: All commercial rubidium frequency standards operate by disciplining a crystal oscillator to the ...
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1answer
500 views

SPI clock - slow frequency but fast rise time issue with waveforms

Background on the issue: I currently have an SPI bus between an Atmel ATSAM3X8E and a Spansion FL164K flash memory chip. SPI has always been super reliable for me in past projects, but this design ...
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Deriving two independently stoppable clocks from one clock

I am trying to do some complex, pipelined computations in FPGA that involves storing partial results in block ram and retrieving them later. The problem is, the number of partial results that needs to ...
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3answers
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How to configure Atmel SAM D20 for internal 48MHz clock source?

I try to run a Atmel SAM D20 MCU at 48MHz using the internal oscillator (OCM8M) and the digital frequency locked loop (DFLL48M). All I achieve is a deadlock of the processor, even I use a simple "...
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143 views

Swapping positive and negative traces of an LVDS oscillator

Can I swap the positive and negative traces of an LVDS oscillator (Si series of silicon labs) when connecting to clock pins of an FPGA? If no, what about adding series capacitors and using AC coupling ...
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Spartan-6 input data: Use data pins or GCLK?

I am designing a PCB which connects to a Spartan-6 via a connector (Opal Kelly XEM board). The PCB hosts some analog components which will communicate with the FPGA (ADCs, DACs). The FPGA board itself ...
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488 views

Is it possible to build an oscillator from an NPN transistor?

I have an old Russian clock, that you wind up every day, but has a AA battery for the alarm. It somehow creates sound and vibration by resonating a metal piece. However, recently this broke. And my ...
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928 views

What is problem with NRZ and how manchester line coding handles out of sync tx and rx clocks.?

I am reading about physical layer of the OSI model. Specifically the different ways in which digital bits can be represented as voltage levels, among the multiple types are: NRZ. Manchester encoding. ...
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How to send a packet every n clock cycles in verilog?

I am fairly new to Verilog and in general Digital Design. I am working on a project which has a state machine. The module, in a particular state, receives a read request packet from some other module ...

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