Questions tagged [clock]

A digital signal that goes high and low at a specific frequency.

Filter by
Sorted by
Tagged with
4
votes
3answers
2k views

Clock switching using clock gates

I am working on an ASIC design and need to use different clock sources for a digital block in different operating modes. Can I safely use clock gating in combination with an OR gate to generate the ...
2
votes
3answers
658 views

Detecting glitches in a sync signal

I have an FPGA clocked at 20 MHz and receiving an input sync signal clocked at 1 MHz. I would like to test that the sync signal has clean edges, so that if the FPGA was to use the sync signal as a ...
4
votes
2answers
3k views

Is it ok to use both rising and falling egde in this VHDL design?

I'm pretty new to designing hardware with VHDL, and I think I'm making a noob mistake. I'm making a CPU and my registerfile is rising_edge triggered. I had a problem though. I'll try putting some ...
3
votes
3answers
5k views

Help understanding AVR execution timing

I am working with an Atmel ATMEGA32U4 microcontroller - datasheet here with a 16 MHz crystal for system clock. From my understanding, this chip has a 'Divide clock by 8' fuse programmed from the ...
3
votes
1answer
11k views

PIC18F2550 oscillator settings?

I'm little confused about oscillator settings for PIC18F2550. I have 20 MHz crystal (not oscillator) and I want PIC to work (if it is possible) at 48 MHz (both PIC core and USB). This is part of a ...
2
votes
3answers
895 views

Clock circuit layout techniques

I am prototyping (point to point wiring only) a digital circuit with multiple shift register IC's to be clocked simultaneously at 500Khz. The distance between the clock source and the IC clock pins is ...
0
votes
2answers
612 views

Identify component in old West German flip clock

I recently got hold of three nice vintage flip clocks. No time keeping mechanism is present but there is something to advance the time on the clock. This mechanism has one major component labelled ...
5
votes
3answers
1k views

Help wanted explaining signals coming with higher frequency than clock and how to handle them

I am getting my hands on Verilog and FPGA programming. So I wrote a simple module that handles two inputs - button signal and a clock. Initially, it lights up two LEDs and when the user presses and ...
-3
votes
3answers
2k views

Generation of clock signals

Inside a computer, a crystal oscillator sends signals to a microcontroller or microprocessors. I want to know if the crystal oscillator is increasing the frequency or generating pulses. My questions ...
1
vote
1answer
1k views

Working with Spartan-6 LX9 clock

I am a novice in digital design and are learning things using "Advanced Digital Design with the Verilog HDL" along with a Spartan-6 LX9 board by Xilinx. So far I have managed to blink few leds on the ...
3
votes
3answers
14k views

Basic timings with an STM32

I am looking to make very basic timings on an STM32. For example, I would like to program my STM32 to output bytes on the UART for 1 minute. What clock/timer should I use? Looking through the ...
2
votes
2answers
2k views

System Clock Ringing

I have a 8 MHz oscillator that I run to two CPLDs on my board. The trace lengths are less than 1.5 inches. The traces do you have vias in them, so they do change their impedance. But I was hoping that ...
1
vote
1answer
2k views

Measuring the HSE frequency of an STM32F2

I am programming an STM32F2 (manual here). I am having clock problems and would like to check every clock using an oscilloscope. The first clock I want to check is HSE, which stands for: High Speed ...
1
vote
1answer
2k views

Setting the HSE clock frequency of an STM32

I am programming an STM32 (manual here). Page 83 has a diagram indicating that the HSE Clock frequency is between 4 and 26 MHz. The paragraph on HSE clocks starts on page 84, but does not give any ...
10
votes
2answers
5k views

Sharing an oscillator between two ICs

I have a microcontroller and an FPGA on the same board. If they're both going to run at the same clock speed, can I just use one oscillator to clock them both? There seems like there is something I ...
2
votes
1answer
519 views

How can pipelining hurt the clock frequency?

As I understand it, pipelining is used to speed up the clock frequency by processing more instructions at once, and longer pipelines should improve the clock frequency. However, my instructor ...
17
votes
6answers
30k views

Using the ATMega328 with the internal oscillator?

I have a project that I think would be best suited for an ATMega328P. However, in every simple project I've seen, people always hook up a 16MHz external oscillator. From what I can see, it should have ...
1
vote
2answers
2k views

Digital Clock Circuit

I am making a solid wood clock using minimal components. So far, I thought of using 21 LEDs to make 7 segment displays (3 LEDs for each segment (overall 63 LEDs for the displays)), 6 LEDs for the 1 in ...
1
vote
4answers
6k views

Clock generation using FPGA

I am trying to use Spartan 3E kit to generate 50 MHz clock. The kit comes along with a 50 MHz crystal which I am trying to use. So, I wrote a simple code to output the clock from the FPGA to the SMA ...
1
vote
1answer
593 views

PCI-Express timestamp source that can be used in Windows?

I need to do some accurate time measurements and I need to have access to a affordable / cheap and somewhat more reliable timestamp/time source than what is built in Windows/CPU. I need to read the ...
4
votes
1answer
906 views

How to sync sensor data

Suppose I have multiple dataloggers receiving sensor data, how can I sync those signals afterwards? The most obvious way would be adding timestamps to the data, but they have independant clocks, so I ...
1
vote
1answer
86 views

feeding another circuit a start signal (initializer) with d-latch (1,0,0,0,0…)

One of our lecturers has shown us a system for hardware compilation that uses control pulses. Anyway, I basically want to generate a starting control pulse of 1 to be fed into another circuit. ...
6
votes
1answer
1k views

Generate a 4.25 GHz using 50 MHz crystal/oscillator and PLL

I want to generate a 4.25 GHz using a PLL and 50 MHz crystal/oscillator. I am confused as to what I need to look for in a PLL. In a integer-N PLL, the prescalers are 16/17, 32/33, 64/65, etc. So, my ...
1
vote
1answer
2k views

How to generate a high-frequency clock?

I want to generate a high frequency (4.25 GHz) clock for a high frequency communication circuit. So, my question is: What are the alternate ways of generating the high frequency clock and which would ...
11
votes
2answers
5k views

When do I need to use a clock buffer IC?

I am designing a circuit and PCB for driving 7 DACs from an FPGA. (DAC is AD9762) Would it be possible to drive the clock inputs on all 7 DACs with a single clock output (from a PLL output pin) of ...
4
votes
2answers
3k views

Timing and clock skew problems in digital designs

I am reading "Rapid Prototyping of Digital Systems: SOPC Edition", and on p.113 it contains the following statement: In VHDL, as in any digital logic designs, it is not good design practice to <...
1
vote
1answer
493 views

What happens when running a LCD at lower clock speed

I need to display a still image (just the same grey color all over, so no need for difficult calculations what to display where) using only an Arduino Duemilanove (ATMega 328) and a Sharp LCD panel (...
0
votes
1answer
2k views

Generating SMPTE time code signal

SMPTE signals are (one of) the signals used to synchronize video and audio recordings from multiple cameras/recorders. How does one go about generating such a signal? I have a GPS-derived clock and ...
5
votes
2answers
6k views

Interfacing PIC18F4550 with I²C EEPROM (24AA1025)

I am working on a university project in which I need to interface a PIC18F4550 with an I²C EEPROM. I read many codes and saw many projects on this topic. And I wrote a sample code from MPLAB C18 (and ...
1
vote
1answer
524 views

Data path timing vs control store subcycles

Are two clock cycles, one at microarchitecture level (data path clock cycle) and another at control store memory address register, operating sequentially or asynchronously of each other? More ...
5
votes
2answers
811 views

Clock Shape Changes with Two O-Scope Probes

I have a Max V CPLD development board which has a 10MHz oscillator onboard. I hooked up CH2 probe to the output pin and then wrote a small VHDL program that output the clock to an external pin. I ...
3
votes
3answers
840 views

Clock generation of 9 phases of clock

I am trying to come up with a circuit that generates a series of clocks, I will need these different clocks on different pins. The circuit must be configurable in terms of frequency and phase shift (...
0
votes
1answer
230 views

bit bang programming with a 1/222.2ns clock

I need to bit bang at a 1/222.2ns clock rate. I am looking a recommendation for the bit banging clock source and "easy" to program means of bit banging at this clock rate.
2
votes
1answer
336 views

Recommendation for si4734 external clock source

The si4734/4735 FM receiver has two options for clock input, one is to use the typical crystal oscillator (a crystal + pair of capacitors to ground), attached to the DCLK+RCLK pins, the other is to ...
4
votes
3answers
5k views

Stopping the clock without gating the clock

How would one go about making a shift register which only shifts when an enable line is high? The obvious answer is to pass the clock and enable through an AND gate, but that breaks the "don't gate ...
3
votes
3answers
346 views

PLL versus putt-putt-skip, putt-putt-wait, fractional-rate division, or other approaches

Many applications use PLL's to generate frequencies where long-term frequency accuracy is necessary, but where a certain amount of short-term jitter might be acceptable. I've seen a number of devices ...
1
vote
1answer
244 views

System Generator:How to know how many clock cicles are nedeed for my FFT block?

I would like to know how many clocks cycles the FFTv4_1 require? Does anyone know how to determine the required clock cycles? I am using the System Generator 9.2i version. Thank you so much!
5
votes
3answers
1k views

What would be the best way to design a real time clock for the MSP430?

Basically that. The way I am doing it now is with the TimerA set to 1 second interrupts. But I think that it's very annoying. Are there any other ways to do it? I want to basically set timers on that ...
10
votes
4answers
4k views

timing constraint for bus synchronizer circuits

I've a bus synchronizer circuit for passing a wide register across clock domains. I'll provide a simplified description, omitting asynchronous reset logic. The data is generated on one clock. ...
1
vote
1answer
122 views

Freescale MCP8260, don't understand pins

I am looking at the Freescale MCP8260 processor. For programming PINS you set values to some registers. I would like to use MII interface for Fast Ethernet for example. I can see the Dedicated PINS ...
7
votes
2answers
27k views

How do I calculate needed pixel clock frequency?

If I want to have a resolution of X * Y pixels, updating in frequency f. How do I calculate the pixel clock speed? Example: 1280 x 1024 @ 85Hz usually have a pixel clock of 157.5 MHz, but how do I ...
3
votes
4answers
1k views

If the output of a D type flip-flop appears immediately on the clock edge, how can the previous output be used?

The way I understand it, the input value (D) of a D type flip-flop appears immediately on the output (Q) of a D type flip when triggered by a positive clock edge. If this is the case, then how can the ...
3
votes
2answers
2k views

Alternating patterns in 8b/10b encoding

I'm trying to evaluate the quality of an 8b/10b encoded data stream (Gigabit Ethernet, 1.25 gigabits/sec). Without doing clock recovery from the data stream, I want to measure jitter (et al) with a ...
5
votes
3answers
3k views

Odd number frequency divider

Important note: You are not helping me do my homework. This is for a competition for engineering students, that encourages you to "use your network" ;) I've got this pattern for a frequency divider ...
5
votes
4answers
4k views

Calculating error between two clocks?

I have a clock. It generates ticks. I want to know the error in PPM relative to another clock, so I count the ticks. Let's say the oscillator is 1 MHz (for simplicity). I should count 1,000,000 ...
1
vote
3answers
324 views

Crafting a digital watch

I've been wondering. How hard is it to craft a (digital) watch from scratch? I'm currently thinking that (with a lot of assumptions) you can buy/import quartz chips or something like that from ...
6
votes
6answers
4k views

How to build an ultra-low power time counter?

Inspired by this question I would like to know how low power you could go with a counter + 32 kHz oscillator (possibly made by yourself). I found a nice oscillator circuit on a BJT reportedly drawing ...
0
votes
1answer
558 views

Can the frequency of the SPI sck on an mbed be adjusted?

I'm trying to control a serial dataflash memory through the SPI interface of an mbed. SCK from the mbed is connected to CLK of the dataflash memory. I'm not sure, but I'm starting to suspect that this ...
6
votes
5answers
8k views

DSC Keybus Protocol

I'm plan to interface a atmel avr with my alarm system in home but the issue is DSC has a propriatary protocol between the keypad and the base. So has anyone messed with this before or can give me a ...
4
votes
5answers
1k views

How much overclocking is “okay”?

So I'm using a PIC32, it's rated for 80 MHz operation. But my crystal might be inaccurate, so it could oscillate at 80.01 MHz. I can presume this is okay, but what if I were to use a 7.3728 MHz ...