Questions tagged [clock]

A digital signal that goes high and low at a specific frequency.

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28 views

Can I use a single clock line for 6 parallel addressable rgb data lines?

I am making a PCB with the dimensions of about 60 (height) mm by 320 mm (width). The PCB contains 5 Letters and 1 logo. The idea is to have 6 datelines in parallel. This way I can have different ...
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119 views

Why Positive-going clock transitions used in certain ICs

Why do certain ICs like 74ALS174 use an inverter so as to make a Positive-going clock transitions occur instead of Negative-going ? Why can't we just save expense of an inverter by removing it and ...
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69 views

Can I bridge output IO's from an FPGA that is driving a clock source to drive longer tracks?

Scenario I have a motherboard and a daughterboard that couple through two headers. The motherboard has a 16x16 array of ultrasound speakers each with their own drivers, that works. I drive them ...
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173 views

Does this clipped-sine oscillator need a buffer?

I'm considering using an Abracon VCTCXO, the ASVTX-11-121-19.200MHz-T to run an AT89LP428. I'm trying to make sure that they're interoperable, but the Abracon device doesn't say anything about the ...
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85 views

Clock synchronised to pulse

I'm thinking about 1Mhz clock signal synchronised to external random pulses (eg. rising edge). Before pulse event clock can be running or stopped. After every pulse, it should run in same fixed phase ...
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119 views

Frequency multiplier from kHz to MHz

I'm not familiar with electronics at all, and would like to get some ideas to implement frequency multiplication of LVCMOS. I want to multiply the frequency in the range of 250 kHz by a factor of 10 ...
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23 views

Tracking ADC Control Logic Not Counting down, only up?

I'm working on trying to build a "tracking" type ADC from individual components. Shown below is my schematic using the parts available in Multisim. The design is based on the 74LS191N 4-bit Up/Down ...
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96 views

STM32F405 Setting Clock Freq Less than Max 168 MHz

For STM32F405 the max system clock frequency is 168 MHz. I want to run it at marginally lower frequency only for the sake of safety and reliability because my application will run non-stop through out ...
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3answers
80 views

Deciding which assembly is more common positive edge detector

I know of two circuits which can act as edge detector: A clock connected as a voltage source across a RC component where resistance is composed of a diode and a resistor and this in series with ...
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1answer
60 views

Zero-R Resistor on XTAL pins

Looking at the schematics of the STM32F4-Discovery board page 28, whose screenshot is attached below.. there is a Zero Ohms resistor 'R25' which is shown in the circuit with the Crystal. And there is ...
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1answer
66 views

MASTER Clock output from one micro to another vs independent clock src

I have a Small STM32 Nucleo board where the on-board ST-Link debugger has an 8mhz crystal for the debugging microcontroller. That microcontroller is set up to output its MASTER clock, in other words ...
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44 views

AES Sub Byte subsitution in four clock cycles

I am trying to implement AES in verilog using 32-bit data path, but I am not able to subsitute the 128-bit in just four clock cycles, my code requires five clock cylces, Here is the small portion of ...
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129 views

STM32CubeMX Timer Clock Source

If i am using External oscillator with STM32F407 and I select 'Internal Clock Source' for a Timer then what would that mean? What clock frequency will the Timer/Counter register see at its input if my ...
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3answers
447 views

555 Clock Circuit - how to choose resistor value? [closed]

I need to design a 555 clock circuit to output a clock pulse of a specific frequency. The circuit I'm using is this one (from here): I've used this circuit before and it works fine but the website ...
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3answers
207 views

Why include frequency dividers in this PLL circuit?

I found replicated in few sites this PLL diagram and I'm wondering why the authors included frequency dividers on the input and output signal, since the two signals to be compared have the same ...
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35 views

FPGA VCU108 FMC Clock

For a project at work, we are attempting to create sinusoidal signals ranging up to 2 GHz using DDS implemented on an FPGA and DAC. Our current hardware consists of a VCU108 FPGA board from Xilinx ...
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4answers
585 views

What is the meaning when we say power of circuit having a clock frequency 100Hz is 2W?

When we say clock frequency is 100Hz, then there are 100 clock pulses in one second. So when we say power is 2W, is it 2W for 100 cycles or one cycle ? Or is it anything else?
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50 views

What does an internal or external loop filter do for this clock IC?

For the CDCE62005 clock generator IC, what does the internal or external loop filter accomplish? Thanks in advance for any input. Page 44 of datasheet, and pages 1-2 and 6 or the eval board user ...
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95 views

Can I use an unmodified ST Nucleo-F303RE to develop USB devices?

I want to use my Nucleo-F303RE to develop firmware for a USB HID. The stm32f303ve data sheet states in section 3.25 that for the USB peripheral to work, the MCU needs a HSE crystal oscillator. ...
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1answer
124 views

SPI clock selection

Using STM32l476 controller. Master is running at 30 MHz and slave is running 15 MHz. In SPImaster, clock should be system clock/2. In slave, clock should be system clock/4. Question: My ...
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2answers
415 views

How to use 1PPS to Synchronize ESP32 Clocks and Peripherals

I've read a few posts (example) about what the 1PPS signal is and how it can be used at a high-level, but I'm still not sure how to actually implement it on a PCB schematic to sync up with my ...
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1answer
94 views

Cascade shift registers driven by single-cycle microcontroller

I'm trying to make a unit in which 4 digits can be updated in a small amount of time from a single-cycle microcontroller (preferably all digits updated within 5uS) My circuit is setup in the ...
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3answers
167 views

Getting CPU clock signal out of computer (as to measure externally) [closed]

I've been searching on the internet some clock generator module capable of reaching up to 1GHz, when I just realized that the machine I'm using to search has one CPU with its own 2.5-3.0 GHz clock... ...
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93 views

Are there still programmable clock synthesizers with single ended TTL output leves (in 2019)?

I'm looking for a clock synthesizer IC that can drive my vintage 5V NMOS CPU in the range of 5 - 50MHz. The granularity would preferably be in the range of 100kHz or less. All I can find when ...
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1k views

Estimate electrical frequency from clock shift

About 6 months ago I installed a solar power system with 2 Tesla Powerwalls for backup. Today, we got to test out the system with a power outage from an ice storm in the southeast. (We are still on ...
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205 views

Inverter feedback when converting clipped sine oscillator signal to square wave

I inherited a design that uses the following circuit to generate a 40MHz square wave clock signal: KT2520K is a TCXO that outputs a clipped sine wave and the inverter has a peak output voltage of 3....
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138 views

Are there special rules for voltage division of a high speed clock?

High speed signals require special care in PCB layout to prevent high speed effects like ringing and overshoot. This obviously applies to clock signals as well. Provided that one has a high voltage ...
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2answers
62 views

Can I use MCU's internal oscillator when communicating with GPS and cellular modules?

Can I use MCU's internal oscillator when communicating with GPS and cellular modules? I want to avoid connecting external crystals for the MCU since they generate noise, extra components, extra costs, ...
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2k views

Can wireless communciation be synchronous?

I understand that in synchronous communication, the sender and receiver need a common clock. Is it possible that wireless communication be synchronous? Can some common clocking element be there for ...
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1answer
64 views

What happen to a dff(flip flop) without input?

I have this question but I don't know what happen to a dff without an input is it always 0 ?? like this picture below the 2nd dff hasn't any d ??? Also, if someone can draw the answer of the question ?...
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1answer
118 views

Pausing a clock signal generated by 555 timer

I am planning to make a simple integer adder/multiplier which needs a variable frequency, comparatively slow clock (around 1 to 200 Hz) for demonstration purposes. I used the following generic 555 ...
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117 views

How to cascade frequency dividers

I'm implementing some modules using VHDL and for some of them I need the FPGA's global clock signal, and for some others I need to update to two different frequencies. A common solution to this is ...
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4answers
116 views

Can I calculate how much time it will take for an electrical signal to propagate through a TTL circuit?

Given a particular circuit of TTL, can I calculate how much time it will take for an electrical signal to propagate through some section, or all of, the circuit? If I wanted to know how long it ...
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2answers
88 views

Maximum Clock Input Frequency Datasheet Confusion

I was looking for an 8-bit parallel to serial shift register to use in a project I am making. Initially, I thought that the 4021 would work perfectly for what I need, however, after looking at the ...
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1answer
59 views

Using 2 Data Flip Flops to create an up counter from 0 to 3 and repeats

I've done most of the legwork. I've got this design working using 2 set reset(SR) flip flops, but I need to make it using 2 data flips, a.k.a D flip flops. What I did: Note the numbers not in ...
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1answer
122 views

Timing Constraints for Forwarded Generated Center-Sampled Clocks?

Problem Description I am trying to figure out the "correct" way to constrain (in .xdc format - this is in Vivado) a forwarded source-synchronous clock that is generated (by division) from the ...
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1answer
317 views

LSE fail to enable

I am using a blue pill with STM32F103C8 and I am trying to debugg my programm but every time it is stack in the activation of the LSE clock (LL_RCC_LSE_IsReady() != 1) I have the following system ...
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1answer
38 views

Bidirectional data bus divided into nibbles not returning correct data - 8051

Since I have 10 I/O lines connected between two microcontrollers (AT89C4051 + AT89S52), I am trying to get away with elegant data transfer. Instead of spending months redoing an entire circuit board, ...
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58 views

Differential Clocking resistor and capacitor choices

I am working on generating a 2MHz differential clock signal for a DDS chip. I have been given a PCB with a design that I am unsure can work or what the thought was behind it. If anyone could help with ...
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1answer
262 views

Clock signal generator using 7400

I have an old PCB that uses this clock generator (means I'm absolutely sticking to the schema). The IC is standard 7400, resistors are the same, but the capacitors I'm using have 470 uF (500's are ...
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1answer
141 views

GPSDO control algorithm

I am currently building my own GPS disciplined oscillator. I have a OCXO which is used as clock source for a microcontroller and one of its counters, and the 1PPS signal from the GPS module is ...
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1answer
668 views

STM32L0 - Delay in microseconds

I am using a B-L072Z-LRWAN1 board (which has a STM32L072 MCU) and I want to get data from a DHT11 sensor. To achieve this, I need a microseconds delay which I am not able to obtain. The libraries ...
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2answers
302 views

(Reasonably) accurate 1Hz clock generator

I would like your advice on components before I purchase anything. I am going to make a digital 24hr clock using probably JK flip flops/multiplexors with 7 segment displays. But it must be battery-...
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41 views

How do I configure system clock while using MBED IDE?

Just starting to use STM32 boards with web-based MBED IDE. This IDE don't have anything like Project configuration menu like other IDEs do. So I can not understand how do I configure system clock. ...
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2answers
1k views

At both posedge and negedge in Verilog?

In Verilog, I can use an always block and make it trigger on a positive or negative edge. Is it possible to trigger the block on both the positive and negative edge, and thus have it basically ...
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1answer
255 views

Separate GND-plane for microcontroller crystal resonator

1.  Background info I'm designing a board for an STM32F767ZI microcontroller. This microcontroller has a primary oscillator for the SYSCLK (overall system ...
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81 views

Have I bricked my ATMEGA3328p by setting

I was playing around with setting the "system clock prescalar" (CLKPR). I'm now in a situation where I can see that the clock is 244.9KHz, using my logic analyser and the "Clock output on PORTB0" ...
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1answer
990 views

STM32 F4 max GPIO toggle frequency [duplicate]

I just started using the STM32 F401VC Discovery Evaluation board and I'm trying to get the maximum GPIO toggling frequency without assambler. So my tought process is following: The code I was ...
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1answer
157 views

Clock oscillator pin, requirement, ac-decoupling and termination

I'm trying to make something with ADI PLL (ADF4159 and ADF5901). In their datasheet there is nothing about how to source the clock pin. I have found lots of information about clocks on the internet ...
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1answer
94 views

What are the advantages of a wider bus in comparison to those of a higher clock frequency? [closed]

The aim is to increase data transfer rate. I understand each may have some drawbacks and advantages. Frankly I'm not knowledgeable enough to know of many so I'd like some input from others. I know ...