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Questions tagged [clock]

A digital signal that goes high and low at a specific frequency.

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2answers
101 views

Are there still programmable clock synthesizers with single ended TTL output leves (in 2019)?

I'm looking for a clock synthesizer IC that can drive my vintage 5V NMOS CPU in the range of 5 - 50MHz. The granularity would preferably be in the range of 100kHz or less. All I can find when ...
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3answers
1k views

Estimate electrical frequency from clock shift

About 6 months ago I installed a solar power system with 2 Tesla Powerwalls for backup. Today, we got to test out the system with a power outage from an ice storm in the southeast. (We are still on ...
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3answers
252 views

Inverter feedback when converting clipped sine oscillator signal to square wave

I inherited a design that uses the following circuit to generate a 40MHz square wave clock signal: KT2520K is a TCXO that outputs a clipped sine wave and the inverter has a peak output voltage of 3....
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2answers
147 views

Are there special rules for voltage division of a high speed clock?

High speed signals require special care in PCB layout to prevent high speed effects like ringing and overshoot. This obviously applies to clock signals as well. Provided that one has a high voltage ...
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2answers
65 views

Can I use MCU's internal oscillator when communicating with GPS and cellular modules?

Can I use MCU's internal oscillator when communicating with GPS and cellular modules? I want to avoid connecting external crystals for the MCU since they generate noise, extra components, extra costs, ...
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5answers
2k views

Can wireless communciation be synchronous?

I understand that in synchronous communication, the sender and receiver need a common clock. Is it possible that wireless communication be synchronous? Can some common clocking element be there for ...
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1answer
73 views

What happen to a dff(flip flop) without input?

I have this question but I don't know what happen to a dff without an input is it always 0 ?? like this picture below the 2nd dff hasn't any d ??? Also, if someone can draw the answer of the question ?...
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1answer
157 views

Pausing a clock signal generated by 555 timer

I am planning to make a simple integer adder/multiplier which needs a variable frequency, comparatively slow clock (around 1 to 200 Hz) for demonstration purposes. I used the following generic 555 ...
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139 views

How to cascade frequency dividers

I'm implementing some modules using VHDL and for some of them I need the FPGA's global clock signal, and for some others I need to update to two different frequencies. A common solution to this is ...
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4answers
118 views

Can I calculate how much time it will take for an electrical signal to propagate through a TTL circuit?

Given a particular circuit of TTL, can I calculate how much time it will take for an electrical signal to propagate through some section, or all of, the circuit? If I wanted to know how long it ...
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2answers
91 views

Maximum Clock Input Frequency Datasheet Confusion

I was looking for an 8-bit parallel to serial shift register to use in a project I am making. Initially, I thought that the 4021 would work perfectly for what I need, however, after looking at the ...
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1answer
66 views

Using 2 Data Flip Flops to create an up counter from 0 to 3 and repeats

I've done most of the legwork. I've got this design working using 2 set reset(SR) flip flops, but I need to make it using 2 data flips, a.k.a D flip flops. What I did: Note the numbers not in ...
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1answer
142 views

Timing Constraints for Forwarded Generated Center-Sampled Clocks?

Problem Description I am trying to figure out the "correct" way to constrain (in .xdc format - this is in Vivado) a forwarded source-synchronous clock that is generated (by division) from the ...
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1answer
372 views

LSE fail to enable

I am using a blue pill with STM32F103C8 and I am trying to debugg my programm but every time it is stack in the activation of the LSE clock (LL_RCC_LSE_IsReady() != 1) I have the following system ...
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1answer
41 views

Bidirectional data bus divided into nibbles not returning correct data - 8051

Since I have 10 I/O lines connected between two microcontrollers (AT89C4051 + AT89S52), I am trying to get away with elegant data transfer. Instead of spending months redoing an entire circuit board, ...
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0answers
65 views

Differential Clocking resistor and capacitor choices

I am working on generating a 2MHz differential clock signal for a DDS chip. I have been given a PCB with a design that I am unsure can work or what the thought was behind it. If anyone could help with ...
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1answer
316 views

Clock signal generator using 7400

I have an old PCB that uses this clock generator (means I'm absolutely sticking to the schema). The IC is standard 7400, resistors are the same, but the capacitors I'm using have 470 uF (500's are ...
2
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1answer
183 views

GPSDO control algorithm

I am currently building my own GPS disciplined oscillator. I have a OCXO which is used as clock source for a microcontroller and one of its counters, and the 1PPS signal from the GPS module is ...
2
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1answer
917 views

STM32L0 - Delay in microseconds

I am using a B-L072Z-LRWAN1 board (which has a STM32L072 MCU) and I want to get data from a DHT11 sensor. To achieve this, I need a microseconds delay which I am not able to obtain. The libraries ...
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2answers
356 views

(Reasonably) accurate 1Hz clock generator

I would like your advice on components before I purchase anything. I am going to make a digital 24hr clock using probably JK flip flops/multiplexors with 7 segment displays. But it must be battery-...
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42 views

How do I configure system clock while using MBED IDE?

Just starting to use STM32 boards with web-based MBED IDE. This IDE don't have anything like Project configuration menu like other IDEs do. So I can not understand how do I configure system clock. ...
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2answers
1k views

At both posedge and negedge in Verilog?

In Verilog, I can use an always block and make it trigger on a positive or negative edge. Is it possible to trigger the block on both the positive and negative edge, and thus have it basically ...
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1answer
295 views

Separate GND-plane for microcontroller crystal resonator

1.  Background info I'm designing a board for an STM32F767ZI microcontroller. This microcontroller has a primary oscillator for the SYSCLK (overall system ...
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1answer
89 views

Have I bricked my ATMEGA3328p by setting

I was playing around with setting the "system clock prescalar" (CLKPR). I'm now in a situation where I can see that the clock is 244.9KHz, using my logic analyser and the "Clock output on PORTB0" ...
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1answer
1k views

STM32 F4 max GPIO toggle frequency [duplicate]

I just started using the STM32 F401VC Discovery Evaluation board and I'm trying to get the maximum GPIO toggling frequency without assambler. So my tought process is following: The code I was ...
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1answer
161 views

Clock oscillator pin, requirement, ac-decoupling and termination

I'm trying to make something with ADI PLL (ADF4159 and ADF5901). In their datasheet there is nothing about how to source the clock pin. I have found lots of information about clocks on the internet ...
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1answer
135 views

What are the advantages of a wider bus in comparison to those of a higher clock frequency? [closed]

The aim is to increase data transfer rate. I understand each may have some drawbacks and advantages. Frankly I'm not knowledgeable enough to know of many so I'd like some input from others. I know ...
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1answer
362 views

Clock signal purpose

I'm a mechE and have been trying to get into the digital world for a bit and need to know why a system would need a clock signal at all. For example, if I have some bit of code getting executed on a ...
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1answer
174 views

CPU clock cycles required to execute the following inx?

Consider the following data path of a simple non-pipelined CPU. The registers A,B, A1, A2, MDR, the bus and the ALU are 8-bit wide. SP and MAR are 16-bit registers. The MUX is of size 8×(2:1) and the ...
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2answers
625 views

SPI interface on Xilinx FPGA, clock domains and timing constraints

I am interfacing a Raspberry Pi board to a dev board with a Spartan 6. I want to do this using SPI. Because of the way the dev board is designed, I need to connect SPI CLK and DATA to standard IO pins....
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1answer
73 views

Selecting the equipment with the optimal 10 MHz reference

In a larger testbench I have 5 synchronized instruments (signal generators, ARBs, VSAs etc). I am trying to decide which instrument to take as "master". I rule out the older/cheaper parts (Tektronix ...
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2answers
368 views

10 MHz reference distribution (daisy chaining vs. BNC tees vs something else)

10 MHz is the quasi-standard for reference clock in measurement equipment. Most boxes have "REF in" and "REF out" or "10 MHz in"/"10 MHz out". In my case, I have a measurement setup consisting of an ...
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0answers
36 views

Can this circuit produce 0, 5 and 12 volts in fixed increments for the AT89LP4052?

Due to the speed requirements of my project, I'm looking at replacing the AT89C4051 with an AT89LP4052 with some code modifications since it offers double the memory and 6x the speed for the same ...
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1answer
51 views

IN/OUT pin of the crystal circuits [duplicate]

Got few questions about the input/output pins of a crystal circuit. As shown above, it's a common clock circuits. My question is: 1. If we want to measure the waveform of the clock, which pin should ...
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1answer
225 views
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2answers
225 views

How to limit the output voltage of a TCXO?

I am using an SiT1552 MEMS TCXO providing 32.768 kHz. It will be sourcing two ICs: a microcontroller and a DA14580 Bluetooth Low Energy transceiver. The ICs and TCXO are all powered by 3.3V. The TCXO ...
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1answer
210 views

Crystal reference and capacitors for w5500

I'm selecting the caps for the crystal oscillator of the wiznet W5500. The standard Load Capacitance for 25Mhz crystals is 18pF. I found out that the hardware guideline claims for a Load Capacitance ...
3
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1answer
138 views

Quartz Clock Accuracy

Do the vibrations of aircraft engines (or any engine, for that matter) dilute the accuracy of a quartz clock? I haven't done any kind of research or hypothesis testing, though I believe that the ...
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2answers
289 views

Xilinx ZYNQ/ARTIX7 Invert Clock without inducing skew

For HDL design I'm currently developing for a zynq SoC, I need to invert a clock signal because of a swapped differential pair on board level. Using "NOT" to invert adds a LUT in the path and as ...
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3answers
210 views

How can I see an output from SCL?

I am new to electronics, circuits, etc. Currently I am reading I2C and synchronous serial communications. As I understand, two devices must be connected to the same CLOCK wire so that the slave knows ...
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1answer
119 views

LCD SPI clock frequency with STM32L0 MCU

I'm designing a PCB that includes LCD Display NHD-C12832A1Z-FSW-FBW-3V3 (datasheet) connected to the STM32L071KZU6 microcontroller (datasheet). I'm afraid that the SPI interface of the LCD will not ...
4
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2answers
1k views

Minimum Clock Period from setup and hold time

I found several different answers to how setup and hold-time of Flip-Flops influence the minimum time between two rising clock edges. tclock >= Propagation delay + tsetup + thold tclock >= ...
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1answer
196 views

How do I redirect/regenerate an input clock to an output pin in my FPGA design (Verilog)

I've got an ADC that requires me to send it 20 clock pulses when requesting to read data out of its internal register (after I've triggered it to read data from my sensor). I was able to simulate ...
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4answers
2k views

Is there a small (6-pin) DIP I can use to generate multi-MHz squarewave clocks with an external crystal?

I'm building a circuit that I'd like to run at 8 MHz to begin with, but I want to be able to try it out at 10, 12, 16, 20, and, maybe, 25 MHz. I know that many microcontrollers have the ability to ...
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1answer
211 views

Is it possible to estimate the execution time of an FPGA design?

Is it possible to evaluate the "execution" time of an FPGA design? I think that if you have a design where you only have And, Or, Not, etc. gates, the result only depends on the inputs. But now with ...
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2answers
4k views

Why use DDR instead of increasing clock speed?

Why would you want to use DDR ram and read/write on every rising and falling edge of the clock instead of just doubling your clock speed and read/write on just one of either the rising or falling edge?...
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3answers
907 views

gps performance for synchronization

I can't understand why GPS reciever clock is very good (stratum 0). I know it's very accurate and pure within itself; but when it passes through a long distance wireless channel, then it has low power ...
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2answers
276 views

Crystals, capacitors and W5100

Background: I have built a number of devices based on the W5100 chip, all them were (are) working more or less decently. However last batch currently in testing show faulty behavior - almost all of ...
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2answers
595 views

Change a quartz clock timebase by changing the frequency of the quartz crystal oscillator?

I've been doing some research on rewiring clock circuits for a project, but I'm new to these types of pulse-counting circuits. My question at this point is: If I replace the existing quartz crystal ...
5
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2answers
827 views

How to get 8MHz square signal out a pic18f45

I am using a Pic18F45K40 to control an ST7590 power line networking chip which requires an 8MHz clock signal to function. I read the datasheet and it looks like a 16MHz signal can be generated from ...