Questions tagged [clock]

A digital signal that goes high and low at a specific frequency.

Filter by
Sorted by
Tagged with
1
vote
1answer
53 views

Is a good practice assigning clk to a signal before component instanciation in FPGAs?

I am working with VHDL for Xilinx FPGAs and I am trying to create some hierarchical components. When instantiating a component B inside another component A, what clk is expected to pass to the ...
0
votes
1answer
219 views

How to connect a 4-pin OSC (crystal oscillator) to an IMU (BNO055) with only 2 pins dedicated to an external clock?

I am using the BNO055 : https://cdn-shop.adafruit.com/datasheets/BST_BNO055_DS000_12.pdf and I can't seem to figure out how to connect a standard external oscillator clock to the chip. As suggested, ...
0
votes
2answers
146 views

High frequency clock from clocked RS latch

We were taught that this circuit is not of much use as when CLK=1, J=1 & K=1, Q toggles at a very high rate. So suppose I want to make a high-frequency clock, can I use this? Of course, the ...
1
vote
0answers
100 views

LVDS CLK Input Appropriate Here?

I'm working with an MCP37231/21-200 that requires a differential input for the clock. I need to know if I can use an LVDS input to drive my clock. The output clock is specified to have LVDS ...
1
vote
2answers
1k views

clock frequency divide by 5 vhdl

i want to get the clock frequency divide by 5, can i do it with integer type or i need something else to run the decimal number? ...
2
votes
2answers
1k views

PCI-E throughput calculation

could someone please do for me the calculation of total throughput of PCI-E? The best material I could find was a Xilinx pdf that mentioned 2.5Gbps as reference value and somewhat awkward formula that ...
12
votes
3answers
3k views

How do processors control their clock speed?

I recently came across an STM processor with 2 oscillators on the circuit - I suppose one for high-speed operation and the other for low power. For something like a desktop processor where the clock ...
0
votes
1answer
208 views

Enabling external reference to HP/Agilent Signal Generator (8648C)

What is the proper way to use an external 10 MHz clock signal for an HP/Agilent signal generator (in my case: 8648C)? With my Tektronix, Rohde & Schwarz devices, internal/external reference has ...
2
votes
2answers
374 views

Crystal oscillator on custom ATMega2560 board is at the wrong frequency

I have designed a custom board using an ATMega2560. The board works fine when configured to use the internal oscillator. The board stops working when I configure it to use the the external 16MHz ...
-1
votes
1answer
88 views

Clock impulse through push button [closed]

I need to store 4 bits in a shift register giving input through a push button. For which I also want to generate a clock pulse with the same push button with some delay(<100ms) so that the clock ...
1
vote
2answers
73 views

Can I use a common Clock pin on my micro-controller project instead of separate clock pins?

In my Propeller project, I have the following devices, with the related pins: DS1302 RTC SClk - IO - CE Micro SD Card SClk - CD - CS - DI - DO SPI SRAM x 2 SClk - SO - SI - CE PS2 Mouse ...
0
votes
1answer
29 views

Signal Integrity and clock waveform measurement

Where do you probe and measure the signal quality of a clock signal that has series termination? Do you probe at the end of the series resistor that is pointed towards the load? Or do you measure at ...
-1
votes
2answers
211 views

How to correct voltage overshoot in clock divider output?

I am trying to make a quadrature phase divide-by-6 clock divider circuit in cadence. I managed to complete the circuit and obtained the correct waveform; however, due to some reason I am getting a ...
-1
votes
1answer
104 views

How to match two clock signal's phases which are physically apart in two locations?

Suppose, I have one Tx and one Rx physically separated by the long distance with clock signals CLK1 and CLK2 as shown in fig. (say both of 50MHz). I wish to align them in phases. By that I mean, ...
0
votes
1answer
141 views

Active high, rising edge circuits update state when, exactly?

I'm very new to electrical engineering. On a recent exam, we had a circuit with two JK flip-flops connected in series with one another. The circuit is beside the point, however. Both flip-flops were ...
0
votes
0answers
61 views

resistor at external clock source line [duplicate]

im reading a arm based mcu board schematic and there is 100R resistor (R30) at external 25MHz oscillator source. What is the main reason of using serial resistor at clock line ?
0
votes
3answers
273 views

Simplest shift register test circuit - clock

I'm looking for the simplest way to test the operation of a 74HC595 shift register without complex circuitry. Currently (on a breadboard) I have a 47K SIP resistor in a pull-up fashion connected to ...
-1
votes
1answer
256 views

How to create discrete high voltage oscillator?

I need to increase 24 V DC to 1.5 kV DC. Using a voltage multiplier would require over 60 stages. I am considering using a few stages of a voltage multiplier, say 8, to increase the voltage to about ...
1
vote
1answer
184 views

Clock generator is not oscillating on the given XTAL's frequency

I created a PCB which needs to have a solid and precious clock source. For this purpose I used a Dual Inverter with Schmitt trigger (NC7WZ14). Now CLKI seems to generate 66kHz square signals (...
1
vote
3answers
97 views

Capacitor to limit AC current, block DC current

I am interested in making a 'life' indicator for my uC, as in, "Is the clock running?". As it has a clock output pin, I was thinking of attaching this schematic to it. simulate this circuit – ...
3
votes
4answers
1k views

Potato battery not powering clock

So for a school project where we have to make a lesson plan for kids to learn stuff out of "lame" experiments, I was assigned potato clock. I could not for the life of me find a simple 1.5 volt led ...
67
votes
5answers
12k views

Serbia, Kosovo power grid row delays European clocks. Why?

According to this article (and a lot more published today on the same topic), Kosovo electricity net production balance has decreased during the last weeks. This has led to a small deviation of the ...
0
votes
0answers
40 views

Faster 8051 not taking the slower 8051 pin status correctly

I'm trying to do a rather simple data transaction between two 8051 microcontrollers using a variant of the SPI protocol. The large one is a slave and the small one is a master. The documentation for ...
0
votes
1answer
268 views

Differences between flip-flop control inputs and clock inputs

I'm studying clocked flip-flops (FFs). However, I cannot differentiate between the two terms control inputs and clock inputs. Can you tell me the differences between those two types of inputs, or ...
0
votes
4answers
256 views

How stable are temperature controlled crystal oscillators?

This question is not as obvious as it might seem. Consider this, concerning Rubidium clocks: All commercial rubidium frequency standards operate by disciplining a crystal oscillator to the ...
4
votes
1answer
423 views

SPI clock - slow frequency but fast rise time issue with waveforms

Background on the issue: I currently have an SPI bus between an Atmel ATSAM3X8E and a Spansion FL164K flash memory chip. SPI has always been super reliable for me in past projects, but this design ...
0
votes
1answer
47 views

Deriving two independently stoppable clocks from one clock

I am trying to do some complex, pipelined computations in FPGA that involves storing partial results in block ram and retrieving them later. The problem is, the number of partial results that needs to ...
0
votes
1answer
270 views

5v clock feeding 3.3v microcontroller - resistor+zener acceptable?

So I've used a resistor and diode to level-shift from 5v to 3.3v, but that's been for general logic - the fastest thing I've done with that is 9600 bps serial. I now have a need to feed a 3.3v ...
0
votes
3answers
118 views

Swapping positive and negative traces of an LVDS oscillator

Can I swap the positive and negative traces of an LVDS oscillator (Si series of silicon labs) when connecting to clock pins of an FPGA? If no, what about adding series capacitors and using AC coupling ...
1
vote
2answers
272 views

Spartan-6 input data: Use data pins or GCLK?

I am designing a PCB which connects to a Spartan-6 via a connector (Opal Kelly XEM board). The PCB hosts some analog components which will communicate with the FPGA (ADCs, DACs). The FPGA board itself ...
0
votes
1answer
419 views

Is it possible to build an oscillator from an NPN transistor?

I have an old Russian clock, that you wind up every day, but has a AA battery for the alarm. It somehow creates sound and vibration by resonating a metal piece. However, recently this broke. And my ...
2
votes
1answer
785 views

What is problem with NRZ and how manchester line coding handles out of sync tx and rx clocks.?

I am reading about physical layer of the OSI model. Specifically the different ways in which digital bits can be represented as voltage levels, among the multiple types are: NRZ. Manchester encoding. ...
2
votes
2answers
2k views

How to send a packet every n clock cycles in verilog?

I am fairly new to Verilog and in general Digital Design. I am working on a project which has a state machine. The module, in a particular state, receives a read request packet from some other module ...
-2
votes
3answers
116 views

Why is SDRAM speed independent from the motherboard?

My understanding based on my research says that Synchronous DRAM has its name because it synchronises with a clock on the motherboard. How is it, then, that the speed of the RAM doesn't depend on the ...
0
votes
2answers
292 views

why they use crystal frequency three times the required CPU clock?

In the data sheets for 8284a, the said The crystal frequency should be selected at three times the required CPU clock. why they use crystal frequency three times the required CPU clock?
0
votes
1answer
1k views

ATmega328P 16MHz or higher clock output on CLKO pin

I need a high frequency clock (16MHz or higher) to drive OV7670 camera module, and I want my ATmega328P to be source of that clock. I'm using the CLKO pin since I ...
0
votes
1answer
126 views

How can I determine the capacitance required for an oscillator (NOT A CRYSTAL!)?

In a typical clocking circuit configuration, where a crystal is tied at the input to an amplifier such as is shown below: The capacitance required for \$C_1\$ and \$C_2\$ would be based on the load ...
0
votes
1answer
166 views

Is combinational logic affected by the clock in FPGA? [closed]

I have a question whether a computational logic expression is affected by the clock if it is in a process and all the inputs are listed in the sensitivity list. If a change happens in one of the ...
3
votes
2answers
717 views

Splitting a ~100 MHz clock on a PCB

I have a PCB with a single-ended sinusoidal clock input via SMA connector. (It should come from an external, low-jitter clock source). This clock is used at various places (as references) and hence ...
0
votes
2answers
134 views

USB2512 - Too low input voltage in datasheet

I have two USB2512BI-AEZG(datasheet) ICs and would like to drive them using only one external crystal for well known reasons. What is misleading me is ultra low input low voltage specified in the ...
0
votes
1answer
60 views

Can this circuit validate AT89Cx051 micro if best valued components are used?

This is a circuit I made in an attempt to validate that the 20-pin microcontroller is an AT89Cx051. and the correct LED will turn on based on how much ram the chip has. While the first step is ...
-2
votes
1answer
303 views

Verilog code for frequency divider 2 [closed]

I have to write a code for frequency divider from 161.24MHz to 8KHz in Verilog. Please help to write a code.
0
votes
1answer
234 views

Building a 7 Segment clock using mains frequency

As the title says, I want to build a clock using the mains frequency (50Hz). I only want to use digital integrated circuits from the CD4xxx series or something similar. (no microcontroller or do-it-...
-1
votes
2answers
389 views

Set up two clock sources with an STM32F103?

As above really. I'd like to set up two clock signals on my STM32F103 for external circuits, one at 4 MHz and the other at 2 MHz. Here's what I've tried so far, but I'm not measuring any signal at ...
0
votes
1answer
557 views

Setting up an STM32F103 8 MHz clock source [closed]

I'm extremely new to the STM32F103 (just received it in the post today) and would like to know how (the best way) to set up one of its pins as a clock source for an external circuit. Ideally, I would ...
0
votes
1answer
194 views

How is the trigger pulse of the 555 timers generated? [closed]

I would like to connect an operational amplifier to the trigger circuit which then generates the pulse that starts the timing of the timer almost always connected to the clock generator. Since 555 ...
1
vote
1answer
914 views

STM32L4 Clocks Configuration

Does anyone know of a code template to properly configure clocks, PLL, latency, etc. for the STM32L4x parts? I'm using a NUCLEO board with this part (L476RG) and have struggled for days with the ...
0
votes
1answer
68 views

Output from latch clock [closed]

I am using a 74LS377 d-type latch but when I connect Vcc and ground, get a 1-1.2V output on the clock pin! I have 4.9V on Vcc and 0V on the ground and enable' pins. For my minimal example, I have left ...
0
votes
3answers
127 views

Interferometry's arch nemesis: CLOCKS

I have a problem and it spans easily 4 Stack Exchange forums so let's wrap up quick here. I'm doing radio astronomy. I'm setting up interferometry among 3 radio telescopes. (I'm using three PCB's with ...
9
votes
5answers
2k views

Setup and hold time output when violated

Consider a positive edge triggered D flip flop with input signal X with a setup time of 20 ns and a hold time of 0 ns. What will be the output? C is clock signal with a period of 40 ns....