Questions tagged [clock]

A digital signal that goes high and low at a specific frequency.

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243 views

5v clock signal to 24v

I have a 555 timer clock output controlling a few things, one of them is the coil of a 24v relay. How can I take the 5v coming from the 555 and pump it up to 24v. ? simulate this circuit – ...
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1answer
4k views

Get_ports vs Get_pins vs Get_nets vs Get_registers

I am doing a design in vhdl for FPGA. I have a top level design which consists of 3 components: clock divider, Module_1 and Module_2. Top level entity has a clock input port. This clock is divided by ...
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2answers
100 views

How to proceed to solve this question?

I was trying to solve this question but I got stuck when I tried to use AND gate with clock and some output. I want to ask whether value of rising edge of a clock is taken as 1 or value preceding it ...
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1answer
225 views

HDMI clock negotiation

For a switching application I want to make two HDMI signals synchronized, is there a way to negotiate clock signals between an HDMI source and sink or two sources (preferably without taking devices ...
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1answer
177 views

What to do to make the clock in the microwave always correct?

My new microwave has the same problem, after setting the correct time, after a week there is already 40 minutes forward. I even thought to install my RTC in it, but the manufacturer should somehow ...
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2answers
114 views

Can I output one flip-flop into another on the same clock pulse?

I have two positive edge octal D type flip flops with output enable (they're both 74LS374 chips), and I am wondering if it's possible to enable the output from one chip and clock the other on the same ...
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1answer
92 views

Is this machine code insufficient to chip timing?

I'm having trouble performing basic communication between two IC's. and AT89S52 and an AT89C4051. Both are connected using 6 GPIO pins of which 4 of them on each microcontroller are high nibbles of ...
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2answers
85 views

*how* are things triggered on clock rise, fall, high or low, [closed]

I know the purpose and function of triggering logic , such as a d flip flop, on certain clock conditions. However, what I have not been able to understand is actually how these "triggers" work. i was ...
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1answer
247 views

Why Op-amp pulse generator circuit do not providing any output?

I'm trying to design a clock with 1.8V CMOS. I've designed the Op-amp and individually it works fine (simulated with up to 10MHz pulse input) . But when I use this opamp to draw the feedback circuit ,...
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61 views

Verilog code indetermination [duplicate]

i have a problem with this code, because in the RTL simulation, the output Cookie appears as StX. I don't know why this is happening since i don't know verilog well. Can someone help me? ...
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2answers
1k views

Counter in verilog

i want to make a counter that increases by the value of its inputs, but i did the testbench and the output is undetermined, xxxx. Can someone tell me if there is something wrong in this code? ...
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1answer
128 views

Synchronize random edge to clock edge

I have a steady clock signal and another signal with random binary pulses. Is there a simple circuit that can detect the rising edge of the random pulses and generate a pulse that is synchronized to ...
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3answers
3k views

How to configure Atmel SAM D20 for internal 48MHz clock source?

I try to run a Atmel SAM D20 MCU at 48MHz using the internal oscillator (OCM8M) and the digital frequency locked loop (DFLL48M). All I achieve is a deadlock of the processor, even I use a simple "...
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127 views

Considering Transmission Line Effects for Clock Generator

I'm trying to design a clock circuit to convert a 50 MHz 5-volt clock signal down to 3.3 volts without inverting it. The concept is relatively simple, but as I never designed anything like this from ...
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4answers
360 views

In clock recovery, how is the recovered clock used to recover data?

I've been refreshing my memory on clock recovery, and I've hit some issues trying to understand how the recovered clock can be practically used to latch data bits from the input data stream. For ...
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56 views

Question on flip-flops

I came across a question which says the following,i don't understand the question and how to come up with a solution In fig,the data word to be stored is S=1001 a)If LOAD is LOW,what does Q equal ...
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3answers
1k views

Do I need a crystal to for the Atmel SAM D20 MCU to Run at 48 MHz?

I am working on a very small device and would like to use the Atmel SAM D20 as MCU (this variant ATSAMD20E16). Reading the data sheet, there is only one point I do not find clearly spelled out: Do I ...
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2answers
711 views

50 MHz Clock shifting from 5 V to 3.3 V and Bidirectional , possible?

I'm trying to design a circuit to convert a 50 MHz clock source from 5 V to 3.3 V. At first, I thought of using Sparkfun's level translator shown in the link below: https://learn.sparkfun.com/...
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1answer
140 views

Basic doubt on clear and preset inputs

I am having a basic doubt regarding the working of preset and clear inputs. Consider these two figures:- Here in figure 1, if clear is 0, then Q will be 0 from 1. But if its active low signal as ...
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1answer
125 views

How exactly do clock speeds of computers relate to operation speeds?

I was wondering about this the other day when I was explaining binary and hexadecimal to a friend of mine and this came up. The question goes something like this: How exactly do instruction ...
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1answer
126 views

Building a leading edge triggered pulse

I am trying to build a pulse generator that is triggered on by the leading edge of a clock signal, stays on for one full clock cycle, and is triggered off by the next leading edge from the clock. ...
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38 views

How to connect the counter below to the counter above

I am designing a synchronous DOWN counter that is supposed to count down from 20 to 00. I tried many different ways but the logic combinations I tried are obviously wrong as I am getting very weird ...
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1answer
124 views

STM32F4 OC Clock Jitter Problem [duplicate]

I am using STM32CubeMX to configure an STM32F4 to output a clock signal using Timer 3, Channel 4 on PC9. I have read in the datasheet PLL section that jitter shouldn't be more than 15ps RMS but I am ...
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5answers
3k views

When do you say two clocks are asynchronous?

I have a situation where reference clock of PLL_0 is coming from some clock source and giving out a clock (named C0) with freq0 and and C0 is going as reference clock to PLL_1 and giving out clock C1 ...
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0answers
199 views

STM32F4 OC Clock Jitter

I am using STM32CubeMX to configure an STM32F4 to output a clock signal using Timer 3, Channel 4 on PC9. I have read in the datasheet PLL section that jitter shouldn't be more than 15ps RMS but I am ...
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0answers
778 views

How to calculate bit time of any signal?

Given a data rate or clock rate, how to calculate bit time of any signal/interface? As per what I know, bit time = 1/data rate. Is it correct? I got a little confused when I could not calculate the ...
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1answer
273 views

Why ring oscillator showing irregular graph ?

I'm trying to design ring oscillator in CADENCE using 180 CMOS .Instead of showing inverted clocking output , output changes in less then millivolt ranges. When I connect only 9 inverter like this ...
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2answers
1k views

Generating i2s Clock Signals

I am trying to design a Pi Hat to integrate my Raspberry Pi 3 for use as an automotive head unit. I have a Texas Instruments TAS6424 and some supporting components, and am trying to design a DAC PCB ...
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2answers
526 views

Importance of an FPGA external clock

I am very new to FPGA development, but I have a relatively simple application I'm trying to implement on a Microsemi ProASIC3. The hardware I have to work with has no external clock source (i.e., no ...
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1answer
254 views

How do you change clock source dynamically on an ATtiny1634?

I'm using an ATtiny1634 for my project and I wanted to make sure the external 8MHz crystal was soldered correctly before I set the fuse to select it at boot. So here's my code from what I found in the ...
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1answer
936 views

VHDL Knight Rider

I am newbie in VHDL. In my code, everything seems right but code doesn't work properly. I couldn't find where my fault is. Any solutions? ...
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4answers
389 views

Self-clocking driver / transceiver

I'm looking for a way to transmit a clock signal and data over a single line, perhaps using a self-clocking signal such as Manchester coding. The design I'm working on has a number of chained units, ...
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1answer
247 views

Configure UCSCTL0 register MSP430F5529

First off: I'm brand new to microcontroller development, so please forgive me for the simple question. I'm trying to learn for my FIRST robotics team so we can use the MSP430 to handle some extra ...
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2answers
222 views

How to theoretically determine max clock speed for a circuit?

I was wondering what influences the max clock speed and how to calculate it for a circuit implementation. Let's take a CPU for example: From what I understand the clock speed has to be choosen so ...
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2answers
1k views

Timer configuration on STM32F4

I'm trying to configure the timer3 to have a frequency of 1KHz, without success. Here's my configurations: System Clock: ...
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1answer
141 views

Dual JK Flip-Flop Toogle Feature

I'm trying to make an 8-bit Display using 4 seven segment displays being driven by a single EEPROM (like in this video). From the video, I used the design of the 555 timer and a dual JK flip-flop to ...
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2answers
48 views

2 outputs of clock synthesizer connected together [closed]

Can anyone explain what is the purpose of the following schematic? Why are outputs Y1 and Y3 connected together?
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1answer
341 views

Is it possible to drive a HDMI output without exact clock frequencies (74.25 MHz, etc.)?

I'm driving a TFP410 parallel to DVI (HDMI) converter using a DM368. Unfortunately I can't generate the exact clock frequencies required for HDMI CEA modes (74.25 MHz, 148.5 Mhz, etc.), I'm stuck with ...
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1answer
659 views

VHDL assignment and condition at the same clock edge on parallel processes

Suppose that I have two processes in VHDL: One process is triggered on the rising clock edge and it is a state machine that sets a flag in one of its states. The second process is also triggered on ...
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1answer
180 views

Radio clock sync circuit identification [closed]

I took out a little board from a radio clock that looks a lot like this one. I believe this is used for automatic clock setting - the coil is probably used as an antenna. It looks like this: The ...
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3answers
2k views

RC circuit as clock source

I am not understanding something very fundamental here , I have read that an RC circuit can be used as a clock source. From this I assume a DC input. Playing around with my oscilloscope the only time ...
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2answers
4k views

Why are there 2 clock rates (core vs memory clock) in the GPU?

I learned at school that the clock rate inside a computer is the signal that keep switching between 0 - 1 (or active - inactive). There's also another delayed clock with the same frequency. These 2 ...
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3answers
299 views

Two phase clock on a breadboard

How can I make a two phase clock on a breadboard (i.e. no surface mount components) without using a microcontroller? Phase 1: _ _ __| |___| |__ Phase 2: ...
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1answer
230 views

Sync clock derived from AC power source [closed]

I am developing a wireless device which stores data by sampling an Analogue sensor at a specific time. The only 'wires' to this device are the two power wires. I am using a 12V AC power supply and I ...
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2answers
147 views

Pic32MX Clock too slow

Using pic32mx340F512H and XC32 compiler and ICD3 debugger on MPLAB. So I'm working on displaying colors on a screen using VGA protocol and, thus, need to max the clock speed. The standard for a pixel ...
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1answer
353 views

Using negative clock edge in phsical design

In Verilog, is it ok to use negedge of clock. Can a memory element be triggered at the negedge of clock? How robust will be the design practically in the chip?
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439 views

Jitter of UART TX pin

I'm developing a small robot using the STM32L152C Discovery board. I'm currently trying to configure the board using the STM32CubeMX. I've never worked at this very-low level (my experience is much ...
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3answers
364 views

How to create a counter to display 6 digits using anodes?

I'm trying to write a digital clock on vhdl for an fpga that runs on 100mhz. I can write it on 4 anodes by creating a counter as shown below(count1 = 249999), the digits seem pretty clear. However, ...
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1answer
859 views

Connect STM32 Ethernet to PHY - clock signal

I want to connect MAC available on STM32F745 to KSZ8041FTL (PHY) via RMII. I will clock PHY from external 50MHz clock generator, connecting clock to the REFCLK input of PHY. But what about STM32? ...
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1answer
228 views

4 quadrature clock vs 2 quadrature clock + falling edges

I started a digital design - a high precision time counter actually - that will be implemented on a Xilinx FPGA. I will describe it in VHDL. I read several papers about this subject and I found about ...