Questions tagged [cmos]

"Complementary Metal-Oxide Semiconductor" is a process which implements a combination of PMOS and NMOS transistors. Most current digital logic is implemented in CMOS. Its cost-effectiveness due to being so widespread means many other applications have become common as well, such as in analog design, image sensors, telecommunication, etc.

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36 views

CD4069 toggle switch

How to connect the trigger out instead of the switch? Like a toggle switch. The first trigger out activates the relay and remains ON infinity, the second trigger out deactivates the relay and remains ...
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130 views

Diode I-V characteristics

I am studying device design, starting from diodes. I am using the VisualTCAD simulator which allows us to simulate device fabrication and simulation. The diode specifications are as follows: n-doping:...
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74 views

Will connecting unused CMOS outputs to VCC damage the chip?

I am using a 74HC154 4x16 decoder in a design I'm working on and I'm not using the last four outputs. During PCB routing it would be very convenient if I could tie these unused outputs to the VCC ...
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966 views

How Does an Adjustable Transistor Size CMOS Driver Work?

Background The source-terminated reflected wave switching scheme is a familiar one. One just needs to add a source-series terminator, which added together with the driver's output impedance equals the ...
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70 views

Method to measure SRAM static noise margin

I have been reading a few papers on static noise margin calculation in SRAM. All of them provide a graphical approach which involves plotting the butterfly curve of cross coupled inverters and ...
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1answer
42 views

Transmission gate conducting in OFF state

Here is a part of my circuit that I am trying to simulate in cadence virtuoso. It has two transmission gates, the one in path of charging the capacitor is on and other one is OFF. Supply voltage is ...
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119 views

Two CMOS switches connected in series

I have seen some circuits like the one below; why do they use two switches in series instead of one switch? Aren't two switches in series equivalent to doubling the length of one? I'm sorry that I ...
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61 views

6T SRAM cell write operation not working as expected in virtuoso

I am trying to play around a 6T SRAM cell by simulating it's write operation in Cadence Virtuoso. The NMOS and PMOS specifications are 120/45 nm and 310/45 nm. The Bit select is kept at constant 1 and ...
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109 views

Finding the gain expression for this CMOS operational transconductance amplifier

So here's the circuit: I think M2 is a common source amplifier and M4 a common gate amplifier, so they form a cascode amplifier where the gain is given by : Av = -gm2 * r0, r0 is the impedance at the ...
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74 views

The unusable state of S-R Latch simulation in LTSpice

I created an S-R Latch in spice using MOS transistors (180nm) and gave noth S and R inputs as 1 (knowing that this state is unusable as both Q and Qbar will be metastable). But I was expecting ...
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Why is this circuit a two-stage amplifier?

I am studying the following circuit and my professor calls it a two-stage amplifier. However I don't understand why as I just see a NMOS differential pair: MN0 and MN1 a PMOS active load (current ...
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SPDIF to CMOS logic

I am trying to get around my head on the three questions below. Is SPDIF protocol is really driving 0.5 V pk-pk without having any DC offset? If yes, HDMI1.4 mentions ARC protocol which is adhered ...
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32 views

Plotting MOS resistances in transmission gates in spice

I am trying to plot the resistance of MOS transistors in transmission gates, as a function of output voltage in ltSpice, as shown in this figure from Jan.M.Rabey: I have a circuit with same ...
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54 views

Op Amp design - open loop gain 73dB, closed loop gain -200dB

This is my first time designing an op amp, using 180nm in Cadence. Two stage design, 1st stage is NMOS differential pair with PMOS current mirror load, second stage is PMOS CS with Miller capacitor. ...
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78 views

Variation in Tphl of MOS nand gate due to input patterns

I was studying the variation of propagation delays in CMOS NAND gate from Jan.M.Rabey Digital IC Design book. It has this table given for Tplh and Tphl for different input patterns applied at inputs A ...
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65 views

MOSFET I/V characteristics. How does this mosfet conduct current?

I am currently studying the basics of CMOS design and came across the following problem in Razavi's textbook with respect to a NMOS transistor : The question is simple: Let \$V_{SB}\$ = 0 (source-...
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111 views

CMOS (analog) switch output has a few hundred mV offset when output is disabled

I'm using an TS12A4514 CMOS switch in order to isolate some digital lines from one device to another. Power rails are 5V & 0V (GND). While the switch is enabled (enable input is 5V), input ...
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47 views

How do the dimensions of a MOS tranistor affect the gain of a CMOS inverter?

I am simulating the voltage transfer characteristic curve of a CMOS inverter, while varying the dimensions of L and W of MOS. Comparing the results for two scenarios, I have the following results: ...
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72 views

How to configure / construct a CMOS sensor to act on changing signals only?

You all probably know how a CMOS sensor works, at least in general. In short, it consists of a lot of pixels (photodiode plus amplifier and so on), and each pixel is read out individually (different ...
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How to draw a stick diagram from this circuit

I'm new to VLSI. I am currently working on a project to make a full 1-bit subtractor. I translated the Bout (carry) logic into Bout = A'.Bin + A'.B + B.Bin. Below is my Proteus simulation. I know the ...
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1answer
54 views

Current source not working in LTspice XVII

I am trying to implement a circuit (CMOS implementation of DVTC) with the help of LTspice (I'm very new to this software.) The built in current source component is not working in LTspice. Following is ...
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I am trying to design a basic CMOS Image sensor

I am new to electronics so I might be doing some bad mistakes on my design but anyways, I'm trying to build a CMOS Image sensor using Proteus, and I couldn't find some basic tutorial to follow, Yet I ...
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312 views

Why is the output of an Op-Amp given by the open loop gain multiplied by the input differential voltage

When designing op-amps at the transistor level, the op-amp output is given by: vout = Aol(vinp - vinm) where vout, vinp and vinm are small signal changes in the output and input voltages. How come ...
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56 views

finding inverting vs non inverting functions

So Im learning cmos systems and Im struggling with the pmos and nmos part of it. So for example given F=minterms(m0,m1,m2...) I can do the kmap and get the function no problem but how do I know if ...
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48 views

change cmos inverter switching threshold

I'm working on a problem that requires me to change the switching threshold of a cmos inverter to a different Vout when Vin is the same. All I know is this relates to the W/L ratio of pfet and nfet. ...
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What does "field" in field oxide mean?

This is an excerpt from Design of Analog CMOS Integrated Circuits by Behzad Razavi. What does "field" in field oxide mean here, electric field?
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VTC curve and the delay time of CMOS inverter

When the VTC curve shifts to the left for a CMOS inverter. why is that the delay for both Tphl and Tplh both increases? What's the reason behind it and what is the quantitative explanation?
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38 views

VTC curve of cmos when Id does not saturate [closed]

For transistors, if the Id does not saturate at the saturation region (nmos: Vds>Vsg-Vt, pmos: Vsd>Vgs-|Vt|), but follow a linear relationship. How will the inverter VTC curve change? I am ...
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4answers
85 views

Why is the power dissipated by a PMOS the same as that stored in the capacitor?

When a CMOS inverter switches from low to high, it took half of the energy dissipated to PMOS and half the energy stored in the capacitor. Why is that? I know how to derive the amount stored in the ...
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60 views

CMOS layout: Simplification and Euler path

what is the simplest form of Y = (logic)' in order to find a Euler path common for pull-up and pull-down network and then implement it through CMOS layout? I have issue finding the best form of the ...
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90 views

Controlling relays with logic gates

Pretty new to electrical engineering world, so probably rather simple question. I´m designing control system for tractor trailer hydraulic system. The system is 12 V and solenoids what I am using ...
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81 views

Manchester and NRZ coding schemes

How does NRZ recover the clock? For example, Manchester coding is a self-time scheme, but we still need to have DLL or PLL for the recovery, it can be done without those CDR circuits? and back to NRZ, ...
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Would the old series 4000 CMOS logic series have evolved over time?

Would the old series 4000 CMOS logic series have evolved over time? The manufacturers surely have bought new machines and are not using the same machines from some odd 40 years back. Would they have ...
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74 views

Cd4030 vs CD4070 exclusive Or gate

is there is difference between the CD4030 and CD4070? both are Quad Exclusive-OR Gates, the only difference i can tell that the Texas instruments datasheet from the Cd4070 is newer. both are rated for ...
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60 views

Creating bi-polar signal from IC's

I'm trying to create a bi-polar square wave from a flip flop but all I get is a positive result. It never goes below GND. I know the second (lower) transistor gets positively biased and maybe this is ...
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99 views

CD4040 clock input

Would you place a Cd40106 inverter before the clock input of a CD4040 or would you be half a cycle to late compared to the rest? ... while clocking a shift register. since the CD4040 is negative edged....
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CMOS Transmission Gate Body Bias in 74HC4052

Page 2 of the 74HC4052 data sheet shows a diagram of a transmission gate. I'm curious about the way the body of the NMOS transistors is biased. It looks like when the t-gate is off, the body is ...
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How are such ICs called ? (Level-shifter + CMOS push-pull driver)

A lot of times I need a circuit like below. Namely, a logic level signal should set a higher voltage (e.g. 12 V) and higher current (few 100 mA, but not Amps) push-pull stage to a hi/lo state at ...
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Substituting the CD4006 with a CD4021

During a YouTube session, I stumbled upon an interesting circuit. I just had to digitize it and archive it. Since the CD4006 is pretty hard to obtain for several years now, like Mouser doesn't offer ...
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Can I use a CAT28LV64 at 5V?

I'm trying to find good EEPROM/Flash memory that I'm able to use on a breadboard for preferably cheaper than $12. I came across the CAT28LV64 and noticed that it fits very well with my needs. The only ...
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65 views

Would the CD4053 still be capable of handling tiny voltages?

Since the CD4053 and other CMOS ICs can't handle a bi-polar 12V circuit, I was wondering if the CD4053 would still be accurate once the control signals / audio has be scaled down to millivolts ...
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37 views

Advancing the clock of a CMOS IC with multiple signals

What would be the best way to advance the clock of a CMOS OC from multiple signals? In my situation the "upper" signal puts the system in working and the system itself generate the next ...
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61 views

Why are complementary gates inverting? [duplicate]

"Complementary gates are inverting, non-inverting functions need an inverter" is something I see in almost every CMOS gate resource, but I don't understand why at all. I feel the math behind ...
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176 views

How does an operational amplifier amplify both ac and dc?

Either input pin can be given a positive or negative voltage with respect to the other input pin and also operates the unchanging DC difference between the two inputs (\$f=0\text{ Hz}\$). Then how is ...
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755 views

Do MOSFET logic gates necessarily need an N channel MOSFET?

I've been studying CMOS logic gate design, such as an inverter here: Why do we need the N-channel MOSFET at the bottom at all? Couldn't it be replaced with a simple resistor into ground like this?
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Is the layout of this transistor fingering better?

I was reading the post and there are some points that I would like to discuss more. The image below is from Razavi book where the figure c is mine. Below is an ...
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Is a pinned photodiode necessary in a 4T APS cell?

I would like to know if a pinned photodiode (PD) is required or desirable for a 4T APS cell that performs global shutter? If yes, Why is it so necessary instead of using a conventional PD?
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105 views

What is a post decoder?

I have heard a bit about pre decoders and post decoders recently in circuit design. When I saw the circuits, the pre decoder is same as the normal decoder in every textbook or website. But I haven't ...
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2answers
129 views

12V logic control of 3 LEDs

I am building a circuit and am stumped without using many relays to achieve the result. I would appreciate any help I can get. Basically I have 3 different colour LED's in a (push button) some of ...
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96 views

Is this actually a good CMOS NAND gate?

This is from www.electronics-tutorials.ws which I just discovered yesterday. The site has a plethora of electronics engineering content, more than I've ever seen from a free site. I came across this ...

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