Questions tagged [cmos]

"Complementary Metal-Oxide Semiconductor" is a process which implements a combination of PMOS and NMOS transistors. Most current digital logic is implemented in CMOS. Its cost-effectiveness due to being so widespread means many other applications have become common as well, such as in analog design, image sensors, telecommunication, etc.

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Differences in CMOS fan-out between the two logic level

I was taught that a number of inputs A CMOS gate can drive when it's output is low differs from the number of inputs it can drive when its output is high. Is it because of different properties of the ...
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How to design an amplifier to meet particular specifications

I need to specify the (W/L) ratio of transistors and the value of the current source in an amplifier as shown in this picture so that these specifications are met: *the height of the input step for ...
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IC design to amplify from microvolt to volt for making a comparator

I am developing an IC in CMOS technology which, among many other things, I need to compare one signal with another. I need a square wave signal above a limit to result in VDD, and signals below that ...
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Analog CMOS Design

I have been studying CMOS design from Baker's book. In the amplifiers chapter he places a "big" resistor between the input gate and output drain of CS derived amplifier stages. What is its ...
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Consider lowering VDD to save power in a static CMOS gate. Also scale Vt proportionally to maintain performance

Will the dynamic power consumption go up or down? Will the static power consumption go up or down? Explain with proper analytics. I came accross this question while solving a question booklet issued ...
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Buffer SWD programming pins for 20VDC tolerance?

I have an application that I'd like to use some existing connector pins for SWD programming. All exposed pins and pads on the device must be 20VDC tolerant. I think I could solve this with an ...
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Analyzing the push-pull output CMOS stage

My problem is, when V2 is 5V, M2 will cutoff obviously. So now if I measure the open-circuit output, which result will I get? Since the source of M1(NMOS) is floating without connecting to anything, I ...
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Some confusions on a basic CMOS multivibrator question

This is a previous exam question, so I do have a solution already, I am not trying to make you solve my homework etc. Few questions in my mind regarding this question above, There is not a given ...
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Safety considerations (for parts) for a beginner building with expensive parts

I'm building for the first time (for me) a circuit with an expensive part (a $80 DEC J11 CPU) and would like to know some "safety" tips so I don't inadvertently destroy the thing while playing with it....
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Phase margin plot of LDO

For this LDO circuit design at https://github.com/promach/LDO/tree/development , 1) which exact circuit node(s) contributes to the zeroes near 1MHz after removing CL ? 2) If I remove "AC 1" from ...
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Why it is preferred to use PNP and PMOS for pull-up, and use NPN and NMOS for pull-down

I have noticed that when I was designing universal logic gates like CMOS NOR gate that uses PMOS for pull-up and NMOS for pull-down. Then I faced it for second time with the H-bridge circuit, but ...
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Why CMOS turns on when input voltage is zero?

When the input voltage is high, Q1 is off and Q2 is on. In this case, the shorted Q2 pulls the output voltage down to ground. On the other hand, when the input voltage is low, Q1 is on and Q2 is off. ...
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Bulk fixing CMOS

Hello everyone I'm having trouble finding the material that talks about CMOS regarding bulk fixation. I know that the bulk is welded in well n (n-well) or well p (p-well) depending on its structure, ...
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Analog CMOS IC layout: DRC, DFM, DFR

Regarding CMOS analog IC layout, what are differences between DRC, DFM and DFR? What I understood during research: DRC (Design Rule Check) - checks if a laid out block follows technology rules what ...
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How can I determine the max frequency of the clock signal for a 3 bit ripple counter

I can't figure out how to determine the max frequency at which a ripple counter functions properly.
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CMOS NOT gate output

Can somebody please tell me why do we have those tiny random spikes on the output signal? And why does the input wave behave like in the picture when we reduce the frequency of the noise source to ...
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voltage follower operational amplifier

I am trying to simulate a buffer with an op-amp using CMOS, I am using Cadence. The gain I am getting is low (16dB). I am trying to reach a gain of 90. how can I increase it? https://www.ti.com/lit/...
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Using CMOS logic ICs to drive a P-channel FET

I am attempting to implement a latching circuit without software. The results thus far seem promising, but now I want to drive a control line on a solid-state relay using its output as a high-side PNP ...
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channel length in Cadence

I am using Cadence software to design a CMOS circuit and I am using the GDPK180 library. Can I modify the length of the transistor to be different for the transistors or it should be the same for all?
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Trade-off between LDO max Iout AND PSRR

PSRR is inversely proportional to output impedance of LDO. But Iout_max of LDO is proportional to width of output mosfet (M20) , Rds of M20 is inversely proportional to width of M20. Given that ...
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How to draw the stick diagram of a JK flip flop

Recently me and my friends have been tasked a project to design a frequency divider using a JK flip-flop (divide by 4). After drawing the transistor circuit, I noticed that it was complicated for me ...
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PMOS and NMOS Current loads in Common Source Stage

I am new to the concept of Single Stage amplifiers design using CMOS. In that, I came across a concept of using current source as loads in design of Common Source Stage, where it was mentioned in a ...
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Build a circuit that will output an analog voltage proportional to the duration of a pulse at the input (pulse-width detection ) CMOS

I don't have a strong background in electronics, so this task is challenging for me. I need to build a circuit that will get an output like this. In my circuit, I can only use voltage sources, ...
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Large signal vs small signal analysis of Differential amplifiers

Here is a question from the textbook "Design of Analog CMOS Integrated Circuits" (Razavi)- Assuming the circuit shown is symmetric, sketch Vout as (a) Vin1 and Vin2 vary differentially from zero to ...
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How to find Input capacitance and output resistance of a CMOS circuit with spice

I have a 2-input NAND gate spice netlist (generated from a Tanner Ledit layout) where I have to find each input's capacitance and the output resistance. I am to use a 1nF load capacitor and a 10 Kohm ...
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How to find he Kpn,Kpp parameters for the given 130nm CMOS models using LtSpice?

The model file is present at http://ptm.asu.edu/modelcard/2006/130nm_bulk.pm I tried finding the value of unCox by finding the value of drain current, gate-source voltage and the threshold voltage for ...
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LDO circuit questions

I have done a LDO circuit at https://github.com/promach/LDO I have few questions : Why in the second bode plot (which might be problematic PSRR), gain going up near unity-gain frequency is often a ...
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Dry or wet etching in fabrication cmos chip?

What types of etching are used in conventional chip fabrication technologies such as TSMC 0.18, dry or wet?
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Why do we use 2 transistors for each path of a MUX in CMOS?

Below is the schematic of a CMOS level 2to1 multiplexer. As you can see that if we want to choose A0, we set S input as Logic-0. My question is that what happens if we remove one transistor from ...
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Which is the simplest way to transform +9V and +5V into 3.3V CMOS acceptable digital levels?

I have a device providing a signal of either +9v or +5v (depending on some action on the device) plus a GND. I would like to convert the Vin signal into something readable as a digital 1 or 0 on CMOS ...
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Which one is the correct symbol of enhancement type MOSFET?

I studied MOSFET from ' Electric Devices and Circuit Theories by Robert L. Boylestad ' The symbols of depletion type and enhancement type MOSFET are given below from the book. But recently, in ...
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VTC of Pass Transistor AND gate in LTSPICE

I am trying to plot the voltage transfer characteristic of this pass-transistor AND gate in Ltspice in order to obtain the following graph: However, when I tried to do it, I did not obtain the ...
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Signal Conversion 36V to Logic Level with Zener Diode

I have 8 cells in series and I want to check them, whether all are connected. I came up with the following schematic: simulate this circuit – Schematic created using CircuitLab My question is ...
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How do I design a RC phase shift oscillator using opamp with the help of cmos (pmos and nmos)?

Designing the opamp using cmos (pmos and nmos) to construct RC phase shift oscillator using opamp with the help of opamp (constructed using cmos.)
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Why PBTI is recoverable, and NBTI is not recoverable?

Why we discuss more about NBTI in mosfet, not PBTI? PBTI - postive bias temperature instability NBTI - Negative Bias temperature instability
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Unused output of LTC6957-4 (or LTC6957-3)

The LTC6957-4 has two complementary CMOS outputs, and I only need one. What do I do with the unused output? My goal is to minimize noise on the used output signal, REFCLK_OUT. The datasheet is clear ...
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What exactly do the well taps in MOSFETs do and how?

Do they affect the flow of charge carriers or charge concentrations at all in the device? How so? Up to this point I've tried to visualize the effects that the various doped areas had on device ...
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Why does this input pin stay high?

simulate this circuit – Schematic created using CircuitLab I am working on a project with some 8-bit D-Flip-Flops (using CMOS logic), feeding the first output into the second, the second into ...
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PC Mainboard - CMOS Bios Battery Circuit

I could imagine the CMOS Bios Battery circuits are quite similar on all recent mainboards. What does it look like and how does it work? Background: My mainboard started draining the bios battery (...
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How to test a cmos sensor without breaking it?

A couple of weeks ago my dad gave me a Syma X5C H5C camera that he found. I wanted a camera for my robot project and I tried to just take the camera but I found a ...
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switiching an input between high and low state with a trigger signal?

I want to build an electronic analogue SPDT switch that switches on a trigger/rising edge. A SPDT CMOS switch control is held high or low for either output. This could be done with 2 outputs of a ...
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How can the design of CMOS Transmission gate or Pass Transistor be improved to get a response similar to the ideal VCS like in LTSpice?

I was trying to implement a Voltage controlled switch. I tried to implement it using CMOS TG and pass transistor in Cadence Virtuoso and used the nmos_1v model in gpdk090 with the default W/L ratio. ...
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What is the purpose of having two type of output interfaces on this ADC?

The ADS4126 comes with a Double Data Rate (DDR) LVDS output interface and a I have following questions: What criteria is used to decide which one of the two to use? Can both be used to read the ADC ...
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Implementing a CMOS TriState Inverter

I have been learning about CMOS Tri State inverters, and I was wondering which one of these two ways is a better implementation of this circuit. The first is what we see in all textbooks : With the ...
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Pull-up/ pull-down resistors in CMOS gates

Can someone help me with understanding why the next two circuits have those outputs? My initial schematic contains only one inverter, and the signal is 5V for output high state, and 0V for low. Now, ...
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CMOS inverter in series

I have the circuit below. Now my question is: why the rise time and fall time measured on Vout are the same as in a circuit using only one inverter gate? I know the propagation delay is the sum of ...
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Determining width and length from CMOS inverter layout

How do I determine the width and length from the following cmos inverter layout, given that lambda=0.25um? The answer is Wn=1.0um, Ln=0.25um, Wp=0.5um, and Lp=0.25um. I know that the length is equal ...
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Why PMOS act like “close switch” when zero voltage

in PMOS that Vtp less than 0 , from what I understand if We give Vg less than Vtp it has current flow from source to drain ,on the other hand if we give Vg more than Vtp it cut-off. but in digital ...
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Fabrication process of ICs

My question simply is why ICs are made using layers? Why they have used this method specifically ?
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What is the maximum frequency of CMOS level triangle wave?

What is the maximum frequency of CMOS (3.3V) level triangle (or square) wave that I can achieve with serial discrete ICs (for example: discrete PLL or DAC + OpAmp cascade)?

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