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Questions tagged [cmos]

"Complementary Metal-Oxide Semiconductor" is a process which implements a combination of PMOS and NMOS transistors. Most current digital logic is implemented in CMOS. Its cost-effectiveness due to being so widespread means many other applications have become common as well, such as in analog design, image sensors, telecommunication, etc.

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Mos circuit amplifier with multiple stages , overall gain

I have the following circuit and i am trying to find uin/vout. My thought process is that M3-M4 is a Cmos inverter so i can calculate the gain until that point as A1= -gm3(ro3//ro5) How can i find the ...
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25 views

Cmos vtc characteristics

Why does the vin=vout takes place at the voltage of (vdd/2) only in the case cmos inverter characteristics? and how to estimate the value of (vout) in every case, so that we can establish ...
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25 views

Is a DMOS potential free? (in case of TPIC6C596)

I've been looking at the Datasheet of the TPIC6C596 and I'm not sure if the DMOS that is mentioned in the package can be used as a potential free. I also don't know in general if a DMOS can be used ...
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33 views

Setup and hold in flipflops

Usually the data launched at 1st clock edge will be captured at 2nd clock edge. But Is it possible to launch at 1st edge and capture data in same clock edge? The clock to capture flip flop is delayed ...
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21 views

What is propagation delay in cmos nets?

I have read somewhere that signal travels as electromagnetic waves in wires near to speed of light. The signals are brought to destination by EM waves. Then what does electrons do? If signals travel ...
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119 views

Why propagation delay is measured at 50% of the input and output waveform?

I didn't find the concept of propagation delay measured at a particular point on the waveform.
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89 views

Which input of NAND is preferred and why? [duplicate]

Let A and B be two inputs of the NAND gate. Say input A arrives at the NAND gate later than input B. To optimize delay of the two series NMOS inputs A and B which one would you place near to the ...
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60 views

simple six-position voting machine into a 7 position voting machine

I'm new to learning about full and half adders and what not. but I am struggling to understand this question out of my study manual. The pictures shows a simple six-position voting machine module ...
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65 views

Frequency Divider Analog Circuit issue

I am trying to implement a divide-by-two circuit quoted from the book "Low power CMOS circuits : technology logic design and CAD tools" by Christian Piguet Could anyone advise about the spice error "...
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63 views

Why does the current in MOSFET have a quadratic function (explain logically without using the integration method)?

The current equation relating Vds ,Vgs and Vt is already known to us ,but if there is any way we can find out how it varies quadratically without using the formulae?
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61 views

Probing with oscilloscope causes current drop

We are testing a fabricated chip with expected output current of around 4mA which is then used to charge a button cell. The input is from a PV cell. However, when we attach an oscilloscope probe onto ...
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1answer
69 views

MOSFET switching on

I have a doubt. Consider an N-MOSFET: which is the voltage that can switch on it? The voltage between Gate and? Sometimes I read "between Gate and Bulk", sometimes "between Gate and Source", sometimes ...
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56 views

Finding transistor width for equal rise and fall times

I am trying to understand how the below CMOS transistor schematic has approximate equal rise and fall times (resistance pull up equal to resistance pull down) Below is the schematic: I notice that ...
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23 views

CMOS IC Dynamic Edge-Triggered Flip Flop setup and hold time calculation

Before explaining i should point out that i refer to changes of signals in the text as a reference change on which i will calculate these times as 50% change of one signal to 50% change of the other ...
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74 views

opamp constant-gm bias circuit

I try to incorporate the constant-gm bias circuit (Figure 6 in Improvements_in_biasing_and_compensation_of_CMOS_opamp) into the PFC (positive feedback frequency compensation) opamp, but it resulted in ...
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23 views

Can the scanning speed of an electronic rolling shutter CMOS sensor be controlled?

I'm not certain I'm asking this correctly as I don't entirely understand how such a camera sensor works, so help me out with a couple of areas please! I want to program something that makes use of ...
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34 views

CMOS switch with “negative” current

In a project, I need to swap the polarity of a 12V power/signal and GND wire combination electronically. The current flow is between 7 and 28 mA. I'm using a DPDT relay for this - the input wires are ...
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79 views

CMOS Inverter Circuit Analysis

So I have a circuit shown below, that looks to me likes it's a CMOS inverter circuit. In this question, we're asked to find the current and voltage across drain-source voltage of the NMOS component. ...
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110 views

Detect Infrared beam projected onto X-Y plane. Save and display coordinates. CMOS sensor?

I'm working on a project in which an IR laser is pointed perpendicular to the surface of an X-Y plane (Think like the old game "Duck Hunt"). I don't know where the IR beam will land on the plane but ...
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58 views

What is the effect on propagation delay when we have a CMOS circuit with multiple transistors connected in series?

How does the fact that in a series connection of two or more transistors only one is connected directly to gnd (in case of nmos transistors) or vdd (in case of pmos transistors) effect the change of ...
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49 views

Single Stage Amplifier CMOS - Biasing Issues

So this is kind of vague question. I'm wondering what the approach to biasing MOSFETs in saturation is. For the following circuit, I really have no specifications - I'm just trying to play around ...
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54 views

This SR latch built with 180nm CMOS does not work in ltspice. How do I fix its behavior and parameters?

EDIT: I copied over the latch from another larger model that had Vdd defined, but missed it when copying over the design. However, after adding in Vdd, I still run into this confusing issue where the ...
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114 views

LTSPICE Simple MOS-FET Stacked Current Mirror/Cascode saturation threshold less than expected

I am running a few very rudimentary cmos circuits in LTSPICE. For some reason, when designing stacked mirrors, I seem to get a much lower saturation turn on thresholds would be expected. I've tried ...
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108 views

What are the advantages of CMOS operational amplifiers vs bipolar in the same class?

Is there something else than Rail-to-Rail output and possibly lower power consumption for low frequency applications? Or Rail-to-Rail is the main one?
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80 views

Using NMOS or PMOS for voltage controlled switch?

If I want to use an NMOS or PMOS as a voltage controlled switch, when would I know to use one over the other? I know a PMOS activates with a LOW at the gate and for an NMOS when HIGH at the gate, but ...
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2answers
116 views

When is it reasonable to ignore channel length modulation in MOSFETs?

It is known that for smaller technologies, the channel length modulation effect is more prominent. However, is there any condition (biasing,voltage levels, transistor sizing ..etc) from which we can ...
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49 views

Performance issues when using CMOS SR Latch with 180nm transistor models in circuit simulator

I am trying to incorporate a CMOS SR latch made with 180nm Level +49 transistors into a larger circuit but am running into issues. I am hoping this community can point me in the right direction of ...
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70 views

Emitter-coupled logic operation

For the operation of emitter-coupled logic and sedra smith book, 1) Compared to CMOS, why ECL is the faster logic family given that it requires so many transistors to propagate to output Y (T5 ...
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leakage power with respect to Switching activity

Can anyone explain me relation of leakage current or power with respect to Switching activity(S.A). I'm assuming that with increase of S.A, the power dissipation of circuit increases in-turn ...
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3answers
79 views

P-MOSFET failures

simulate this circuit – Schematic created using CircuitLab P-Mosfet Datasheet The goal is that 5V (or logic high) appears on U3 when there is logic low on U4 and logic high on U2. That 0V (or ...
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71 views

STM32F407 CMOS or TTL or HC

I wonder which logic technology is STM32F407 MCU based on.. CMOS or TTL or HC or LVT etc? Although its mentioned in the datasheet that the GPIO's are CMOS and TTL compliant. I am concerned about this ...
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1answer
194 views

NRST pin of unpowered STLINK V2

I am using the STLINK from a Nucleo board in order to flash and debug a STM32F7 MCU on a custom board. Everything works fine except when STLINK is connected to my custom board AND unpowered. Indeed, ...
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17 views

Drain capacitance of CMOS inverter

How to find the total drain( NMOS+PMOS) capacitance of CMOS inverter in cadence virtuoso?
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39 views

CMOS Inverter output for a given transfer characteristics

I have tried solving the below CMOS problem with a given transfer characteristics but my answer is wrong. Answer should be 0.25. Could someone please point out where I went wrong ?
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82 views

74HC4060 lower frequency limit

I need to sequence some micropower (low-microamp range) logic at a once-per-several-minute rate, and am falling back on the good ol' 4060 as my timebase (plus a 138 and a 534 for the sequencing). I ...
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71 views

Possibility to change IC HCF4060BE to IC 74HC4060

I recently purchased a very old synthesizer that uses CI HCF4060BE and I want to know if it is the memso that CI 74HC4060. To help here is the CI datasheet HCF4060BE: LINK Here the dataset of the CI ...
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2answers
141 views

What is the point of 2 inverters in series? [duplicate]

In the datasheet for the Nexperia HEF4543B, in the logic diagram, there are 2 inverters in series: What is the point of these inverters in series?
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Help Identifying a CMOS optical mouse sensor?

I'm working to repurpose the trackball assembly of a Logitech Trackman wired mouse for use in an experimental rig. I assumed that Logitech would use Avago's ADNS series of optical flow sensors, but it ...
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2answers
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MOSFET construction

I've just read an application note and I was confused about this sentence: "Engineers often think of a MOSFET as a single power transistor, but it is a collection of thousands of tiny power FET cells ...
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1answer
121 views

Switching threshold of CMOS inverter [closed]

How to find the switching threshold of CMOS inverter from it's transfer characteristics in Cadence Virtuoso?
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1answer
50 views

MOSFET treshold voltage

Does anyone know how MOS treshold voltage varies if the physical distance between source and drain decreases ?
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2answers
190 views

Shot or thermal noise of a MOS transistor

I'm trying to compare the shot and thermal noise contributions in a MOS transistor. In the literature, the above-threshold MOS transistor has only thermal noise, which is found by integrating the ...
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3answers
60 views

zero AC gain of CMOS inverter

Why is the following AC analysis of CMOS inverter resulted in zero AC gain (vout/vin) ?
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1answer
63 views

Current to Voltage Converter in CMOS [closed]

If I want to use a 2-stage opamp for the current to voltage converter application, How should I check for the stability of the circuit? Will it need any kind of stability correction? An uncompensated ...
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1answer
56 views

Why is it not sensible to connect many (MOS) transistors in series?

For example a NAND-gate with 3 inputs has 3 NMOS in series and 3 PMOS in parallel. But why aren't there cmos gates with e.g. 10 inputs?
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dc sweep convergence issue for cmos inverter

I am having some convergence issue with DC sweep for a CMOS inverter. To duplicate the exact issue, see the following log as well as the attached netlist files, together with modelcard.nmos and ...
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75 views

How does this circuit with inverters work?

What this does this circuit do? I suspect it is an amplifier, but don't know how it amplifies. For example Inv 5 and Inv 6 are connected in parallel with reverse sides but there is a wire between ...
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2answers
64 views

CMOS Inverter circuit

I want to design CMOS Inverter which gives: 0 volt input --> 5 V output Any positive input voltage above threshold voltage --> 0 V output. On simulating, it is giving me alternatively +2.5v and -2....
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30 views

Measurement of Cmos Parasitic capacitors

i've had a question which asks if we assume that capacitance of capacitors with w/l of 1u/0.5 are then what are capacitance of capacitors (with the actual w/l) now i know cgs in saturation for ...
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67 views

Common Mode and differential Mode gain of this Cmos diff Amp inverter

This is one of questions our prof gave to students in recent years and im preparing myself for this exam. What is Common Mode and differential Mode gain of this Cmos diff Amp inverter? i understand ...