Questions tagged [cmos]

"Complementary Metal-Oxide Semiconductor" is a process which implements a combination of PMOS and NMOS transistors. Most current digital logic is implemented in CMOS. Its cost-effectiveness due to being so widespread means many other applications have become common as well, such as in analog design, image sensors, telecommunication, etc.

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Dummy Switches - Charge Injection and Capacitive Feedthrough

[R. Jacob Baker] I have some confusion regarding a technique using dummy switches to compensate for charge injection and capacitive feedthrough. How does M2 compensate for the charge injection of M1?...
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Cascode Amplifier: clarifications about output resistance and working point of transistors

let's consider this cascode amplifier (here the reference): I have the following questions: 1) Is it good as a voltage amplifier or as a transconductance amplifier? I do not understand it because: -...
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Is the minimum size of a poly contact in SCMOS 2x2 or 4x4?

By "SCMOS" I mean the "normal" MOSIS SCMOS rules, not SUBM or DEEP rules. All dimensions implicitly measured in lambdas. Also note that I have noticed that SCMOS rules are no longer as relevant as ...
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Diode Connected MOS

let's consider the equivalent circuit of a diode connected Mosfet. Since the current source between drain and source is: gm * Vgs = gm * Vds and it is proportional to Vds, it means that this ...
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Simulation LTSpice a two stages Operational Amplifier with CMOS

I need to simulate this circuit on LTspice. In the exercise I have to balance the parameter to makes it work and estimate the gain in the center of the band. The inputs are v+ and v- (differential ...
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MOS working point in a differential analog mixer

let's consider this simple configuration of a balanced differential mixer (analog multiplier): I have understood that the local oscillator is generally a high signal, while the radio-frequency signal ...
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55 views

Delay circuit having different high-to-low and low-to-high delays

I'm trying to design an integrated circuit that can implement a delay of approximately 100 ns, working with a 180nm process. With this process, an inverter has a delay of picoseconds, so it would ...
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43 views

What does this circuit with an analog video signal to the emitter and a TX signal to the base of a an NPN do?

The CAM1_AHD is the signal coming from a camera and it goes to the TVI receiver as well as to the emitter of the transistor. The video signaling scheme is analog. The TVI receiver is TP2825 and in the ...
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Large Signal Transconductor

I have a basic question about the following circuit, which is introduced in the book " and is described as a "large signal transconductor": It says that: the capacitance value is chosen to be a ...
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64 views

CMOS Flip-Flop Design

I'm new in Transistor-Level Design and for that reason, I have practiced and learned from designs that I found on google. When I tried to design a mux from scratch without relying on the design of ...
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What happens to the body effect and the channel length modulation for the short channel devices?

Does body effect and channel length modulation effective for both, short and long channel devices?
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How is the propagation delay of a logic gate affected by the amount of inputs (fan in)?

I was trying to find out what parameters affects propagation delay and how. When trying to discover if somehow the propagation delay could increase with the increment in the amount of inputs in a gate,...
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What is the resulting Voltage Transfer characteristics of the modified CMOS-inverter circuit if NMOS and PMOS are interchanged?

What is the resulting Voltage Transfer characteristics of the modified CMOS-inverter circuit, if the positions of \$NMOS\$ and \$PMOS\$ are interchanged?
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“Power On Reset” on CD4026 IC

I know it's needed to connect a capacitor from Vdd to Vss on 40XX IC's. Is it also useful on a CD4026 counter to connect the reset pin to one end of the capacitor to reset the IC to zero when powered ...
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Is it possible to have a non-integer multiple of minimum length in MOSFET technology?

I need to design an OTA with 0.25 \$\mu m\$ CMOS technology. Can I choose to have a transistor with a channel length of 0.60 \$\mu m\$? I don't know if 0.25 is the resolution of our technology process ...
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How are Circuitboards with Multiple CMOS Chips Routed?

For my school side project i'm building a digital clock from 40xx series chips. I'm at 11 IC's now, taking up two regular sized breadboards. While I could simply solder this all onto solderable ...
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What does the dashed line between diodes in a CMOS protection network mean?

On the datasheet for CD4007 there are schematics for the input protection network: and the output protection network: On both, there are 2 diodes connected by a dashed line (D2 on the ...
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Minimum number of transistors to implement cmos logic of this function

I have designed the following circuit to implement cmos logic of : \$out=\overline{(a+b).\overline{c}+e.(\overline{f}+\overline{g})}\$ I’m looking for optimal circuit with minumum number of ...
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Solving CMOS logic structures

Can somebody please help me with understanding how to derive the equation from the red box from included picture (the other equations are trivial, it's just the right usage of De'Morgan's law)? I am ...
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691 views

pull-ups between logic gates

I'm trying to understand why, on this circuit bit, they used pull-ups resistors between logic ICs of the 74LS and CD4000 families. Specifically I'm talking about resistor array RM1 and R1. All the ICs ...
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Transistor sizing in CMOS circuit

Hello, I am currently studying for a digital circuit design course and had a question regarding circuit design here. The sample we were given was unfortunately incomplete and I am not told why this ...
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33 views

What is the pad-etching process in standard CMOS fabrication process

What is the pad etching process? Is it possible to etch to the bottom metal layers or vias in standard CMOS fabrication?
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52 views

What is the difference between these ring oscillator topologies? How can I simulate one without “noise voltage?”

If I understand correctly, with ring oscillator, it adds the negative feedback back to the loop to make a supposedly infinite gain. With the first topology (NMOS inverter) the negative feedback adds ...
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Is there such a thing as analog and digital compatible cmos or ccd sensors?

I'm way over my head with this one but I am trying to learn about cmos/ccd(preferred) sensors in order to build my own camera. Looking to get analog video from a sensor in a very small package size &...
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Why in Digital Design only Capacitive load?

Why in designing of CMOS logic we only consider the capacitive load of fanout? There is some wire resistance. So, why don't we consider resistive load?
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size pmos and Nmos in inverter for same rise and fall time

I want to design a minimum sized CMOS inverter with same rise/fall time. I am making use of 45nm technology(FREEPDK45). If i make the NMOS minimum width size, so 90nm. I don't know how to define the ...
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dynamic charge sharing between multiple gates

Based on this video: https://www.youtube.com/watch?v=CN4oIcAPIV4 hopefully it is legitimate I understand what is being done here. However, I don't understand it well enough for a more complex case ...
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Switched capacitor resistor

I have some basic doubts about switched capacitor resistors: With this circuit we get an equivalent resistance equal to (Reference: Wikipedia): Where f is the frequency of the clock signals that ...
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66 views

Three CMOS Inverters with feedback

I have been working on this circuit many days. I just would like to know how it works. In my opinion, the key is in the feedback in the 2º CMOS, but I do not really know how to manage it. All the ...
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55 views

What is the purpose /name of this CMOS gate configuration?

I have tried search via google images, but it's not good at recognizing line drawings
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Parameter extraction of MOSFET

I am doing the internship at Texas Instruments. I need to extract the parameters of MOSFET to study how all these parameters are getting affected by stress on silicon chips. If you guyz have good ...
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VOH is lower than VIH

I have a SoC connects to a DSP with SPI. They are all powered by 1.8V, so I didn't even compare SoC's Voh and DSP's Vih at the first time, they should working fine. However, yesterday my colleague ...
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98 views

Current Mirrors Design in IC

I was looking at a certain circuit in which there was the necessity of generating 3 DC current sources (10uA, 50uA, 250uA), starting from a given current source of 10uA. Let's consider firstly the ...
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State of CMOS Inverter

For the circuit below, we know that kn = kp = 1.2 mA/V^2 and that Vt (V threshold) is the same for the NMOS and the PMOS. Does this mean that both MOSFETs are always in the same state.
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What is the reasoning behind Barkhausen's criteria?

Especially why should loop gain be equal to 1, won't that give us infinite circuit gain?
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Are there combo gates XOR followed by AND? (4-bit identity comparator)

Is there no 4 bit identity comparator in TTL or CMOS? It could fit into a DIP-12 package as all it would have is 4 XOR gates for selectable invesion and 1 4-way AND gate. OUT := (A1 xor B1) and (A2 ...
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Can I use a simple fuse to protect a CMOS over current?

I'm designing an output with a MOSFET transistor to control loads such as relays, motors or incandescent lamps, similar to the outputs of a PLC. Obviously, there is no problem as long as the load ...
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What are the most common compounds used today in CMOS IC pn junctions?

Many many moons ago I was using germanium-based transistors but I know we have been able to exponentially speed up switching response times with newer doping compounds. I believe newer IC’s also ...
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What does worst-case gate capacitance mean in a MOS transistor?

I have searched the statement; MOS worst-case gate capacitance in various forms but no avail. Keep in mind I'm a student. The course I am taking has no reference material. With note slides with ...
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FIFO Clock Setup for CMOS Detector

When attempting to construct a miniature laser beam profiler with the Omnivision OV7740 CMOS detector and an Arduino Due, I am running into some problems with FIFO reading/writing. From the datasheet, ...
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Symmetric Inverter Sizing Based on load capacitance and propagation delay

I am doing Symmetric Inverter Sizing Based on load capacitance and propagation delay that is given. Also mobilities, threshold voltages are given. Symmetry ratio is process dependent based on ...
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Tricky problem regarding CMOS

My lecturer gave us the following problem today: "A CMOS gate (with inputs A, B, C) consists of a pull-up network with 0 or more PMOS transistors, and a pull-down network with 0 or more NMOS ...
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Short Channel MOSFET model

I was reading on a book (Thomas Lee, The Design of CMOS Radio Frequency Integrated Circuits) that in a short channel model, since the phenomenon of drift speed saturation is very relevant, it is a ...
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MOSFET as a Capacitor in IC

I was reading in a book that it is often possible to realize a certain capacitance in Integrated Circuits by exploiting the Gate Capacitance of a MOSFET. I read that the main disadvantage of this ...
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Finding node voltages in a MOSFET circuit

simulate this circuit – Schematic created using CircuitLab Considering Vdd=5v I want to calculate the node voltages at P,Q and R.
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Equivalent resistance in this mosfet circuit

simulate this circuit – Schematic created using CircuitLab I have 3 NMOS are connected as shown above. I need to calculate equivalent resistance as seen by the capacitor so that I am able to ...
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104 views

Analog Switch times for popless audio

If I am using a CMOS switch, how much do I have to slow down the switch time so that I don't experience a pop in my audio signal out of my amplifier and how would I accomplish that? The switch time ...
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What is the actual cmos technology node of China and Russia not licensing major process technology from outside?

There are a number of Russian fabs but from what I can see they are just using liscened technology ie Sitronics using STmicroelectronics at 90nm node or Angstrem-T using AMD see yet in the past there ...
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Using a CMOS 555 as a window comparator

I've been working on a small project inspired by this question that uses a CMOS 555 timer as a power button controller (short press to turn on, 3s hold to turn off), the goal being to design a ...
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Deriving PU / PD given a sketch of a PMOS

For the PMOS given below I can derive the function f, such that f inverted in its variables corresponds to the expression of PMOS(f) and f inverted equals NMOS(f). For this specific problem I have ...

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