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Questions tagged [cmos]

"Complementary Metal-Oxide Semiconductor" is a process which implements a combination of PMOS and NMOS transistors. Most current digital logic is implemented in CMOS. Its cost-effectiveness due to being so widespread means many other applications have become common as well, such as in analog design, image sensors, telecommunication, etc.

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Emitter-coupled logic operation

For the operation of emitter-coupled logic and sedra smith book, 1) Compared to CMOS, why ECL is the faster logic family given that it requires so many transistors to propagate to output Y (T5 ...
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Sine wave mos hf oscillator? [on hold]

I can't make a cross coupled HF oscillator with MOS transistors. I constructed a MOS triangle wave generator!
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leakage power with respect to Switching activity

Can anyone explain me relation of leakage current or power with respect to Switching activity(S.A). I'm assuming that with increase of S.A, the power dissipation of circuit increases in-turn ...
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52 views

CMOS sensor connector identification

This is cmos image sensor exmor rs for mobile by sony. android of so-01j has this cmos. I want to know specification or standard of this connector.
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72 views

P-MOSFET failures

simulate this circuit – Schematic created using CircuitLab P-Mosfet Datasheet The goal is that 5V (or logic high) appears on U3 when there is logic low on U4 and logic high on U2. That 0V (or ...
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1answer
28 views

STM32F407 CMOS or TTL or HC

I wonder which logic technology is STM32F407 MCU based on.. CMOS or TTL or HC or LVT etc? Although its mentioned in the datasheet that the GPIO's are CMOS and TTL compliant. I am concerned about this ...
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1answer
33 views

NRST pin of unpowered STLINK V2

I am using the STLINK from a Nucleo board in order to flash and debug a STM32F7 MCU on a custom board. Everything works fine except when STLINK is connected to my custom board AND unpowered. Indeed, ...
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Drain capacitance of CMOS inverter

How to find the total drain( NMOS+PMOS) capacitance of CMOS inverter in cadence virtuoso?
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CMOS Inverter output for a given transfer characteristics

I have tried solving the below CMOS problem with a given transfer characteristics but my answer is wrong. Answer should be 0.25. Could someone please point out where I went wrong ?
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74HC4060 lower frequency limit

I need to sequence some micropower (low-microamp range) logic at a once-per-several-minute rate, and am falling back on the good ol' 4060 as my timebase (plus a 138 and a 534 for the sequencing). I ...
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1answer
34 views

Possibility to change IC HCF4060BE to IC 74HC4060

I recently purchased a very old synthesizer that uses CI HCF4060BE and I want to know if it is the memso that CI 74HC4060. To help here is the CI datasheet HCF4060BE: LINK Here the dataset of the CI ...
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84 views

What is the point of 2 inverters in series? [duplicate]

In the datasheet for the Nexperia HEF4543B, in the logic diagram, there are 2 inverters in series: What is the point of these inverters in series?
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How to calculate propogation delay from an I-V curve of a PMOS transistor (CMOS inverter circuit)

How does one find the total propagation delay using the formula $$T_{pHL} = C\frac{V_{swing}/2}{current_{average}}$$ from the chart below. How is the \$current_{average}\$ derived?
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1answer
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Help Identifying a CMOS optical mouse sensor?

I'm working to repurpose the trackball assembly of a Logitech Trackman wired mouse for use in an experimental rig. I assumed that Logitech would use Avago's ADNS series of optical flow sensors, but it ...
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MOSFET construction

I've just read an application note and I was confused about this sentence: "Engineers often think of a MOSFET as a single power transistor, but it is a collection of thousands of tiny power FET cells ...
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1answer
38 views

Switching threshold of CMOS inverter [closed]

How to find the switching threshold of CMOS inverter from it's transfer characteristics in Cadence Virtuoso?
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47 views

MOSFET treshold voltage

Does anyone know how MOS treshold voltage varies if the physical distance between source and drain decreases ?
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105 views

Shot or thermal noise of a MOS transistor

I'm trying to compare the shot and thermal noise contributions in a MOS transistor. In the literature, the above-threshold MOS transistor has only thermal noise, which is found by integrating the ...
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46 views

zero AC gain of CMOS inverter

Why is the following AC analysis of CMOS inverter resulted in zero AC gain (vout/vin) ?
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36 views

Current to Voltage Converter in CMOS [closed]

If I want to use a 2-stage opamp for the current to voltage converter application, How should I check for the stability of the circuit? Will it need any kind of stability correction? An uncompensated ...
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1answer
50 views

Why is it not sensible to connect many (MOS) transistors in series?

For example a NAND-gate with 3 inputs has 3 NMOS in series and 3 PMOS in parallel. But why aren't there cmos gates with e.g. 10 inputs?
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dc sweep convergence issue for cmos inverter

I am having some convergence issue with DC sweep for a CMOS inverter. To duplicate the exact issue, see the following log as well as the attached netlist files, together with modelcard.nmos and ...
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How does this circuit with inverters work?

What this does this circuit do? I suspect it is an amplifier, but don't know how it amplifies. For example Inv 5 and Inv 6 are connected in parallel with reverse sides but there is a wire between ...
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2answers
38 views

CMOS Inverter circuit

I want to design CMOS Inverter which gives: 0 volt input --> 5 V output Any positive input voltage above threshold voltage --> 0 V output. On simulating, it is giving me alternatively +2.5v and -2....
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Measurement of Cmos Parasitic capacitors

i've had a question which asks if we assume that capacitance of capacitors with w/l of 1u/0.5 are then what are capacitance of capacitors (with the actual w/l) now i know cgs in saturation for ...
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1answer
48 views

Common Mode and differential Mode gain of this Cmos diff Amp inverter

This is one of questions our prof gave to students in recent years and im preparing myself for this exam. What is Common Mode and differential Mode gain of this Cmos diff Amp inverter? i understand ...
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35 views

Understanding CMOS Circuit Behaviour with Resistive Loads using Thevenin theorem

I have been reading the Digital Design: Principles and Practices 3rd Edition as a hobby. Unfortunately, I am stuck at page 103 of Section 3.5.2: Circuit Behavior with Resistive Loads. In Figure 3-27: ...
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IC layouts - Transistors (Body)

I'm trying to get into IC layouts... Why do I see some IC layouts with or without the body terminal on the transistors. Do MOSFet transistors need a body terminal in an integrated circuit? Or should ...
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3answers
87 views

Latch-Up in CMOS-Devices

I recently read something about the latch-up effect in CMOS-Structures but I don't understand why are MOSFETs affected by this effect. I understand that high currents through the source-drain path ...
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3answers
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Measuring transconductance of any circuit

May I know if the following transconductance measurement test circuit is correct because I am getting quite small Gm values ? I suspect that I need to use some derivative function because changing ...
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2answers
75 views

Force the state of floating digital input to particular level

Given: a microcontroller in QFP package. A pin is configured as digital input, no pullups/pulldowns. The physical pin is not connected to anything else, besides the pad on PCB. Is there a way to ...
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1answer
31 views

Are there ways/technologies to use High negative voltages in flash memories?

I am using an FGMOSFET with tunneling gate and control gate as an analog memory for simulation in SPICE. I use -25V to inject electrons into the floating gate and 25V to remove electrons. Everything ...
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2answers
62 views

Wiring of body terminal in a network of MOSFET switches

I am trying to design a set of switches in a cmos design. The switches are supposed to control a number of capacitors and I want to implement them as single NMOS or PMOS transistors. Based on my ...
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2answers
1k views

Why do we use a CMOS for inverting a circuit when the PMOS already achieves that?

The output in a PMOS is as follows: I/P O/P 0 1 1 0 Why can't I just use this instead of using a CMOS for inverting logic? (Please ...
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56 views

Operational amplifier for higher slew rate

what are the possible ways to improve slew rate of an operational amplifier in CMOS technology?
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121 views

Resetting CD4017 Counter when power source is OFF

I found the circuit below online and I have two questions about the reset switch. Does it help to click the reset button when power is OFF? I mean, does it clears the memory of the CD4017 chip when ...
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1answer
51 views

74AS TTL to CMOS pull up resistor and maximum speed (or lowest delay)

Hello I have to pilot a CMOS input 5V chip device with a 7474 flip flop with the lowest possible delay to minimize clock jitter. Signal is about 11.3 Mhz I have two options: 1) 74HC74 (CMOS ...
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1answer
110 views

Implement an 8 input AND gate with least delay

I'm trying to implement an 8-input AND gate using CMOS technology with the best number of stages and least delay (I have attached the schematic in the link given). Using logical effort I have so far ...
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2answers
92 views

Weird Current Mirror

I just encountered this circuit and I'm a bit confused by it I see that it's an NMOS current mirror. At first I thought it's a cascode current mirror due to M3 on the right but it isn't. I have two ...
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1answer
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Why does my AND cmos gate have less dissipation than my NAND gate?

I've just started taking a course in VLSI and from the little I know, this result seems a bit off. Below you can see the layout for the AND and NAND gate I designed : They both seem to be working ...
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Do cascoded MOSFETs need to be in their own wells in order to properly connect bulk to source?

I am learning to design CMOS layouts. When creating the layout for something like a cascoded current mirror, are individual wells needed to properly connect the bulk to source? For example, for the ...
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What is the response curve of a CMOS sensor cell to the amount of light?

Using my Nikon D5100, shooting RAW pictures and using Darktable to disable absolutely all contrast curves, white balancing, sharpening and even the debayering, I've measured the average value of the ...
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1answer
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CMOS implementation of D flip-flop

I am trying to implement edge triggered flip-flop using CMOS logic. Google search provides following diagram on wikipedia: Upon simulating this using tanner, I find out that output resembles positive ...
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1answer
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CMOS Inverter-based question from Sedra&Smith, Microelectronic Circuits

Exercise 4.47 from Microelectronic Circuits, 6th edition, Sedra & Smith. I am unable to analyze the following question. Can anyone help me solve it? I only know that the circuit won't remain ...
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1answer
77 views

Increased current consumption of micro-power devices

I've been working with microwatt and nanowatt power consumption devices for a while and I've mentioned that sometimes, due to unknown reason, current consumption increases in order of magnitude. ...
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1answer
65 views

Replace a relay with an analog switch

I'm trying to replace a relay with a SPDT cmos analog switch MAX4678 for switching a sine wave, The switch is powered with dual power supply +5/-5 and +5 to its V_logic pin. This is what i got in ...
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240 views

What is the difference between CMOS and Pass-Transistor Logic?

My friend and I are taking our first digital systems designs course this semester. Our professor has introduced to us two different type of circuit designs; CMOS and Pass-Transistor Logic. The ...
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1answer
50 views

CMOS Technology [closed]

Why is dynamic CMOS faster than static CMOS? One reason is that the load capacitance is small. I can not understand how they are related to the speed of CMOS. Another reason is the lower number of ...
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1answer
98 views

Output voltage in MOS cascode amplifier

I'll give a background to my main question:- In a simple NMOS as shown, while constructing the small signal model of the MOSFET, when there is no resistance between Vdd and drain, NMOS is modeled ...
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Jellybean Radio Button logic Chip

Below is an LTSpice simulation of a 'radio button' circuilt. Ignore the bottom button, I am working on a 'reset' mechanism to unlatch any of the other buttons. The idea is that the button you push, ...