Questions tagged [cmos]

"Complementary Metal-Oxide Semiconductor" is a process which implements a combination of PMOS and NMOS transistors. Most current digital logic is implemented in CMOS. Its cost-effectiveness due to being so widespread means many other applications have become common as well, such as in analog design, image sensors, telecommunication, etc.

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Why we have positive voltages for ground/VSS supply?

I have seen circuit designs that use multiple power supplies/grounds, and some of the VSS ground supplies are non-zero, for example: 0.3V. I am curious to know why this is useful. Where is it used? ...
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Noise sensitivity to output impedances [duplicate]

A lower value of output impedance in a CMOS inverter leads to less sensitivity to noise of the inverter. Can someone elaborate regarding this? The quote comes from Digital Integrated Circuits by ...
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"Tiny " XOR gate simulation not working

I am trying to implement this below XNOR circuit in Cadence. I am using GPDK 180nm and 1.8 V power supply. Here is the schematic in Cadence. Doing a DC simulation, I am not getting proper voltages at ...
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How to implement this simple truth table with CMOS logic?

In my project I intend to use an USB-audio switch. It has a SELECT input pin which must be high when an USB headset is connected to the USBC port, and low in any other case. When a USB headset is ...
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Transmitting an RS232 Signal over Wireless/RF. Can this be achieved? [closed]

I have an idea I am trying to implement and I want to know if this is possible and feasible. I have a Barcode Scanner device that gets connected to a PC with a DB9 COM port. Using this connection and ...
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Miller effect in MOSFET

I have few question related to Miller effect in cmos. What does rate of change of Vgd (across Cgd) or Vd (drain point) depend on, when the transistor turns on? When transistor is on, it will get into ...
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Are there any ways to increasing the gain and ICMRs to this opamp?

Here's the netlist of this CMOS opamp schematics. ...
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Push-pull output stage doesn't reach input voltage

I tried to simulate a push-pull output stage in this configuration: Here with the closed switch: As you can see, the output voltage is very low. I expected 3.3 V and 250 mA at the output. Shouldn't ...
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Using transistors to boost MOSFET gate voltage alternatives [closed]

I'm working with a micro controller based on CMOS logic. So I want to drive a load that is connected to the P-MOSFET low side. To make sure that the gate is fully saturated, I want to boost the 5 V to ...
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Problem on biasing of the differential folded cascode with ideal and non-ideal CMFB

For this circuit, a PMOS input stage folded cascode amplifier as a gain booster, I have two questions. The PMOSs (Mppp1 to Mppp4) in the cascode banches are in strong-inversion saturation while the ...
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Interfacing LM3914 to CMOS logic circuitry

I built the ubiquitous battery voltage monitor using the equally ubuiqutous LM3914. It monitors a 12V battery and controls a charger. The datasheet mentions the IC can interface with TTL or CMOS logic,...
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I want to Implement this active inductor design in my circuit

I'm trying to use the active inductor in here instead of the inductor in my class e power amplifier, however I'm having difficulties in getting the required values for the parameters in here Cds, Cgs, ...
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Can someone explain how I can avoid voltage spikes in this graph?

I’m trying to implement this boolean function using CMOS transmission gate in LTspice. F = AB + A'C' + AB'C I've used two symbols in my project: Transmission gate symbol schematic: 180nm CMOS ...
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Could we use holes in an NMOS?

In an NMOS we have a p-substrate, and we use a positive voltage to attract negative charge "to the top". But could we have used negative charge to attract holes instead and gotten a "...
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Why is gate fanout calculated like that for general gate?

In the given example I am currently struggling to understand why the fanout of each gate is equal to the ratio of the size of this gate to the previous gate. In a simple chain of inverters, the fan ...
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Cascode: Which device goes into triode region first?

In the above cascode network, which device goes into triode region first, if the supply gradually decreases? Framing the question other way round, if the supply gradually increases from 0V, which ...
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How can you block the parasitic body diode in digital CMOS I/O IC design?

I've been screwing around with IBIS models lately and came across something that left me scratching my head. First, the generic model structure for the semiconductor portions of an IBIS I/O looks ...
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How does the CMOS Schmitt trigger work

I have some questions on how the schmitt trigger works. Assuming we start with low Vin hence Vout is high. It means that M1 is ON thus the source of M2 is conducting Vdd hence M2 is On as well. ...
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What is the maximum number of inputs to a logic gate that is being used in computing hardware these days?

I was referring to this question, but I had a confusion due to the concept of programmable logic devices. Image from UW page 7. Here the OR section can have up to 8 inputs to it. I'm confused about ...
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Figure of Merit for sizing P-MOS and N-MOS in Inverter circuit

I am trying to design a basic circuit block of inverter (Analog circuit) in Cadence Virtuoso schematic in 22nm technology. It will be used for non-overlapping clock generator. I need to size the P-MOS ...
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Setting multi-fingers in MOSFET in series configuration in Cadence Virtuoso schematic

I am trying to figure out to set multi-fingers (nf = 3) for MOSFET (both P-MOS and N-MOS.) I know I can increase the length directly. As connecting MOSFETs in series increases length, can I somehow ...
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Why does switching cause power dissipation?

I know that switching logic values causes power dissipation but I could never understand why. Is it because transistors need to be turned on each time we want to charge/pull up a node and discharge/...
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Purpose of field implant in semiconductor manufacturing

I recently joined the semiconductor manufacturing industry. In one of the process flows, I see a stage that has extra boron implantation step (called the field implant) in the P-WELL region. I've ...
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1 answer
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Getting SPDT behavior (with zero quiescent current) from an SPST switch

If you've got an SPDT switch, it's pretty straightforward to use it as a front panel input to some CMOS logic. Even with simple debouncing (no hysteresis, which is acceptable for my purposes), it ...
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Using an SN74HC595 as a single-wire state machine

I have an SN74HC595 shift register, and I want to use it to replace a microcontroller to save space and cost, since a microcontroller isn't really needed in my application. The application is a system ...
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Is it possible to design dynamic logic using pre-discharge NMOS transistor and evaluation done using PMOS?

Traditionally dynamic logic has a clock input which determines whether the device will work in pre-charge or evaluation phase. PMOS is used as the pre-charge transistor and evaluation is done using ...
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NMOS Cascode Logic

I have following problem and I ask you ,if possible, any help to resolve it. Size the following circuit so that it achieves a 100 ps delay (50-50) using 0.25 μm devices, while driving a 100 fF load ...
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VOH vs CMOS VOH

I'm new to circuit design. I'm trying to design a clock for a circuit containing 8 SPI to CAN devices. However, I'm not sure if it's possible with a single clock (perhaps this reference). As I'm not ...
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Test-charge injection circuit for CSA(Charge Sensitive Amplifier) in CMOS IC

I need to inject test-charge (electrons) into a CSA. Is there any specific name for this kind of circuit? Is there any other alternative for the circuit below? This is one of the example. This circuit ...
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2 votes
4 answers
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How do processor transistor counts keep increasing, without geometric scaling?

Reading into the history of the semiconductor industry and Moore's Law, and looking at the ITRS/IRDS documents, I understand that scaling down and modern node names (7nm, 5nm etc) are now "...
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Analyzing circuit that cascades a pseudo NMOS inverter with a CMOS inverter

I have simulated this circuit in LTSPICE and it seems that the output is only High for A = 0 and B = 0. In other words, the circuit behaves similar to a NOR gate. However, I'm having trouble analyzing ...
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CD4069 toggle switch

How to connect the trigger out instead of the switch? Like a toggle switch. The first trigger out activates the relay and remains ON infinity, the second trigger out deactivates the relay and remains ...
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Diode I-V characteristics

I am studying device design, starting from diodes. I am using the VisualTCAD simulator which allows us to simulate device fabrication and simulation. The diode specifications are as follows: n-doping:...
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Will connecting unused CMOS outputs to VCC damage the chip?

I am using a 74HC154 4x16 decoder in a design I'm working on and I'm not using the last four outputs. During PCB routing it would be very convenient if I could tie these unused outputs to the VCC ...
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8 votes
1 answer
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How Does an Adjustable Transistor Size CMOS Driver Work?

Background The source-terminated reflected wave switching scheme is a familiar one. One just needs to add a source-series terminator, which added together with the driver's output impedance equals the ...
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Transmission gate conducting in OFF state

Here is a part of my circuit that I am trying to simulate in cadence virtuoso. It has two transmission gates, the one in path of charging the capacitor is on and other one is OFF. Supply voltage is ...
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Two CMOS switches connected in series

I have seen some circuits like the one below; why do they use two switches in series instead of one switch? Aren't two switches in series equivalent to doubling the length of one? I'm sorry that I ...
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6T SRAM cell write operation not working as expected in virtuoso

I am trying to play around a 6T SRAM cell by simulating it's write operation in Cadence Virtuoso. The NMOS and PMOS specifications are 120/45 nm and 310/45 nm. The Bit select is kept at constant 1 and ...
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Finding the gain expression for this CMOS operational transconductance amplifier

So here's the circuit: I think M2 is a common source amplifier and M4 a common gate amplifier, so they form a cascode amplifier where the gain is given by : Av = -gm2 * r0, r0 is the impedance at the ...
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The unusable state of S-R Latch simulation in LTSpice

I created an S-R Latch in spice using MOS transistors (180nm) and gave noth S and R inputs as 1 (knowing that this state is unusable as both Q and Qbar will be metastable). But I was expecting ...
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Why is this circuit a two-stage amplifier?

I am studying the following circuit and my professor calls it a two-stage amplifier. However I don't understand why as I just see a NMOS differential pair: MN0 and MN1 a PMOS active load (current ...
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2 votes
2 answers
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SPDIF to CMOS logic

I am trying to get around my head on the three questions below. Is SPDIF protocol is really driving 0.5 V pk-pk without having any DC offset? If yes, HDMI1.4 mentions ARC protocol which is adhered ...
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1 answer
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Plotting MOS resistances in transmission gates in spice

I am trying to plot the resistance of MOS transistors in transmission gates, as a function of output voltage in ltSpice, as shown in this figure from Jan.M.Rabey: I have a circuit with same ...
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Op Amp design - open loop gain 73dB, closed loop gain -200dB

This is my first time designing an op amp, using 180nm in Cadence. Two stage design, 1st stage is NMOS differential pair with PMOS current mirror load, second stage is PMOS CS with Miller capacitor. ...
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Variation in Tphl of MOS nand gate due to input patterns

I was studying the variation of propagation delays in CMOS NAND gate from Jan.M.Rabey Digital IC Design book. It has this table given for Tplh and Tphl for different input patterns applied at inputs A ...
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MOSFET I/V characteristics. How does this mosfet conduct current?

I am currently studying the basics of CMOS design and came across the following problem in Razavi's textbook with respect to a NMOS transistor : The question is simple: Let \$V_{SB}\$ = 0 (source-...
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CMOS (analog) switch output has a few hundred mV offset when output is disabled

I'm using an TS12A4514 CMOS switch in order to isolate some digital lines from one device to another. Power rails are 5V & 0V (GND). While the switch is enabled (enable input is 5V), input ...
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How do the dimensions of a MOS tranistor affect the gain of a CMOS inverter?

I am simulating the voltage transfer characteristic curve of a CMOS inverter, while varying the dimensions of L and W of MOS. Comparing the results for two scenarios, I have the following results: ...
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How to configure / construct a CMOS sensor to act on changing signals only?

You all probably know how a CMOS sensor works, at least in general. In short, it consists of a lot of pixels (photodiode plus amplifier and so on), and each pixel is read out individually (different ...
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How to draw a stick diagram from this circuit

I'm new to VLSI. I am currently working on a project to make a full 1-bit subtractor. I translated the Bout (carry) logic into Bout = A'.Bin + A'.B + B.Bin. Below is my Proteus simulation. I know the ...
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