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Questions tagged [cmos]

"Complementary Metal-Oxide Semiconductor" is a process which implements a combination of PMOS and NMOS transistors. Most current digital logic is implemented in CMOS. Its cost-effectiveness due to being so widespread means many other applications have become common as well, such as in analog design,...

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Exercise about CMOS sizing

I have to solve the following exercise: Given the function Y = (A'+C')(B'+D')(c'+DE) draw the relative CMOS circuit,then establish the combinations of inputs that produce the worst case HL and LH ...
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Force the state of floating digital input to particular level

Given: a microcontroller in QFP package. A pin is configured as digital input, no pullups/pulldowns. The physical pin is not connected to anything else, besides the pad on PCB. Is there a way to ...
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26 views

Are there ways/technologies to use High negative voltages in flash memories?

I am using an FGMOSFET with tunneling gate and control gate as an analog memory for simulation in SPICE. I use -25V to inject electrons into the floating gate and 25V to remove electrons. Everything ...
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50 views

Wiring of body terminal in a network of MOSFET switches

I am trying to design a set of switches in a cmos design. The switches are supposed to control a number of capacitors and I want to implement them as single NMOS or PMOS transistors. Based on my ...
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Why do we use a CMOS for inverting a circuit when the PMOS already achieves that?

The output in a PMOS is as follows: I/P O/P 0 1 1 0 Why can't I just use this instead of using a CMOS for inverting logic? (Please ...
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39 views

Operational amplifier for higher slew rate

what are the possible ways to improve slew rate of an operational amplifier in CMOS technology?
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3answers
75 views

Resetting CD4017 Counter when power source is OFF

I found the circuit below online and I have two questions about the reset switch. Does it help to click the reset button when power is OFF? I mean, does it clears the memory of the CD4017 chip when ...
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1answer
34 views

74AS TTL to CMOS pull up resistor and maximum speed (or lowest delay)

Hello I have to pilot a CMOS input 5V chip device with a 7474 flip flop with the lowest possible delay to minimize clock jitter. Signal is about 11.3 Mhz I have two options: 1) 74HC74 (CMOS ...
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103 views

Implement an 8 input AND gate with least delay

I'm trying to implement an 8-input AND gate using CMOS technology with the best number of stages and least delay (I have attached the schematic in the link given). Using logical effort I have so far ...
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2answers
84 views

Weird Current Mirror

I just encountered this circuit and I'm a bit confused by it I see that it's an NMOS current mirror. At first I thought it's a cascode current mirror due to M3 on the right but it isn't. I have two ...
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1answer
84 views

Why does my AND cmos gate have less dissipation than my NAND gate?

I've just started taking a course in VLSI and from the little I know, this result seems a bit off. Below you can see the layout for the AND and NAND gate I designed : They both seem to be working ...
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38 views

Do cascoded MOSFETs need to be in their own wells in order to properly connect bulk to source?

I am learning to design CMOS layouts. When creating the layout for something like a cascoded current mirror, are individual wells needed to properly connect the bulk to source? For example, for the ...
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60 views

What is the response curve of a CMOS sensor cell to the amount of light?

Using my Nikon D5100, shooting RAW pictures and using Darktable to disable absolutely all contrast curves, white balancing, sharpening and even the debayering, I've measured the average value of the ...
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1answer
483 views

CMOS implementation of D flip-flop

I am trying to implement edge triggered flip-flop using CMOS logic. Google search provides following diagram on wikipedia: Upon simulating this using tanner, I find out that output resembles positive ...
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54 views

CMOS OTA Open Loop Gain

I am trying to design a fully differential transconductor. However, when I try to check the Open Loop DC gain, I get a negative dB value, which tells me that my transconductor is attenuating instead ...
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58 views

CMOS Inverter-based question from Sedra&Smith, Microelectronic Circuits

Exercise 4.47 from Microelectronic Circuits, 6th edition, Sedra & Smith. I am unable to analyze the following question. Can anyone help me solve it? I only know that the circuit won't remain ...
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74 views

Increased current consumption of micro-power devices

I've been working with microwatt and nanowatt power consumption devices for a while and I've mentioned that sometimes, due to unknown reason, current consumption increases in order of magnitude. ...
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1answer
55 views

Replace a relay with an analog switch

I'm trying to replace a relay with a SPDT cmos analog switch MAX4678 for switching a sine wave, The switch is powered with dual power supply +5/-5 and +5 to its V_logic pin. This is what i got in ...
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139 views

What is the difference between CMOS and Pass-Transistor Logic?

My friend and I are taking our first digital systems designs course this semester. Our professor has introduced to us two different type of circuit designs; CMOS and Pass-Transistor Logic. The ...
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cmos inverter tanner eda

I am trying to model a simple cmos inverter but i am not getting the desired output.I am including the w-edit and t-edit files.
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1answer
48 views

CMOS Technology [closed]

Why is dynamic CMOS faster than static CMOS? One reason is that the load capacitance is small. I can not understand how they are related to the speed of CMOS. Another reason is the lower number of ...
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1answer
69 views

Output voltage in MOS cascode amplifier

I'll give a background to my main question:- In a simple NMOS as shown, while constructing the small signal model of the MOSFET, when there is no resistance between Vdd and drain, NMOS is modeled ...
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49 views

Jellybean Radio Button logic Chip

Below is an LTSpice simulation of a 'radio button' circuilt. Ignore the bottom button, I am working on a 'reset' mechanism to unlatch any of the other buttons. The idea is that the button you push, ...
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56 views

What is the lowest voltage a cmos transistor can operate?

I am trying to do some hspice simulation with some free 45nm CMOS transistor models. I found that an inverter can simulate properly with voltage as low as 0.25V, though it's slower. My question is, ...
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129 views

How to amplify RF signal to high enough level for a CMOS downconverting mixer?

I've been reading original academic papers on mixers and now a RF textbook and I have been unable to understand a very basic thing, which is how do I get a RF signal, say -65 dBm, at a high enough ...
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32 views

Finding drain voltage for a resistor loaded CMOS inverter with 0V at input terminal

Introduction: The following example is from the textbook Sedra/Smith Microelectronic Circuits. It is stated in the solution to this example that since both \$Q_n\$ and \$Q_p\$ are both matched and \$|...
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A circuit with Schmitt trigger and inverter.

During the exam I was asked to explain a schematics. The question is to show the outputs (draw) from point B,C,D,E and what will be the time when E switches. The input voltage is being increased from ...
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1answer
66 views

Replacing CMOS SRAM with equivalent TTL SRAM

I want to replace an IS62WV51216BLL-55 (http://www.issi.com/WW/pdf/62WV51216ALL.pdf) with an AS7C4098A-12 (https://au.mouser.com/datasheet/2/12/as7c4098a_v1.2-1288279.pdf), as the latter has much ...
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1answer
43 views

MCU sinking current from a higher voltage source

In previous designs, I have used an MCU digital output to drive the lower side of a resistor ladder to the supply voltage, to prevent power consumption when the ladder is not being sampled: Schematic ...
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2answers
1k views

How to manufacture chip on board?

I am a developer of a cheap product and i have no experience in mass production. Device is fully functional and represents a single sided PCB, a microcontroller, a bunch of diodes and a few passive ...
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1answer
67 views

5V to 3.3V Converter

I have a problem in connecting Raspberry PI to an MCP3202. I am using MCP3202 at 5V and knowing that raspberry pi works on 3.3v. I have found a solution to convert from 3.3V to 5V using 74HCT244. And ...
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2answers
51 views

Maximize output signal swing in digital circuit design

Please help me understand the following paragraph in chapter CMOS Digital Logic Circuit from book"Sedra/Smith micro electronics circuit 6e". An ideal VTC is one that maximizes the OUTPUT signal ...
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41 views

How can I reduce loading effect in dc common drain source follower?

I want to make a dc voltage buffer using an nmos source follower. I found that by making Rs as large as possible or even open, Vs= Vgs-Vth. I verified it using multisim. The problem is it suffers from ...
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5k views

Why isn't the BIOS' ROM chip made using CMOS technology?

After reading a computer hardware course on BIOS/CMOS, I'm still unable to determine the reason why the BIOS' ROM chip isn't built using CMOS technology, and why it is connected to a separate chip ...
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244 views

measurement of output impedance of a CMOS inverter

I am measuring output impedance of CMOS inverter using ngspice. No matter how I measure the output impedance, the result can never come any close to the following theoretical calculation if I reduce ...
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1answer
35 views

Adiabatic CMOS circuits in low power design

There are several techniques to reduce dynamic power consumption in low power design, but I could not understand the basic concepts of Adiabatic circuits and how will it reduce the dynamic power ...
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92 views

CMOS NAND Image

I was looking at this image which shows a CMOS NAND standard cell. However, how can I see this depicts a NAND? A CMOS NAND has parallel PMOS and serial NMOS transistors but somehow I can't see this ...
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Why is the input voltage of transistors in the CMOS circuit set to Vdd when calculating the equivalent resistance?

When deriving the equivalent resistance formula of NMOS inverter the graph which is used in derivation is as shown: $$R_{eq} = \frac{1}{-V_{dd}/2} \int_{V_{dd}}^{V_{dd}/2} \frac{V}{I_{Dsat}(1+\...
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56 views

Monostable multivibrator problem

As you see in the picture above, diode voltage drop is 0V, and the monostable multivibrator is made in CMOS technology with protection diodes. I have problem finding the output of this circuit in some ...
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64 views

Identifying the logic function of this specific MOS layout

I am not sure about the functionality of the following MOS layout. I came up with the logic function AND(NOT(AB),C). Can anyone confirm or correct me ? PS: The steps I made are attached
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How to select the nets from schematic in Test bench ADE cadence?

I'm performing my pre-layout simulation in cadence. I can select the output nets from test bench because I loaded the ADE environment for test bench but I also want to select the nets schematic as ...
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123 views

D FLIP FLOP Cadence

Basically I am designing D flip flop. While doing my pre-layout simulations, not getting the output Q for the inputs. See the attached attachments. But when I tried to take the output from CLKPULSE, ...
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2answers
3k views

Why is there no rolling shutter when using a mechanical shutter?

So I know it might not be the best place to ask this question, but maybe some of you are familiar with the mechanics of digital mirrorless cameras and the technology of CMOS sensors. I don't quite ...
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1answer
98 views

What is comparison of readout times of global and rolling shutter cameras? [closed]

Rolling shutter will take more time because of sequential readout and global will take less time.But what are the exact values of image readout time?
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47 views

PSPICE simulation

I have a PSPICE file that contains approximately 200+ transistors. Naturally, simulating the whole circuit everytime I make a change takes a while. Is there anyway to run a simulation measuring only ...
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1answer
30 views

Bump Circuit in PSPICE

I am designing a bump circuit in PSPICE to determine if two voltages are equal. The schematic is shown in the figure below. The parameters are set in the subthreshold region, with a VDD of 2 volts. ...
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1answer
143 views

Is a TXB0108 apt for level-shifting in SPI programming?

I plan to use a TXB0108 to level-shift between the cheap CH341A programmer voltage and the Winbond W25Q64FW from 3.3V to 1.8V On the silicon I can read: ...
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1answer
129 views

Subthreshold Transconductance Amplifier

As part of a broader project, I am designing IC circuit using CMOS to one of the first steps I'm working on is the filtering a series of pulses with of the noise. The actual pulses are around 1 kHz so ...
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1answer
96 views

How could I put an Enable pin on a standard two-stage CMOS op-amp?

I need to design an LDO regulator that only sources supply voltage and current to the load whenever it receives a logic-1 signal. Since the main element used in the LDO regulator is a differential ...
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56 views

Dynamic power dissipation of a Cmos inverter with relation to it's geometry

I know that the dynamic power dissipation of a CMOS inverter is defined by the equation: Pd = (Cl)(Vdd^2)(fb). My teacher challenged us to find ways to reduce power dissipation besides the obvious ...