Questions tagged [cmos]
"Complementary Metal-Oxide Semiconductor" is a process which implements a combination of PMOS and NMOS transistors. Most current digital logic is implemented in CMOS. Its cost-effectiveness due to being so widespread means many other applications have become common as well, such as in analog design, image sensors, telecommunication, etc.
1,029
questions
0
votes
1
answer
25
views
Sizing an CMOS StrongArm Latch comparator on Virtuoso from scratch
I'm currently designing an CMOS comparator and I'm a little bit lost regarding sizing the transistors. I was taught to use the Id formula, but for that to work I need to have muCox, and I do not. Can'...
- 1
1
vote
3
answers
96
views
Shouldn't the differential pair gain be \$\frac{V_X - V_Y}{V_{in1}-V_{in2}} = -g_m R_D/2\$?
This is a snipet from the book Design of Analog CMOS Integrated Circuits (page 112).
This is analysis of differential pair.
For \$g_{m1} = g_{m2} = g_m\$, reduces to
$$\begin{equation}
(V_X − V_Y ) = −...
- 410
0
votes
1
answer
55
views
How can this circuit remove \$R_{D2}\$ in small signal analysis for this nmos?
The following is differential pair small signal analysis from the book Design of Analog CMOS Integrated Circuits.
Let us set \$V_{in2}\$ to zero and find the effect of Vin1 at X and Y [Fig. 4.17(a)]. ...
- 410
1
vote
1
answer
86
views
Transfer function for CMOS opamp design
I am currently working on my bachelor thesis about readout interface for resistive gas sensors. In the whole schematic a use an opamp which I am currently trying to design. At first, I want to have ...
- 61
1
vote
1
answer
112
views
How is CMOS impedance calculated?
The following is a snippet from the book Design of Analog CMOS Integrated Circuits
Here is what I thought.
$$V_1 = 0-V_x $$
$$V_{bs1} = 0 - V_{s1}$$
$$V_{s1} = I_x r_{o1}$$
According to KCL.
$$ g_{...
- 410
0
votes
0
answers
22
views
Horizontal Blanking Interval (Idling Time) optimization
I have questions regarding the time slot in-between two frames of video stream, i.e. Horizontal Blanking Interval (let's say HBI in the following), seen as Idling Time sometimes.
Considering a CMOS ...
0
votes
0
answers
47
views
How to find maximum output current of a CMOS inverter?
I'm having trouble finding the calculations to find the maximum current at the output of the inverter.
I managed to find all types of different voltages that are found in the CMOS inverter at each ...
- 363
0
votes
1
answer
51
views
How does Vout (DC) track VX (DC)?
I examined the both Vx and Vout with the Aspect Ratio in all transistors. I found that both are equal and I don't understand how this happens.
Could someone please explain with details, because I want ...
- 21
1
vote
1
answer
57
views
Is this transistor schematic of a CMOS layout correct? [closed]
Working through some problem sets on CMOS circuits right now, is the following circuit correct?
It seems eerily close to a 3 input NAND circuit, except that the top three transistors I’ve drawn are ...
1
vote
1
answer
118
views
12 transistor XOR CMOS gate
I have come across this circuit for an XOR gate (see below) using 12 transistors in CMOS technology. I am having trouble understanding the circuit, mainly in identifying the logic gates.
I know that ...
- 1,403
1
vote
2
answers
176
views
Capacitance of MOS capacitor vs orientation
Edit Both FETs are the same PFET with the same dimensions.
I wanted to check the capacitance of a MOS capacitor vs its orientation. I expected the gate low orientation to have greater capacitance ...
- 1,234
1
vote
0
answers
36
views
CMOS Inverter Transistor Sizing Wording
"Assume that both the gate lengths as well as W_n for the 180 nm technology in the table can have dimensions down to 180 nm."
I'm simply wondering here what they're referring to with the &...
- 11
2
votes
1
answer
57
views
The logic gate design of a positive edge triggered, master slave d flip flop with asynchronous inputs preset and clear?
I'm a computer science student who's trying to get a better understanding of the d flip-flop. My project assignment is to make a CMOS design of a positive edged d flip-flop using ff master slave and ...
0
votes
2
answers
43
views
How does moving an input signal node closer to the output node reduce parasitic capacitance
So I have been studying about logic gates designed using the CMOS family and in my professors notes it says "Move NMOSFET-B closer to output node, without changing the functionality , to reduce ...
0
votes
1
answer
105
views
Simulating cmos comparator on cadence virtuoso
I am trying to simulate the following cmos comparator circuit using cadence virtuoso spectre.
Here's my schematic on cadence:
I am using the following test bench to simulate the circuit with Ibias = ...
- 3
2
votes
3
answers
141
views
How does a CMOS image sensor manage to read and record all the pixel values? Any good ideas for doing it for discrete components?
As background info, I'm an electrical engineer (power IC design) and photographer, and I'm designing my own camera (32x40 discrete pixels made of SMD photodiodes, will be about the size of a 4"x5&...
- 135
0
votes
2
answers
107
views
What is the purpose of compensation resistor in the CMOS Two stage op-amp circuit shown here? And it effect on Unity Gain?
I wonder why there is a compensation resistor in some CMOS Op-Amp circuit shown here. What is the purpose of this? I tried to vary it and this is what I got for unity gain of each value. Based on many ...
0
votes
1
answer
66
views
Minimum compensation capacitance for 45 degree phase margin in two-stage CMOS OTA
I'm working through a solved example problem on compensation of a two-stage op amp. For extra context, this example problem is originally from an exam of a now-concluded course offering, so it is ...
- 657
2
votes
2
answers
84
views
Clamp transistors in folded cascode for slew rate improvement
Razavi's textbook Design of Analog CMOS Integrated Circuits (2nd edition) includes a possible option of improving the slew rate of a folded-cascode amplifier in Figure 9.77, included below (along with ...
- 657
1
vote
3
answers
107
views
Converting a 74LS74 and a 74LS193 to CMOS. What inputs need pullups and what needs pulldowns
I have a circuit I traced out off an old, dead PCB that came from the early 90s. It was using TTL chips back then. One thing I noticed is that it has a dual flip-flop. One flip-flop is being used as a ...
- 75
0
votes
2
answers
85
views
Need help identifying circuit diagram symbol
In the datasheet for Hamamatsu s13131-1536 CMOS line sensor(https://www.hamamatsu.com/content/dam/hamamatsu-photonics/sites/documents/99_SALES_LIBRARY/ssd/s13131-1536_kmpd1159e.pdf) there is this ...
1
vote
3
answers
217
views
Why does current mirror need a diode connected configuration?
I am not able to understand why the connection between gate and drain of the first MOS is required.
A similar question to this is asked here but it is BJT based current mirror and the answer is there ...
0
votes
1
answer
48
views
Unusual Transconductance Equation
I am a math-heavy electronics noob, and I was reading a paper when I came across this equation:
$$g_m=\frac{2 I_D}{\left(V_{G S}-V_{T H}\right)}\left[1-\frac{1}{2} \frac{\theta_1\left(V_{G S}-V_{T H}\...
3
votes
2
answers
159
views
Why does a 1k resistor between signal and MOSFET gate minimize the output rise time of a CD4000 IC?
I've come across a circuit behavior that I find surprising and don't really know how to go about researching it further except just to ask here:
I am building a circuit that needs a momentary RESET ...
- 410
1
vote
2
answers
141
views
On synthesizing CMOS implementation given logic function with uncomplemented literals
I understand that the basic idea is to construct a PUN such that \$V_f\$ (the output node) is raised up to \$V_{DD}\$ if and only if we have input valuations such that \$f = 1\$, and similarly to ...
- 309
0
votes
0
answers
79
views
How do I calculate Trise and Tfall for a cmos inverter?
I am an undergrad student and learning about mosfets as well as inverters using mos. I wasn't able to find a clear formula anywhere regarding the rise and fall times during switching between logics. ...
0
votes
2
answers
56
views
How to convert RS-422 paired-signals to one CMOS signal
I am able to find several commercial ICs for converting CMOS or TTL input levels translate to RS-422 output levels. (I.e One 5V single input to two differential output). However, I couldn’t find how ...
- 119
0
votes
0
answers
39
views
S11108 CMOS linear image sensor not working
I'm looking for help/advise working with a S11108 is a CMOS linear image sensor. My son is studying computer science at university who has been helping. We are using the S11108 to scan a moving ...
2
votes
2
answers
113
views
What are the theoretical constraints that prevent making the propagation delay of a CMOS inverter arbitrarily small?
I'm taking a course on CMOS circuit design and, from my course slides, I have that the the low-high propagation delay of a matched CMOS inverter is given by
$$
\frac{2\,L\,{\left(C_{\textrm{DB2}} +C_W ...
2
votes
1
answer
62
views
Why is the output resistance of a CMOS inverter determined by the NMOS when the output is high but by the PMOS when the output is low?
For the output pulled high, my professor's slides give this diagram:
and the equation
$$
r_{DSN} = \frac{1}{k_n'\left( \frac{W}{L} \right )_n \left(V_{DD} - V_{tn}\right)}
$$
and for the output ...
0
votes
1
answer
40
views
I need to calculate the bandgap voltage in terms of threshold voltage mismatch (circuit shown in figure). Does my equation look correct?
I computed the change in current due to threshold mismatch, in my assignment question they asked us to express the bandgap voltage due to delta Vth in terms of gm. Does this look equation look correct?...
- 37
1
vote
2
answers
96
views
Wrong wiring in a transistor circuit
This circuit confused me, when A=0 the PMOS (assuming its source is connected to the power supply, because it's not mentioned by the exercise) will be ON so the circuit between the power supply and ...
- 81
2
votes
2
answers
1k
views
Exercise asking what a transistor circuit does
This exercise from the book Introduction to Computing Systems from Bits and Gates to C/C++ & Beyond by Yale N. Patt and Sanjay J. Pattel asks what this transistor circuit does. I don't understand ...
- 81
1
vote
1
answer
111
views
Implementing a logical function to a circuit
This is an exercise in the book Introduction to computing systems from bits and gates to C/C++ & beyond by Yale N. Patt and Sanjay J. Pattel.
It asks to label the inputs of that transistor-level ...
- 81
0
votes
1
answer
51
views
MOSFET circuit: output connected to both 0 and 1
In this circuit when A = 0 and B = 1 (or when A = 1 and B = 0), the OUT wire is connected both to high voltage (1) from the power supply and to ground (0) at the same time, what would be the output in ...
- 81
0
votes
1
answer
54
views
Strange plot of voltage source in CMOS inverter circuit simulation
I made a simple simulation of a CMOS inverter in everycircuit and the results look reasonable enough when I just plot the voltages on the input and output nodes. But, for some reason, the voltage ...
0
votes
2
answers
105
views
74HC373 Shift Register?
This is my first attempt at designing a discrete digital circuit.
Basically I'm looking to count the number of times a button is pressed. Each button press will trigger a new output. And the final ...
- 353
0
votes
1
answer
81
views
Is there a CMOS-based analog compute chip that uses hybrid technology nodes? (e.g. 14 nm for digital part such as SRAM and 28 nm for analog part)
In CMOS-based analog computing, there always are mixture of analog and digital parts.
For example, the computation is performed in analog domain and the storage of on-chip data in performed in digital ...
- 1
3
votes
3
answers
512
views
What is the meaning of the "E" in the part number of Texas Instrument's CD4000 series?
Most CD4xxx chips come with a part number of CD4xxxBE or CD4xxxUBE.
Official documentation tells you that B and UB stand for buffered and unbuffered outputs respectively, and mentions that the last ...
- 33
0
votes
5
answers
124
views
Should I parallel unbuffered inverters in a CMOS crystal oscillator circuit?
I want to use a 74HCU04 unbuffered inverter oscillator circuit as a digital clock source on a PCB, as referenced in this TI app note:
Appnote SZZA043
It's mentioned in the note, the inverter gain is ...
0
votes
0
answers
46
views
Need help in understanding circuit of PMOS reverse
Given 2 PMOS enhancement: Vdd = 5 V, k1/k2 = 9, Vt = -1.
I'm trying to find Voh, Vol, Vil, Vih.
I would appreciate help and explanation.
- 1
0
votes
1
answer
104
views
What affects the unity-gain bandwidth (UGB) of a symmetrical OTA?
I am trying to determine the sizing of transistors in the OTA as shown below. A strange thing I found earlier was that a small output impedance of M5 would cause a much smaller GBW than designed, as ...
- 309
0
votes
0
answers
121
views
Miller effect in CMOS inverter
I have a doubt concerning the Miller effect. I found on more than one source the following situation:
where Cgd1 and Cgd2 are modeled as a capacitor connected to ground as a consequence of the Miller ...
- 101
3
votes
0
answers
56
views
How can I design two CMOS ring oscillators so that I can observe sub harmonic injection locking?
I am trying to design two CMOS ring oscillators for the purpose of observing sub harmonic injection locking. I want the injection frequency to be two times the locking frequency. I have designed some ...
- 107
0
votes
1
answer
53
views
What is the correct CMOS setting?
I'm having trouble understanding the correct configuration, because the CKT below has mosfet channel n symbology, but when I see the configuration it looks like p channel connections and looking at ...
- 363
2
votes
2
answers
346
views
3V oscillator to 5V µC with an 74HCT inverter (12.8 MHz) - bad idea?
I'd like to use an AVR (ATmega328P-AU to be precise) in combination with a fairly accurate oscillator for timing purposes. I stumbled upon the fact that oscillators which have greater accuracy mostly ...
- 33
0
votes
0
answers
39
views
Is it feasible to model a CMOS inverter as a control system?
I have some knowledge of basic control theory from a course I took this summer and I'd like to use it to model CMOS circuits for an independent study project with one of my EE professors this upcoming ...
2
votes
1
answer
82
views
Translating a negative mV signal to CMOS level
I'm currently thinking of a circuit that will need to translate the output of a SIPM into a CMOS signal. And I'm looking for some input and ideas.
The SIPM output signal has a rise time of ...
- 183
0
votes
1
answer
70
views
Drain Terminal of a Multiplexer
I am confused about some of the aspects of how a multiplexer works. In particular, I am working with an ADG508A multiplexer. Looking at its functional block diagram (Fig 2, top panel, page 1) and the ...
- 103
0
votes
0
answers
21
views
How to perform image windowing on the OV5647 CMOS sensor?
I have an Arducam 5MP OV5647 Motorized Focus CMOS camera module (which is the same as a regular 5MP Raspberry Pi Camera, but with a motorized lens for manual focusing).
https://www.arducam.com/...
- 292