Questions tagged [cmos]

"Complementary Metal-Oxide Semiconductor" is a process which implements a combination of PMOS and NMOS transistors. Most current digital logic is implemented in CMOS. Its cost-effectiveness due to being so widespread means many other applications have become common as well, such as in analog design, image sensors, telecommunication, etc.

Filter by
Sorted by
Tagged with
0
votes
2answers
67 views

Transistor fingering reducing gate resistance

In the transistor fingering diagram (b) below, shouldn't the two transistor fingers be connected at the right side as well in order for the fingers to actually appear in parallel? As it is right now ...
0
votes
2answers
65 views

Is it ok to connect a CMOS logic output to a power-on-reset circuit like this?

I am trying to make a power-on reset circuit that can also be manually reset. The reset is active-low. When the capacitor is charging, I'm assuming 5v will be present on pin 10. Would this damage the ...
1
vote
1answer
34 views

Flip Flop Switch for a Rocket

I am looking for the best (closest) way to create a solid state version of a dual coil latching relay. Essentially, a circuit that has two inputs (on & off) that when pulsed will flip flop the ...
0
votes
1answer
43 views

Thevenin Equivalent of Common-Gate Amplifier

I'm having some difficulty understanding how Razavi determined \$V_{\text{in, eq}}\$. My understanding was that the small-signal model allows us to model the PMOS device as a constant current source (\...
2
votes
0answers
30 views

MOSFET diffusion to substrate capacitance

in order to eliminate body effect one way is to connect the substrate to source when the well is for a single device (PMOS with a well in a CMOS for example) , but i read that it increases the source ...
-1
votes
0answers
31 views

Drawing CMOS logic circuts from expression

Draw the CMOS logic, calculate transistors and determine the worst-case analysis. 60ps R= a! b!+b!c+abc! I looked everywhere. if you know a source please fill me in.
0
votes
1answer
53 views

Combining CMOS and TTL with drivers and Leds with relay driver

I need some practical advice on how to combine different component types. I designed a circuit with at the heart an up/down counter (74f269) The outputs of the counter are connect to via 330 ohm ...
0
votes
1answer
198 views

Why does decreasing the voltage also decrease the circuit frequency?

In CMOS circuit design, we know dynamic power is propotional to \$V_{dd}^2Cf\$, so the best way to reduce dynamic power is to reduce Vdd. However, according to the textbook, Keeping the same clock ...
0
votes
0answers
48 views

DC>DC Isolated Converter (ADuM5401)

I'm in a bit of a quandary as to if I've approached something the right way or if there's an obvious solution I'm missing. (Sorry for lack of schematic, still WIP). Goal: Self-powered isolated USB >...
1
vote
1answer
40 views

Industry Standard for Memory Address Decoder Design

I am currently designing the address decoder of a piece of ReRAM that will be sent to TSMC and manufactured. I have studied in class and textbook that there are two common address decoder designs. One ...
0
votes
1answer
58 views

Needed help in drawing CMOS design and euler path p-tree ,n-tree for boolean function

I have the expression \$Z=(A(D+E)+(BC))'\$, I'm trying to draw CMOS logic but I guess I've gone wrong somewhere. I'm unable to draw Euler path for this diagram
-1
votes
1answer
102 views

What logic function does this layout implement?

I'm having trouble wrapping my head around the following layout. I can't understand what logic function it is implementing. For what I understand the rightmost side implements a CMOS inverter with ...
1
vote
1answer
36 views

Clarification of the layout

Can someone please clarify me what the rightmost strip of this layout is? I know the red ones are poly, the squares are contacts, in green the n-well, in brown the p-diffusion and in blue with ...
1
vote
1answer
77 views

How to interpret this layout?

I'm wrapping my head around this layout, I'm trying to extract its schematics so I can determine the logic function. For what I understand we have two PMOS and two NMOS transistor. I see one ...
-2
votes
2answers
59 views

Why are contacts used to connect metal to active layers but not poly to active layers? [closed]

In the CMOS layouts that I've seen, metal layers always seem to connect to n+/p+ active regions by using a contact, but poly layers are just laid directly over them. Is there a reason we don't use a ...
0
votes
0answers
25 views

What's the small signal model of this CMOS differential pair?

I cannot derive the small-signal model for this differential pair: My goal is to observe the effect of transistors M6 and M7 which should create a hysteresis effect in the output equation for Vo1 or ...
0
votes
2answers
26 views

How to simulate digital logic using CMOS technology (MOSFET) in Proteus?

Hello I'm having trouble with Proteus to do this CMOS logic simulation, I used transistors, I can do the logic perfectly, but when I use CMOS for some reason the logic doesn't work. I used the methods ...
1
vote
1answer
59 views

Why don't pull-up/pulldown resistors prevent microcontroller I/O pins from changing state?

Apologies for the vague title, wasn't sure how to summarize the question. I've been struggling with this for two days and feeling a bit desperate. This is how I understand simple CMOS gates work in ...
0
votes
2answers
65 views

Designing Schmitt trigger oscillator using CMOS NAND gate

I am designing a Schmitt trigger oscillator based on a CMOS NAND gate. The block diagram along with schematics and its results are attached for your reference. I am using the CADENCE tool with 0.35um ...
0
votes
2answers
69 views

How to make one of the CD4040 output pins reset another counter?

Why does pin 4 (Q7) 4040 reset itself perfectly but not reset 4026? I would like the signal from this pin to reset the 4026 as well, but it doesn't. I also do not understand why this pin has such a ...
0
votes
1answer
24 views

Load Capacitance in CMOS Circuits

I am studying VLSI Coursers and I came up to a question. what happens if we don't use output load in CMOS circuits? what happens to overshoot/undershoot and circuit delay? thanks
0
votes
1answer
40 views

Output behavior of CMOS

Assume a CMOS-cell, which is an inverter(?) here and hence, the input is connected to both transistors, but please let's treat the transistors independent from each other. ...
0
votes
0answers
23 views

Identifying source and drain for a transistor [duplicate]

My question is related to this post (the comments below). Basically, how can I identity the source and drain of a transistor ? I thought that drain and source were totally symmetric inside of NMOS or ...
0
votes
1answer
45 views

CMOS inverter: circular reasoning to understand it?

I am confused by a litte detail with CMOS inverter. Note that I am really a beginner in CMOS "theory". Here is the electrical circuit: At "first view", I understand the principle. ...
0
votes
1answer
37 views

General CMOS circuit

In any CMOS circuit like an inverter or an n-input NOR or NAND gate, where the pMOS network is connected at the top to Vdd source terminal and nMOS network is connected at the bottom to the ground ...
0
votes
3answers
45 views

cmos impedance calculations

I posted a question about a week ago about impedance and have a follow up if you will indulge me. I'm comparing input and output impedance from TTL and CMOS ICs, specifically 7401 and 4011 NAND gate ...
1
vote
2answers
23 views

Is sum of currents equal to capacitor current for NMOS Inverter with Capacitor as Load?

I found this in my lecture notes and could not understand how drain current is equal to sum of load and (IL) capacitor currents (ICL) given in the figure for a NMOS Inverter with capacitor load. By ...
0
votes
1answer
66 views

CMOS vs TTL power and impedance

I need to compare and contrast a CMOS IC with a TTL IC. I've chosen a quad 2 input NAND gate IC, 7400 for the ttl version and 4011 for the CMOS. I'm having a bit of trouble with 2 of the requirements. ...
0
votes
0answers
41 views

Phase noise improvement after gain compression

The very curious question/observation is about the improvement in phase noise for input power levels greater than P1dB. I am designing a cascode 3 stage distributed amplifier in 65nm CMOS technology. ...
0
votes
1answer
48 views

Why would a CD4060BE produce a copy of an input clock signal?

I am making a CMOS logic clock and I have a problem with the 1Hz signal generator (see schematic below). When I connect up the CD4060BE chip to a crystal the output on Q8 of the second chip does not ...
0
votes
0answers
43 views

What is the logical equivalent to this CMOS circuit?

I'm examining a chip die and I'm trying to figure out what this arrangement of transistors is equivalent to if it's a logic gate or what (something you could get in a 74LS chip for example). simulate ...
0
votes
0answers
39 views

Is there such a thing as an RF CMOS pdk?

In this PhD thesis (page 10) about some dust particle detector that was based on an RF chip , we can read " Since this thesis was the first attempt in this way, there were not any primary ...
1
vote
1answer
55 views

Delaying clock pulses without adding (much) extra circuitry (CMOS)

I have a counter (74HC193) counting up with Qn outputs being decoded by a demultiplexer (74HC138). My clock pulses (CP) are no less than 100 microseconds long and the interval between them is always ...
0
votes
0answers
31 views

Is bandwidth of cmos comparator important?

The concept of bandwidth is developed based on small-signal analysis. However, comparator works usually under large-signal conditions, and transistors are not in saturation region, since comparator ...
1
vote
2answers
189 views

Common-Source Amplifier

Hi, I have two ways of thinking about this and I don't know which is more correct: Explanation A There are essentially two devices there, each trying to force a different current into the same branch. ...
2
votes
2answers
143 views

Soft errors from SEUs/SETs in early 8-bit microprocessors?

Why is it that soft errors due to single-event upsets/transients never seemed to be a problem in early 8-bit microprocessors, like the MOS 6502 or the Zilog Z80? The microprocessors themselves were ...
0
votes
0answers
31 views

ADG714 analog switch daisy chain issue

As per shown in the below schematic, I have two ADG714(datasheet) octal SPST analog switches connected in the daisy chain configuration. IC7 is connected to the STM32F303 controller. connenction of ...
2
votes
0answers
89 views

How to measure Common Mode Range and Output Swing of a CMOS Differential Amplifier in LTspice

I'm designing a CMOS opamp in LTspice here is my current design. The amplifier obtains a DC gain of roughly 50dB and has a phase margin of 70 degrees at a ω (unity gain frequency) = 250 MHz. I'm also ...
1
vote
2answers
48 views

Can drain and source length be smaller than minimum channel length in CMOS technology?

I know the channel width can't be smaller, but what about drain and source? Say, in 0.18u technology, what would be a typical drain/source length?
2
votes
1answer
61 views

3.3V GPIO output of esp01 interfacing to CMOS logic gates operating at 12V

I want to check this circuit for proper interfacing, I am interfacing a 3.3V output to CMOS CD4071 with supply voltage of 12V. -First I used a low threshold voltage NMOS TN0106 as shown in the circuit....
1
vote
0answers
29 views

Recording multiple pixels simultaneously in CMOS or CCD image sensors

Is it possible to recording multiple pixels simultaneously in CMOS or CCD image sensors? Because of the low intensity of radiation I need to increase the surface area of the each pixel (photodetector)....
0
votes
1answer
68 views

How to fix this uln2003 circuit?

I am trying to make understand to working of uln2003 but not able to run this circuit properly please anyone help me to understand why this is not working..
3
votes
2answers
85 views

How deos this clock generator work?

This circuit shows a clock generator, where a capacitor is charged to a certain voltage for half a period (phi opening switches S1 and S2). The same voltage but with negative polarity will be shown to ...
2
votes
1answer
45 views

plot the max slopes of Voltage-Transfer characteristics in ngspice

I have implemented a basic CMOS inverter in ngspice, performing a DC sweep analysis on the input voltage to obtain the Voltage Transfer Curves (Vout vs Vin) at varying Vdd voltages. ...
3
votes
0answers
58 views

What is the shortest possible *channel length* in a currently available commercial CMOS process?

I'm aware that terms like "5 nm", "7 nm" for the latest technology nodes no longer refer to any linear dimension of the transistors, although I have seen some interpretations in ...
0
votes
0answers
32 views

2 trnsistor mosfet in line

i tried to calculate the cuurent that flow into 2 trnsistor that conect in line. the drain of the first is conect to the source of the other. and they conect to the same Vd. one of them is l1=1010^-4 ...
0
votes
1answer
138 views

How to design a voltage follower/Unity gain buffer circuit using MOSFET?

I am trying to design a voltage follower to drive a resistive load using MOSFET as a peripheral circuit. I am using this simple circuit using two NMOS transistors. The output is following the input. ...
1
vote
0answers
28 views

Powering cmos invertor from battery charging line

I use MCP73831/2 for charging a battery. But now I have to power a logic gate from the same line (I mean connect gate's vcc directly to the battery and to charger output). Is it a good idea? Could the ...
0
votes
1answer
53 views

No unconnected inputs yet ICs (logic gates) still seem to yield erratic/odd behaviour

I just finished building a 4-bit adder on a breadboard and I am experiencing some quite odd/erratic behaviour and I am wondering why. The actual circuit/logic works as intended, meaning the 4-bit ...
0
votes
0answers
55 views

What causes these peaks in the output voltage of a CMOS inverter?

The figure is taken from https://ece.uwaterloo.ca/~mhanis/ece637/lecture7.pdf There is no significant inductive element in a CMOS inverter, so what is the cause of these peaks while switching?

1
2 3 4 5
16