Skip to main content

Questions tagged [cmos]

"Complementary Metal-Oxide Semiconductor" is a process which implements a combination of PMOS and NMOS transistors. Most current digital logic is implemented in CMOS. Its cost-effectiveness due to being so widespread means many other applications have become common as well, such as in analog design, image sensors, telecommunication, etc.

Filter by
Sorted by
Tagged with
-6 votes
0 answers
49 views

draw the circuit [closed]

Please draw the circuit for the corresponding timing diagram.
MUSAIB IBN HABIB MIKDAD's user avatar
0 votes
1 answer
56 views

Non buffered CMOS logic gates working under load when using real components (LTSpice Sim)?

I'm experimenting with CMOS logic gates and have encountered something I am having a hard time understanding. When I make an inverter using ideal components and measure the output, it works exactly as ...
dka13's user avatar
  • 165
1 vote
0 answers
33 views

Gate Oxide vs. Source/Drain ESD protection [closed]

It's common practice to not tie VCC/GND directly to the gate of a MOSFET but use tie HI/LO cells instead in order to protect the thin gate oxide of the driven transistor in the event of unstable ...
SalvagedDoor's user avatar
8 votes
2 answers
2k views

How can the CMOS version of 555 timer have the output current tested at 2 mA while its maximum supply is 250 μA?

As per the Datasheet of LMC555, the maximum supply current is 250 μA @ 5 volt supply voltage. How come the output current reach 2 mA, I mean where did the IC get the extra (2*1000-250) μA? Maybe I ...
AbdAllah Talaat's user avatar
-1 votes
1 answer
92 views

Why isn't this inverter based amplifier amplifying?

I was studying about CMOS inverter an amplifier for analog applications instead of its more well known application as a switch for digital circuits. For the following inverter based circuit : I think ...
Koustubh Jain's user avatar
1 vote
0 answers
30 views

Identify Regulator from Canon Camera CMOS Board

I'm trying to Identify 3 Regulators from a Canon Camera CMOS Board The only hint I have is L814, A1BE5, LA42 But I don't know how to find the actual reference of the parts, I need them to repair my ...
Gamer Gamer's user avatar
0 votes
0 answers
96 views

Designing a 0.18-µm CMOS Multi-Stage MOSFET Amplifier (150 V/V Gain, 1-5 GHz) Without External Resistors/Capacitors

I'm working on a project to design a full-transistor-based (MOSFET) multi-stage amplifier using 0.18-µm CMOS technology. The requirements for the amplifier are as follows: Voltage gain of at least ...
Raczidian's user avatar
2 votes
1 answer
179 views

Bus contention - possible momentary short circuit with 74HC

I have a tristate bus where both input and output are controlled via 74HC573 latches, with only one latch OE (output enabled) active at any time. My concern is that the signal update from the control ...
padawan's user avatar
  • 121
1 vote
2 answers
67 views

Designing a particular clock cycle series with glue logic/CMOS/TTL for serial data without a uP

I am looking to design an interface for serial data that runs for 31 cycles (not 32, I know), but with uneven cycles to transmit serial data. Each cycle is 8 clock pulses (at 7MHz). For the first 20 ...
paraparabolic's user avatar
1 vote
1 answer
58 views

Issues with switch debouncing

I am having some issues with debouncing a switch with an RC filter and 74HC14 Schmitt-trigger inverter IC. I am using a standard circuit that is linked in the datasheet. The circuit in question here ...
Zackery Fleming's user avatar
0 votes
0 answers
53 views

differential gain for mismatched \$g_m\$ in differential amplifiers

I couldn't understand how the author came up with the expression of differential mode gain. He states to look from the Fig 4.17 to derive this expression, whereas the fig 4.17 has no mention of \$R_{...
wolff's user avatar
  • 13
0 votes
1 answer
47 views

NE555 Trigger Voltage

I'm looking to use an NE555 in monostable mode, generating a pulse of defined length whenever the trigger level drops to a low state. I was planning on powering the NE555 from the same source as my ...
Jacob Shaw's user avatar
2 votes
1 answer
61 views

Multiplexer with transmission gates

I have a multiplexer with 2 selection bits (S0 and S1), 4 inputs (x0, x1, x2, x3) and 1 output (y). The truth table for this circuit is the following: S1 S0 y 0 0 x0 0 1 x1 1 0 x2 1 1 x3 I also ...
S214ky's user avatar
  • 63
1 vote
0 answers
106 views

6T SRAM Simulation on Cadence

I had recently studied about SRAM in Computer Architecture and learned that a SRAM Cell is actually made up of MOSFETs. I was curious to learn more about the architecture of SRAM, for which I read ...
Inder Saini's user avatar
2 votes
1 answer
37 views

Clock feedthrough in 5T OTAs?

I'm using a 5T OTA as a comparator, and the reference voltage is applied to the gate of M2 by another circuit - I modelled it with a capacitor (100fF) charged to Vref, just for describing my question. ...
Jack Black's user avatar
1 vote
0 answers
45 views

How can a ring oscillator's frequency be inversely proportional to supply voltage?

I was reading this paper on Ring Oscillators, when I came across the following statement on the first page : since the delay of an inverter falls as the supply voltage \$V_{DD}\$ increases, the ...
Koustubh Jain's user avatar
0 votes
0 answers
18 views

Pinout for Onsemi AR1335 (63-ODCSP/63-WFBGA/CSPBGA)

I am currently working on a project utilizing the Onsemi AR1335 (AR1335CSSC11SMKA0-CP) CMOS Image Sensor, 13 MP, 1/3". I chose this sensor since my MPU/APU platform (NXP i.MX8M P) already offers ...
Sofia Braun's user avatar
1 vote
2 answers
111 views

Why simulation of single NMOS/PMOS on LTspice has big difference with manual calculation using Level 1 Standard Parameters?

I am researching the mode of operation on PMOS and NMOS using Level 1 standard parameters. This is the information of the NMOS circuit to be designed. Using transistor model level 1 parameters, ...
CJ. T's user avatar
  • 41
3 votes
1 answer
176 views

Why did my CR 2032 CMOS battery with reversed polarity discharge when connected?

I own an Intel NUC which we use as a HTPC. It stays turned off most of the time minus game day/movie nights. It by default uses a JST connector standard polarity CR 2032 3V battery. I ordered a ...
itcorekj's user avatar
0 votes
0 answers
51 views

A good rising edge D Flip Flop CMOS implementation

I'm currently trying to create a basic CPU with SOT32 CMOS transistors. I have made a good design and architecture and began testing and ordering PCB's. However, I found that there are a lot of rising ...
MathijssY Klaver's user avatar
0 votes
1 answer
58 views

A question about layout: How to connect the gate to metal 1 layer?

I'm trying to draw a NMOS as shown above, but have some problems (the figure is from Razavi's book, the green box I added represents the N implant layer) In the process I used, there's a design rule ...
Jack Black's user avatar
0 votes
1 answer
81 views

Sony IMX421 Eval board with IMX422 Sensor - produces odd repeating patterns instead of true images

I am working on an application that involves use of a Sony IMX422 CMOS image sensor - namely writing VHDL code to act as a receiver interface to the sensor over an SLVS bus. the setup involves a ...
CNfan's user avatar
  • 39
1 vote
1 answer
35 views

TP223 replacing a button?

I have a button which does some resistor-alteration: simulate this circuit – Schematic created using CircuitLab Now I wish to replace SW with TP223 (link): ...
Daniel's user avatar
  • 959
0 votes
1 answer
90 views

For a CMOS closed-loop op amp, under what condition will the output influence the saturation condition of transistors inside the amplifier?

This question is from Example 9.6 of Razavi's book. Design of CMOS analog integrated circuits. I will first outline my confusion regarding Razavi's solution and the clarification of the inequality ...
Tong Su's user avatar
  • 113
0 votes
0 answers
84 views

Single Switch with Momentary and Latching/Hold Properties Using CMOS/Logic (no µP/microprocessor)

I am looking for a CMOS/logic based solution (no µP/microprocessor) to a momentary switching scheme I'd like to implement that involves the following scenario: 1: pressing a momentary switch engages ...
paraparabolic's user avatar
0 votes
0 answers
115 views

LUP.6 DRC ERROR

I got a latch up #6 error while performing a DRC. LUP.6 { @ Any point inside NMOS source/drain space to the nearest PW STRAP in the same PW <= 30 um @ Any point inside PMOS source/drain space to ...
rosetta's user avatar
1 vote
2 answers
87 views

Comparator Using Common Gate CMOS

I am currently in the process of designing and testing a CMOS Comparator based of a Common Gate Topology. Below is an extract of the ref circuit I am using: The authors in the paper mention "...
soccernismo's user avatar
0 votes
0 answers
30 views

Single stage CMOS amplifier PSpice design

I'm at the very beginning of my electronics adventure and facing the given problem: I'm trying to design a single-ended CMOS amplifier with small signal gain = 15dB at 10kHz. The load capacitance has ...
kazap's user avatar
  • 1
0 votes
1 answer
48 views

How to translate 0V pulldown switch to negative voltage?

I have a circuit with a momentary switch connected between GND and a net with a pullup resistor (switch output is 0V while pressed). This switch signal is then buffered by a flip-flop before feeding ...
jlam98's user avatar
  • 38
2 votes
0 answers
85 views

Negative PSRR of Two-Stage Op Amp

From page 4-9 of this lecture note https://pallen.ece.gatech.edu/Academic/ECE_6412/Spring_2004/L180-PSRR-2UP.pdf, it gives example on how to model a Two-Stage Op Amp to find the PSRR- when \$V_{Bias}\$...
Matt's user avatar
  • 149
3 votes
0 answers
364 views

Minimalist 3-input XOR gate using CMOS

As an enthusiastic noob to CMOS I browsed multiple examples of XOR gates using PMOS and NMOS. I find it hard to find any good examples of 3-input XOR gates; I found an example of a 4 FET 2-input XOR ...
David H Parry's user avatar
3 votes
1 answer
84 views

Having trouble understanding a basic MOS OpAmp diagram

Taken from: Analysis and Design of Analog Integrated Circuits, 4th Edition by Paul R. Gray , Paul J. Hurst, Stephen H. Lewis, Robert G. Meyer. Page unknown. Hi. I am studying about MOSFETs and I am ...
It's_A_Me's user avatar
1 vote
0 answers
68 views

Lower transistor count CMOS implementations of XOR and/or XNOR with leakage current only for all static input combinations

I'm perfectly fine with the 10- and 12-transistor implementation(s), see e.g. en.wikipedia on XOR gate CMOS implementation. There are variations of 6-transistor pass-gate XOR implementations (...
greybeard's user avatar
  • 1,956
3 votes
1 answer
359 views

Using a function generator as a clock source to drive several ICs (CD4000 CMOS series & 74 TTL)

I am building a circuit that uses a 4 MHz reference carrier. The used ICs are basically XOR 7486 and NOT 7404, CD4013 flip-flop, etc. I have a function generator which is capable of providing up to 5 ...
Mohamed Abuain's user avatar
0 votes
1 answer
115 views

CMOS logic gate output impedance

I generated +/-5V 1MHz square wave signal from D-flipflop (part number:CD4013).i planned to use the signal as an excitation for LC tank(L:47uH C:500-1000pF) through a coupling capacitor.I planned to ...
dhuwarkesh's user avatar
1 vote
1 answer
86 views

Getting temperature dependence for a beta multiplier circuit

I am currently working on designing a beta multiplier voltage reference, and came across this paper. I am slightly confused as to how they ended up with equation (6) after taking the derivative of (5) ...
soccernismo's user avatar
0 votes
0 answers
87 views

Camera chip identification, 12-pin, SMD, HBCZ 60X

May I ask for your knowledge and take a look at this image of a IC. I found this in a cmos camera that spits out a low latency <10ms video UDP stream. I think this IC is responsible for reading a ...
Dennis de Graaf's user avatar
1 vote
0 answers
57 views

MOS transconductance plot using LTspice

I am trying to plot the transconductance of a MOS using LTspice in DC sweep. However, I heard that there is no dy/dx function in LTspice. Therefore, I came up with another way. Keep the drain voltage ...
Willis Lin's user avatar
0 votes
1 answer
54 views

TC160G IC pin numbers

I'm finding the pin numbers for this Toshiba IC. Google search results shows this Datasheet, but it doesn't have the pin numbers written. Thank you. Bonus: What does this logo represents? They're all ...
Assidious123's user avatar
0 votes
0 answers
42 views

CMOS in a switched capacitor

If CMOS is used in a switched capacitor circuit, is it possible to ensure that the pair of switches are break-before-make? I'm specifically considering the wiring of the CD4007 CMOS transistor array ...
Mark Smith's user avatar
0 votes
1 answer
98 views

Process compatibility between a non-planar avalanche photodiode and planar CMOS at 0.130μm process technology node

I plan to integrate a non-planar P⁺⁺/i/P⁺/N⁺⁺ avalanche photodiode (APD) array with a peripheral control circuit (e.g., trans-impedance amplifier, analog-to-digital converter, and quenching circuit) ...
Amita Rawat's user avatar
2 votes
1 answer
176 views

How to eliminate other possible solutions when doing DC analysis of Analog CMOS

This is my LTspice schematic. I want to calculate \$V_{D5}\$, \$V_{D1}\$, \$V_{o}\$ with vpasolve of matlab. (body effect is omitted) $$I_D = K \frac{W} {L} (|V_{GS}| - |V_{th}|)^2 (1 + \lambda |V_{...
kile's user avatar
  • 897
1 vote
1 answer
108 views

Schmitt trigger using CMOS inverters [duplicate]

How does this circuit exactly work? Source: Problem 8.14, Introduction To Digital Microelectronic Circuits by K. Gopal Gopalan
FISqrt's user avatar
  • 161
1 vote
1 answer
161 views

CMOS (Energy Supply of voltage) [closed]

Can someone please explain why, when \$ln\$ is transitioning from low to high, the energy supplied is \$C_{vdd}\cdot V_{dd}^2\$?
Timothy Garott's user avatar
0 votes
1 answer
80 views

MOSFET circuit design

Consider this organization of P-MOSFETS and N-MOSFETS. A CMOS cell has a complementary property which refers to the use of both n-type (N-MOSFET) and p-type (P-MOSFET) transistors within the same cell ...
Angela Ilieva's user avatar
0 votes
0 answers
54 views

DC analysis of a CMOS comparator

I'm designing a strongarm latch comparator in virtuoso using gpdk90 and I'm not seeing what I'm doing wrong while doing DC simulations. I want to extract the comparator's offset but the output is ...
Scully's user avatar
  • 3
1 vote
1 answer
164 views

Where am I wrong in understanding feedback network?

The following is from the book Design of Analog CMOS Integrated Circuit, Page 314. Calculate the open-loop and closed-loop gains of the circuit shown in Fig. 8.66(a). Assume that λ = γ = 0. For ...
kile's user avatar
  • 897
0 votes
0 answers
181 views

How to write the truth table for this CMOS circuit

How would you get the truth table for this CMOS circuit where there are two outputs 'A' and 'B' and one output 'Out'? And from that, how would you derive the the Boolean expression along with the ...
Sabreen Kaur's user avatar
2 votes
7 answers
424 views

A circuit that temporarily keeps the toy on after pressing the button

I'm working on a project to add a time delay to the button, so that when pressed, the toy plays for, say, 15 seconds and turns off. The toy is intended for children with disabilities and sometimes ...
JSK's user avatar
  • 35
0 votes
0 answers
114 views

Reasons for lower flicker noise in PMOS vs. NMOS - buried channel, mobility

There have been other questions on the site about why PMOS devices are observed to have less flicker noise than NMOS devices, for example this one, but I'm not sure it's correct. On mobility - the ...
Halleff's user avatar
  • 677

1
2 3 4 5
22