Questions tagged [cmos]

"Complementary Metal-Oxide Semiconductor" is a process which implements a combination of PMOS and NMOS transistors. Most current digital logic is implemented in CMOS. Its cost-effectiveness due to being so widespread means many other applications have become common as well, such as in analog design, image sensors, telecommunication, etc.

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Understanding the Schmitt trigger circuit using CMOS inverters

This is the circuit I'm trying to understand: What I understand: Clearly, whenever \$V_{out}\$ is low \$M_{3}\$ is off and the strength of \$M_{2}\$ and \$M_{4}\$ surpasses that of \$M_{1}\$ so the ...
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1 answer
201 views

How to test a cmos sensor without breaking it?

A couple of weeks ago my dad gave me a Syma X5C H5C camera that he found. I wanted a camera for my robot project and I tried to just take the camera but I found a ...
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Why we have positive voltages for ground/VSS supply?

I have seen circuit designs that use multiple power supplies/grounds, and some of the VSS ground supplies are non-zero, for example: 0.3V. I am curious to know why this is useful. Where is it used? ...
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1 answer
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"Tiny " XOR gate simulation not working

I am trying to implement this below XNOR circuit in Cadence. I am using GPDK 180nm and 1.8 V power supply. Here is the schematic in Cadence. Doing a DC simulation, I am not getting proper voltages at ...
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Noise sensitivity to output impedances [duplicate]

A lower value of output impedance in a CMOS inverter leads to less sensitivity to noise of the inverter. Can someone elaborate regarding this? The quote comes from Digital Integrated Circuits by ...
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3 answers
299 views

Designing Schmitt trigger oscillator using CMOS NAND gate

I am designing a Schmitt trigger oscillator based on a CMOS NAND gate. The block diagram along with schematics and its results are attached for your reference. I am using the CADENCE tool with 0.35um ...
1 vote
3 answers
456 views

Differential Amplifier with Hard Limiting

I'm currently going through RF Microelectronics by Razavi. In chapter 3 he presents an example where the following signal is applied to a differential amplifier with a tail current source. $$Acos(...
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How to implement this simple truth table with CMOS logic?

In my project I intend to use an USB-audio switch. It has a SELECT input pin which must be high when an USB headset is connected to the USBC port, and low in any other case. When a USB headset is ...
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1 answer
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D flip-flop in Cadence

I am designing a D flip-flop. While doing my pre-layout simulations, I wasn't getting the output Q for the inputs, see attachments. But when I tried to take the output from CLKPULSE, I was getting ...
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2 answers
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Transmitting an RS232 Signal over Wireless/RF. Can this be achieved? [closed]

I have an idea I am trying to implement and I want to know if this is possible and feasible. I have a Barcode Scanner device that gets connected to a PC with a DB9 COM port. Using this connection and ...
4 votes
2 answers
117 views

How can you block the parasitic body diode in digital CMOS I/O IC design?

I've been screwing around with IBIS models lately and came across something that left me scratching my head. First, the generic model structure for the semiconductor portions of an IBIS I/O looks ...
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5 answers
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Push-pull output stage doesn't reach input voltage

I tried to simulate a push-pull output stage in this configuration: Here with the closed switch: As you can see, the output voltage is very low. I expected 3.3 V and 250 mA at the output. Shouldn't ...
3 votes
1 answer
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What causes these peaks in the output voltage of a CMOS inverter?

The figure is taken from https://ece.uwaterloo.ca/~mhanis/ece637/lecture7.pdf There is no significant inductive element in a CMOS inverter, so what is the cause of these peaks while switching?
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2 answers
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Current Conveyor CCII internal circuital realization

I have read this article about current conveyor CCII, and I have some problems about understanding its circuital realization (page 4): simulate this circuit – Schematic created using CircuitLab ...
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Miller effect in MOSFET

I have few question related to Miller effect in cmos. What does rate of change of Vgd (across Cgd) or Vd (drain point) depend on, when the transistor turns on? When transistor is on, it will get into ...
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Are there any ways to increasing the gain and ICMRs to this opamp?

Here's the netlist of this CMOS opamp schematics. ...
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Transistor fingering reducing gate resistance

In the transistor fingering diagram (b) below, shouldn't the two transistor fingers be connected at the right side as well in order for the fingers to actually appear in parallel? As it is right now ...
1 vote
1 answer
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What are the output logic levels of this STM32?

I am struggling getting my head around the input and output logic levels, mostly the output levels of this STM32 (STM32F446xC/E). This table shows the output logic levels as dependent on if it is a ...
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2 answers
948 views

Depletion mosfet inverter

I know that if both transistor in a cmos inverter are enhancement then the output will be as shown in the figure: But I wonder, what if one of them is enhancement and the other is Depletion?
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Using transistors to boost MOSFET gate voltage alternatives [closed]

I'm working with a micro controller based on CMOS logic. So I want to drive a load that is connected to the P-MOSFET low side. To make sure that the gate is fully saturated, I want to boost the 5 V to ...
1 vote
1 answer
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Problem on biasing of the differential folded cascode with ideal and non-ideal CMFB

For this circuit, a PMOS input stage folded cascode amplifier as a gain booster, I have two questions. The PMOSs (Mppp1 to Mppp4) in the cascode banches are in strong-inversion saturation while the ...
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1 answer
163 views

Combining CMOS and TTL with drivers and Leds with relay driver

I need some practical advice on how to combine different component types. I designed a circuit with at the heart an up/down counter (74f269) The outputs of the counter are connect to via 330 ohm ...
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1 answer
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Interfacing LM3914 to CMOS logic circuitry

I built the ubiquitous battery voltage monitor using the equally ubuiqutous LM3914. It monitors a 12V battery and controls a charger. The datasheet mentions the IC can interface with TTL or CMOS logic,...
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1 answer
633 views

Minimum number of transistors to implement CMOS logic of this function

I have designed the following circuit to implement CMOS logic of: \$\text{out}=\overline{(a+b).\overline{c}+e.(\overline{f}+\overline{g})}\$ I’m looking for the optimal circuit with the minimum number ...
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2 answers
482 views

Dual edge triggered D flip flip CMOS implementation. Less than 20 transistors

I need to implement a dual edge triggered D flip flop (DET) in a CMOS IC using 0.35u technology. The best design which I could find is this one. I attached the circuit to this post also. First ...
1 vote
1 answer
74 views

Cascode: Which device goes into triode region first?

In the above cascode network, which device goes into triode region first, if the supply gradually decreases? Framing the question other way round, if the supply gradually increases from 0V, which ...
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I want to Implement this active inductor design in my circuit

I'm trying to use the active inductor in here instead of the inductor in my class e power amplifier, however I'm having difficulties in getting the required values for the parameters in here Cds, Cgs, ...
2 votes
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494 views

Cross coupled-gm boosting stage

From this paper, a wideband differential LNA is proposed with structure below: The first stage is called "cross coupled- gm boosting stage". I am wondering if there is a mistake here. As ...
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2 answers
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Could we use holes in an NMOS?

In an NMOS we have a p-substrate, and we use a positive voltage to attract negative charge "to the top". But could we have used negative charge to attract holes instead and gotten a "...
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1 answer
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Why is gate fanout calculated like that for general gate?

In the given example I am currently struggling to understand why the fanout of each gate is equal to the ratio of the size of this gate to the previous gate. In a simple chain of inverters, the fan ...
2 votes
1 answer
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Can someone explain how I can avoid voltage spikes in this graph?

I’m trying to implement this boolean function using CMOS transmission gate in LTspice. F = AB + A'C' + AB'C I've used two symbols in my project: Transmission gate symbol schematic: 180nm CMOS ...
2 votes
2 answers
414 views

plot the max slopes of Voltage-Transfer characteristics in ngspice

I have implemented a basic CMOS inverter in ngspice, performing a DC sweep analysis on the input voltage to obtain the Voltage Transfer Curves (Vout vs Vin) at varying Vdd voltages. ...
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This SR latch built with 180nm CMOS does not work in ltspice. How do I fix its behavior and parameters?

EDIT: I copied over the latch from another larger model that had Vdd defined, but missed it when copying over the design. However, after adding in Vdd, I still run into this confusing issue where the ...
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1 answer
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Finding the gain expression for this CMOS operational transconductance amplifier

So here's the circuit: I think M2 is a common source amplifier and M4 a common gate amplifier, so they form a cascode amplifier where the gain is given by : Av = -gm2 * r0, r0 is the impedance at the ...
4 votes
1 answer
546 views

Subthreshold Transconductance Amplifier

As part of a broader project, I am designing IC circuit using CMOS to one of the first steps I'm working on is the filtering a series of pulses with of the noise. The actual pulses are around 1 kHz so ...
2 votes
4 answers
266 views

How do processor transistor counts keep increasing, without geometric scaling?

Reading into the history of the semiconductor industry and Moore's Law, and looking at the ITRS/IRDS documents, I understand that scaling down and modern node names (7nm, 5nm etc) are now "...
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What is the resulting Voltage Transfer characteristics of the modified CMOS-inverter circuit if NMOS and PMOS are interchanged?

What is the resulting Voltage Transfer characteristics of the modified CMOS-inverter circuit, if the positions of \$NMOS\$ and \$PMOS\$ are interchanged?
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CMOS IC Dynamic Edge-Triggered Flip Flop setup and hold time calculation

Before explaining i should point out that i refer to changes of signals in the text as a reference change on which i will calculate these times as 50% change of one signal to 50% change of the other ...
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3 answers
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How to simulate digital logic using CMOS technology (MOSFET) in Proteus?

Hello I'm having trouble with Proteus to do this CMOS logic simulation, I used transistors, I can do the logic perfectly, but when I use CMOS for some reason the logic doesn't work. I used the methods ...
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2 answers
425 views

74AS TTL to CMOS pull up resistor and maximum speed (or lowest delay)

Hello I have to pilot a CMOS input 5V chip device with a 7474 flip flop with the lowest possible delay to minimize clock jitter. Signal is about 11.3 Mhz I have two options: 1) 74HC74 (CMOS ...
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How does the CMOS Schmitt trigger work

I have some questions on how the schmitt trigger works. Assuming we start with low Vin hence Vout is high. It means that M1 is ON thus the source of M2 is conducting Vdd hence M2 is On as well. ...
16 votes
8 answers
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Why does switching cause power dissipation?

I know that switching logic values causes power dissipation but I could never understand why. Is it because transistors need to be turned on each time we want to charge/pull up a node and discharge/...
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1 answer
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Setting multi-fingers in MOSFET in series configuration in Cadence Virtuoso schematic

I am trying to figure out to set multi-fingers (nf = 3) for MOSFET (both P-MOS and N-MOS.) I know I can increase the length directly. As connecting MOSFETs in series increases length, can I somehow ...
2 votes
1 answer
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Purpose of field implant in semiconductor manufacturing

I recently joined the semiconductor manufacturing industry. In one of the process flows, I see a stage that has extra boron implantation step (called the field implant) in the P-WELL region. I've ...
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2 answers
209 views

PSPICE simulation

I have a PSPICE file that contains approximately 200+ transistors. Naturally, simulating the whole circuit everytime I make a change takes a while. Is there anyway to run a simulation measuring only ...
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1 answer
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What is the maximum number of inputs to a logic gate that is being used in computing hardware these days?

I was referring to this question, but I had a confusion due to the concept of programmable logic devices. Image from UW page 7. Here the OR section can have up to 8 inputs to it. I'm confused about ...
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Figure of Merit for sizing P-MOS and N-MOS in Inverter circuit

I am trying to design a basic circuit block of inverter (Analog circuit) in Cadence Virtuoso schematic in 22nm technology. It will be used for non-overlapping clock generator. I need to size the P-MOS ...
3 votes
1 answer
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What exactly do the well taps in MOSFETs do and how?

Do they affect the flow of charge carriers or charge concentrations at all in the device? How so? Up to this point I've tried to visualize the effects that the various doped areas had on device ...
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1 answer
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How to send to pulses to a CMOS Counter

I have tried to find answers to this many times, and the only solution I have been able to find is having two 555 Timers (or a 556) one in astable, and one in monostable. I could easily do this with ...
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369 views

Effects of input capacitance on propagation delay (with Logical Effort analysis)

Let's consider the logical effort methodology for the propagation delay's computation. Here there are some informations (https://en.wikipedia.org/wiki/Logical_effort). Let's consider a generic CMOS ...

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