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Questions tagged [cmos]

"Complementary Metal-Oxide Semiconductor" is a process which implements a combination of PMOS and NMOS transistors. Most current digital logic is implemented in CMOS. Its cost-effectiveness due to being so widespread means many other applications have become common as well, such as in analog design, image sensors, telecommunication, etc.

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Probing with oscilloscope causes current drop

We are testing a fabricated chip with expected output current of around 4mA which is then used to charge a button cell. The input is from a PV cell. However, when we attach an oscilloscope probe onto ...
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2k views

NMOS: why VGS instead of VG?

I am having lots of trouble trying to understand how the mosfet is triggered. The text I read assumes the source of the NMOS connect to ground, while a positive voltage is applied at the gate. ...
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52 views

MOSFET switching on

I have a doubt. Consider an N-MOSFET: which is the voltage that can switch on it? The voltage between Gate and? Sometimes I read "between Gate and Bulk", sometimes "between Gate and Source", sometimes ...
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183 views

Differential Amplifier with Hard Limiting

I'm currently going through RF Microelectronics by Razavi. In chapter 3 he presents an example where the following signal is applied to a differential amplifier with a tail current source. $$Acos(...
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107 views

Detect Infrared beam projected onto X-Y plane. Save and display coordinates. CMOS sensor?

I'm working on a project in which an IR laser is pointed perpendicular to the surface of an X-Y plane (Think like the old game "Duck Hunt"). I don't know where the IR beam will land on the plane but ...
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445 views

D FLIP FLOP Cadence

Basically I am designing D flip flop. While doing my pre-layout simulations, not getting the output Q for the inputs. See the attached attachments. But when I tried to take the output from CLKPULSE, ...
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1k views

Can I create a CMOS AND gate with 2 serial n-type and 2 paralel p-type CMOS transistors?

So I know that a CMOS AND gate is made with 2 parallel p-type transistors and 2 serial n-type transistors and an inverter on the output. But can we just make the AND gate similar to the NOR gate -...
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8k views

Measure the leakage current of a CMOS inverter

I would like to measure the leakage current of a CMOS inverter. As this current depends on the input, I decided to measure something average, namely, the leakage current of a ring with two CMOS ...
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353 views

Depletion mosfet inverter

I know that if both transistor in a cmos inverter are enhancement then the output will be as shown in the figure: But I wonder, what if one of them is enhancement and the other is Depletion?
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1k views

normalized parasitic delay

I am confused why many books and sites call normalized parasitic delay as " ratio of diffusion capacitance to gate capacitance in a particular process" . According to me its delay of gate when it ...
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1answer
45 views

Finding transistor width for equal rise and fall times

I am trying to understand how the below CMOS transistor schematic has approximate equal rise and fall times (resistance pull up equal to resistance pull down) Below is the schematic: I notice that ...
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427 views

Design CMOS comparator

I made the circuit. like this paper, But It's not working. When you insert the AC input, a square waveform should appear. I can not interpret the circuit well. If you know anything, please answer ...
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220 views

Inversion Coefficient Based Design in CMOS amplifiers

I have designed amplifiers, using potential division method. What are the steps to design differential amplifier using inversion coefficient based design methodology? Please provide links/...
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23 views

CMOS IC Dynamic Edge-Triggered Flip Flop setup and hold time calculation

Before explaining i should point out that i refer to changes of signals in the text as a reference change on which i will calculate these times as 50% change of one signal to 50% change of the other ...
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69 views

opamp constant-gm bias circuit

I try to incorporate the constant-gm bias circuit (Figure 6 in Improvements_in_biasing_and_compensation_of_CMOS_opamp) into the PFC (positive feedback frequency compensation) opamp, but it resulted in ...
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22 views

Can the scanning speed of an electronic rolling shutter CMOS sensor be controlled?

I'm not certain I'm asking this correctly as I don't entirely understand how such a camera sensor works, so help me out with a couple of areas please! I want to program something that makes use of ...
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32 views

CMOS switch with “negative” current

In a project, I need to swap the polarity of a 12V power/signal and GND wire combination electronically. The current flow is between 7 and 28 mA. I'm using a DPDT relay for this - the input wires are ...
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2answers
77 views

CMOS Inverter Circuit Analysis

So I have a circuit shown below, that looks to me likes it's a CMOS inverter circuit. In this question, we're asked to find the current and voltage across drain-source voltage of the NMOS component. ...
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290 views

How does a “bulk connected to input voltage” mos work?

This is the circuit I am supposed to analyze, but I don't understand at transistor level, what does a MOS do when its gate is grounded and its bulk is the input terminal! I mean bulk is tied to Vdd or ...
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1answer
45 views

What is the effect on propagation delay when we have a CMOS circuit with multiple transistors connected in series?

How does the fact that in a series connection of two or more transistors only one is connected directly to gnd (in case of nmos transistors) or vdd (in case of pmos transistors) effect the change of ...
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1answer
111 views

Monostable multivibrator problem

As you see in the picture above, diode voltage drop is 0V, and the monostable multivibrator is made in CMOS technology with protection diodes. I have problem finding the output of this circuit in some ...
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2answers
176 views

Shot or thermal noise of a MOS transistor

I'm trying to compare the shot and thermal noise contributions in a MOS transistor. In the literature, the above-threshold MOS transistor has only thermal noise, which is found by integrating the ...
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2answers
48 views

Single Stage Amplifier CMOS - Biasing Issues

So this is kind of vague question. I'm wondering what the approach to biasing MOSFETs in saturation is. For the following circuit, I really have no specifications - I'm just trying to play around ...
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77 views

74AS TTL to CMOS pull up resistor and maximum speed (or lowest delay)

Hello I have to pilot a CMOS input 5V chip device with a 7474 flip flop with the lowest possible delay to minimize clock jitter. Signal is about 11.3 Mhz I have two options: 1) 74HC74 (CMOS ...
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1answer
3k views

CMOS implementation of D flip-flop

I am trying to implement edge triggered flip-flop using CMOS logic. Google search provides following diagram on wikipedia: Upon simulating this using tanner, I find out that output resembles positive ...
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1answer
51 views

This SR latch built with 180nm CMOS does not work in ltspice. How do I fix its behavior and parameters?

EDIT: I copied over the latch from another larger model that had Vdd defined, but missed it when copying over the design. However, after adding in Vdd, I still run into this confusing issue where the ...
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187 views

what logic family does tri state logic fall into?

Here is a good Wikipedia on logic families. This seemed like a particularly important line. Of these families, only ECL, TTL, NMOS, CMOS, and BiCMOS are currently still in widespread use. I'...
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100 views

LTSPICE Simple MOS-FET Stacked Current Mirror/Cascode saturation threshold less than expected

I am running a few very rudimentary cmos circuits in LTSPICE. For some reason, when designing stacked mirrors, I seem to get a much lower saturation turn on thresholds would be expected. I've tried ...
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107 views

What are the advantages of CMOS operational amplifiers vs bipolar in the same class?

Is there something else than Rail-to-Rail output and possibly lower power consumption for low frequency applications? Or Rail-to-Rail is the main one?
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When is it reasonable to ignore channel length modulation in MOSFETs?

It is known that for smaller technologies, the channel length modulation effect is more prominent. However, is there any condition (biasing,voltage levels, transistor sizing ..etc) from which we can ...
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1answer
124 views

How can I have an ECL logic input for a CMOS logic gate

I'm working on a triggering system that uses a comparator to check if the signal is below a threshold value. I found a great comparator for the job, except its output is ECL logic. I wanted to use the ...
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1answer
65 views

Using NMOS or PMOS for voltage controlled switch?

If I want to use an NMOS or PMOS as a voltage controlled switch, when would I know to use one over the other? I know a PMOS activates with a LOW at the gate and for an NMOS when HIGH at the gate, but ...
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44 views

Performance issues when using CMOS SR Latch with 180nm transistor models in circuit simulator

I am trying to incorporate a CMOS SR latch made with 180nm Level +49 transistors into a larger circuit but am running into issues. I am hoping this community can point me in the right direction of ...
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Emitter-coupled logic operation

For the operation of emitter-coupled logic and sedra smith book, 1) Compared to CMOS, why ECL is the faster logic family given that it requires so many transistors to propagate to output Y (T5 ...
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118 views

CMOS source follower with 2 in series

I am really struggling with where to start to analyse this. Using the Shichman Hodges Model and the small signal equivalent circuit, the voltage gain can be equation can be seen to be vo = -gmvgsr0. ...
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leakage power with respect to Switching activity

Can anyone explain me relation of leakage current or power with respect to Switching activity(S.A). I'm assuming that with increase of S.A, the power dissipation of circuit increases in-turn ...
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3answers
79 views

P-MOSFET failures

simulate this circuit – Schematic created using CircuitLab P-Mosfet Datasheet The goal is that 5V (or logic high) appears on U3 when there is logic low on U4 and logic high on U2. That 0V (or ...
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146 views

NRST pin of unpowered STLINK V2

I am using the STLINK from a Nucleo board in order to flash and debug a STM32F7 MCU on a custom board. Everything works fine except when STLINK is connected to my custom board AND unpowered. Indeed, ...
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63 views

STM32F407 CMOS or TTL or HC

I wonder which logic technology is STM32F407 MCU based on.. CMOS or TTL or HC or LVT etc? Although its mentioned in the datasheet that the GPIO's are CMOS and TTL compliant. I am concerned about this ...
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Drain capacitance of CMOS inverter

How to find the total drain( NMOS+PMOS) capacitance of CMOS inverter in cadence virtuoso?
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181 views

How could I put an Enable pin on a standard two-stage CMOS op-amp?

I need to design an LDO regulator that only sources supply voltage and current to the load whenever it receives a logic-1 signal. Since the main element used in the LDO regulator is a differential ...
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113 views

Are source and drain terminals of Access Transistors in 6T SRAM interchangeable?

My textbook understanding is that the source terminals (S) of the access transistors in a 6T SRAM cell are to be connected to the bit lines (BL/BLB) while the drain terminals (D) to the storage nodes (...
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38 views

CMOS Inverter output for a given transfer characteristics

I have tried solving the below CMOS problem with a given transfer characteristics but my answer is wrong. Answer should be 0.25. Could someone please point out where I went wrong ?
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137 views

Practical ESD protection without latchup

My understanding has always been that any CMOS I/O pin needs external ESD protection - since the on-chip protection diodes are only there to guard against ESD events during manufacture handling. ...
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3answers
82 views

74HC4060 lower frequency limit

I need to sequence some micropower (low-microamp range) logic at a once-per-several-minute rate, and am falling back on the good ol' 4060 as my timebase (plus a 138 and a 534 for the sequencing). I ...
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1answer
139 views

Arduino/Mosfet control of CMOS logic chip

So I've found a basic composite video "synth" which I'm trying to manipulate with an arduino. The device was originally controlled by NO tact switches between pins on the CMOS MCU, a Signetics ...
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1answer
60 views

Possibility to change IC HCF4060BE to IC 74HC4060

I recently purchased a very old synthesizer that uses CI HCF4060BE and I want to know if it is the memso that CI 74HC4060. To help here is the CI datasheet HCF4060BE: LINK Here the dataset of the CI ...
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2answers
122 views

What is the point of 2 inverters in series? [duplicate]

In the datasheet for the Nexperia HEF4543B, in the logic diagram, there are 2 inverters in series: What is the point of these inverters in series?
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Help Identifying a CMOS optical mouse sensor?

I'm working to repurpose the trackball assembly of a Logitech Trackman wired mouse for use in an experimental rig. I assumed that Logitech would use Avago's ADNS series of optical flow sensors, but it ...
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2k views

Significance of -1 slope in CMOS inverter transfer characteristics

In the CMOS inverter transfer characteristics what is the significance of slope of \$-1\$ at the points where \$V_{IH}\$ and \$V_{IL}\$ have been shown? And how is this the occurrence of the values, \$...