Questions tagged [cmos]

"Complementary Metal-Oxide Semiconductor" is a process which implements a combination of PMOS and NMOS transistors. Most current digital logic is implemented in CMOS. Its cost-effectiveness due to being so widespread means many other applications have become common as well, such as in analog design, image sensors, telecommunication, etc.

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27 views

Power consumption in voltage detector

I am quite new in embedded system and circuit design. I have designed a system in which I have to add voltage detectors. I need to find the accurate power that the detector can consume in each cycle ...
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Determining Rs Value for 32kHz Crystal Oscillator Circuit

I'm building a Pierce-Gate oscillator circuit using a 74HC4060 and a 32kHz 12.5pF watch crystal. I'm a novice, but AFAICT the oscillator circuit of the SN74HC4060 is just a buffered CMOS inverter: ...
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CMOS Inverter Circuit Analysis

So I have a circuit shown below, that looks to me likes it's a CMOS inverter circuit. In this question, we're asked to find the current and voltage across drain-source voltage of the NMOS component. ...
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Fundamental CMOS astable multivibrator

So i need to perform analysis of simple astable multivibrator circuit shown in the following picture: These Vdd and GND are just the power rails of those CMOS inverters. Now, i need to perform ...
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Obtaining D flip-flop mosfet-level schematics from CMOS layout

Could anyone help to derive D flip-flop mosfet-level schematics from the following CMOS layout described in this conference document : Open Cell Library in 15nm FreePDK Technology ?
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current consumption of hall sensors and AND gates?

How do we calculate the current consumption of devices like Hall sensors and CMOS gates (for example: sensors like ACS725 and AND gate like MC74VHC1G08)?
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Does this circuit have marginal voltage level problem?

As a research for the problem I described here I found this circuit by Maxim: This is clock doubler, and must be a really good fit in my case as input frequency is very well defined. However looking ...
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133 views

How can I have an ECL logic input for a CMOS logic gate

I'm working on a triggering system that uses a comparator to check if the signal is below a threshold value. I found a great comparator for the job, except its output is ECL logic. I wanted to use the ...
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Why does cmos inverter consume power while discharging load capacitance?

Consider a simple CMOS inverter. To calculate the switching power dissipation, we consider the case when capacitor is charged till by pmos as the current is drained from Vdd. But when it is being ...
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153 views

Practical ESD protection without latchup

My understanding has always been that any CMOS I/O pin needs external ESD protection - since the on-chip protection diodes are only there to guard against ESD events during manufacture handling. ...
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217 views

How could I put an Enable pin on a standard two-stage CMOS op-amp?

I need to design an LDO regulator that only sources supply voltage and current to the load whenever it receives a logic-1 signal. Since the main element used in the LDO regulator is a differential ...
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128 views

CMOS source follower with 2 in series

I am really struggling with where to start to analyse this. Using the Shichman Hodges Model and the small signal equivalent circuit, the voltage gain can be equation can be seen to be vo = -gmvgsr0. ...
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Uncertainty(jitter) in setup and hold calculation

In setup calculation, the launch flop is triggered by 1st edge and capture flop is triggered by next edge. And in calculation we take jitter into account only for the clock path of capture flop. There ...
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Contact on substrate of a MOSFET

Why do we want to have an ohmic contact on a substrate terminal of mosfet? What would happen if we used schottky contact instead?
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Mos circuit amplifier with multiple stages , overall gain

I have the following circuit and i am trying to find uin/vout. My thought process is that M3-M4 is a Cmos inverter so i can calculate the gain until that point as A1= -gm3(ro3//ro5) How can i find the ...
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210 views

what logic family does tri state logic fall into?

Here is a good Wikipedia on logic families. This seemed like a particularly important line. Of these families, only ECL, TTL, NMOS, CMOS, and BiCMOS are currently still in widespread use. I'...
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MOSFET switching on

I have a doubt. Consider an N-MOSFET: which is the voltage that can switch on it? The voltage between Gate and? Sometimes I read "between Gate and Bulk", sometimes "between Gate and Source", sometimes ...
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Cmos vtc characteristics

Why does the vin=vout takes place at the voltage of (vdd/2) only in the case cmos inverter characteristics? and how to estimate the value of (vout) in every case, so that we can establish ...
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149 views

Arduino/Mosfet control of CMOS logic chip

So I've found a basic composite video "synth" which I'm trying to manipulate with an arduino. The device was originally controlled by NO tact switches between pins on the CMOS MCU, a Signetics ...
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25 views

Is a DMOS potential free? (in case of TPIC6C596)

I've been looking at the Datasheet of the TPIC6C596 and I'm not sure if the DMOS that is mentioned in the package can be used as a potential free. I also don't know in general if a DMOS can be used ...
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34 views

Setup and hold in flipflops

Usually the data launched at 1st clock edge will be captured at 2nd clock edge. But Is it possible to launch at 1st edge and capture data in same clock edge? The clock to capture flip flop is delayed ...
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What is propagation delay in cmos nets?

I have read somewhere that signal travels as electromagnetic waves in wires near to speed of light. The signals are brought to destination by EM waves. Then what does electrons do? If signals travel ...
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Why propagation delay is measured at 50% of the input and output waveform?

I didn't find the concept of propagation delay measured at a particular point on the waveform.
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Which input of NAND is preferred and why? [duplicate]

Let A and B be two inputs of the NAND gate. Say input A arrives at the NAND gate later than input B. To optimize delay of the two series NMOS inputs A and B which one would you place near to the ...
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313 views

Why not switching extra inverters with opposite MOSFETs in CMOS XOR gate?

Below you can see a CMOS XOR gate. I wonder why we do not change extra inverters like A' or B' with opposite MOSFETs. For example, could not we just put the green construction in the place of red ...
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Frequency Divider Analog Circuit issue

I am trying to implement a divide-by-two circuit quoted from the book "Low power CMOS circuits : technology logic design and CAD tools" by Christian Piguet Could anyone advise about the spice error "...
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simple six-position voting machine into a 7 position voting machine

I'm new to learning about full and half adders and what not. but I am struggling to understand this question out of my study manual. The pictures shows a simple six-position voting machine module ...
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Why does the current in MOSFET have a quadratic function (explain logically without using the integration method)?

The current equation relating Vds ,Vgs and Vt is already known to us ,but if there is any way we can find out how it varies quadratically without using the formulae?
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Probing with oscilloscope causes current drop

We are testing a fabricated chip with expected output current of around 4mA which is then used to charge a button cell. The input is from a PV cell. However, when we attach an oscilloscope probe onto ...
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NMOS: why VGS instead of VG?

I am having lots of trouble trying to understand how the mosfet is triggered. The text I read assumes the source of the NMOS connect to ground, while a positive voltage is applied at the gate. ...
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195 views

Differential Amplifier with Hard Limiting

I'm currently going through RF Microelectronics by Razavi. In chapter 3 he presents an example where the following signal is applied to a differential amplifier with a tail current source. $$Acos(...
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Detect Infrared beam projected onto X-Y plane. Save and display coordinates. CMOS sensor?

I'm working on a project in which an IR laser is pointed perpendicular to the surface of an X-Y plane (Think like the old game "Duck Hunt"). I don't know where the IR beam will land on the plane but ...
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484 views

D FLIP FLOP Cadence

Basically I am designing D flip flop. While doing my pre-layout simulations, not getting the output Q for the inputs. See the attached attachments. But when I tried to take the output from CLKPULSE, ...
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Can I create a CMOS AND gate with 2 serial n-type and 2 paralel p-type CMOS transistors?

So I know that a CMOS AND gate is made with 2 parallel p-type transistors and 2 serial n-type transistors and an inverter on the output. But can we just make the AND gate similar to the NOR gate -...
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Measure the leakage current of a CMOS inverter

I would like to measure the leakage current of a CMOS inverter. As this current depends on the input, I decided to measure something average, namely, the leakage current of a ring with two CMOS ...
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379 views

Depletion mosfet inverter

I know that if both transistor in a cmos inverter are enhancement then the output will be as shown in the figure: But I wonder, what if one of them is enhancement and the other is Depletion?
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normalized parasitic delay

I am confused why many books and sites call normalized parasitic delay as " ratio of diffusion capacitance to gate capacitance in a particular process" . According to me its delay of gate when it ...
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Finding transistor width for equal rise and fall times

I am trying to understand how the below CMOS transistor schematic has approximate equal rise and fall times (resistance pull up equal to resistance pull down) Below is the schematic: I notice that ...
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441 views

Design CMOS comparator

I made the circuit. like this paper, But It's not working. When you insert the AC input, a square waveform should appear. I can not interpret the circuit well. If you know anything, please answer ...
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224 views

Inversion Coefficient Based Design in CMOS amplifiers

I have designed amplifiers, using potential division method. What are the steps to design differential amplifier using inversion coefficient based design methodology? Please provide links/...
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CMOS IC Dynamic Edge-Triggered Flip Flop setup and hold time calculation

Before explaining i should point out that i refer to changes of signals in the text as a reference change on which i will calculate these times as 50% change of one signal to 50% change of the other ...
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opamp constant-gm bias circuit

I try to incorporate the constant-gm bias circuit (Figure 6 in Improvements_in_biasing_and_compensation_of_CMOS_opamp) into the PFC (positive feedback frequency compensation) opamp, but it resulted in ...
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Can the scanning speed of an electronic rolling shutter CMOS sensor be controlled?

I'm not certain I'm asking this correctly as I don't entirely understand how such a camera sensor works, so help me out with a couple of areas please! I want to program something that makes use of ...
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CMOS switch with “negative” current

In a project, I need to swap the polarity of a 12V power/signal and GND wire combination electronically. The current flow is between 7 and 28 mA. I'm using a DPDT relay for this - the input wires are ...
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305 views

How does a “bulk connected to input voltage” mos work?

This is the circuit I am supposed to analyze, but I don't understand at transistor level, what does a MOS do when its gate is grounded and its bulk is the input terminal! I mean bulk is tied to Vdd or ...
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What is the effect on propagation delay when we have a CMOS circuit with multiple transistors connected in series?

How does the fact that in a series connection of two or more transistors only one is connected directly to gnd (in case of nmos transistors) or vdd (in case of pmos transistors) effect the change of ...
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Monostable multivibrator problem

As you see in the picture above, diode voltage drop is 0V, and the monostable multivibrator is made in CMOS technology with protection diodes. I have problem finding the output of this circuit in some ...
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Shot or thermal noise of a MOS transistor

I'm trying to compare the shot and thermal noise contributions in a MOS transistor. In the literature, the above-threshold MOS transistor has only thermal noise, which is found by integrating the ...
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Single Stage Amplifier CMOS - Biasing Issues

So this is kind of vague question. I'm wondering what the approach to biasing MOSFETs in saturation is. For the following circuit, I really have no specifications - I'm just trying to play around ...
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74AS TTL to CMOS pull up resistor and maximum speed (or lowest delay)

Hello I have to pilot a CMOS input 5V chip device with a 7474 flip flop with the lowest possible delay to minimize clock jitter. Signal is about 11.3 Mhz I have two options: 1) 74HC74 (CMOS ...