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Questions tagged [cmos]

"Complementary Metal-Oxide Semiconductor" is a process which implements a combination of PMOS and NMOS transistors. Most current digital logic is implemented in CMOS. Its cost-effectiveness due to being so widespread means many other applications have become common as well, such as in analog design, image sensors, telecommunication, etc.

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Question about mosfet gate resistor

I have n mosfet gate connected to 4043 logic and Id is about 100mA. Both 4043 and mosfet has +5v. I have plan to use 2N7000 mosfet Questions are: How large gate resistor i need between 4043 and ...
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2answers
21k views

“Tristate a pin”

What does it mean to "tristate a pin" on a CMOS microcontroller?
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7answers
90k views

Voltage at what Amperage

I've often seen devices with power requirements specified only in Volts (e.g. 7-12V) but never the amperage. I've wanted to run various embedded devices of wall warts and batteries (the devices have ...
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6answers
9k views

Power consumed by a CPU

I think the power for a CPU with current I and voltage U is I · U. I wonder how the following conclusion from Wikipedia is derived? The power consumed by a CPU, is approximately ...
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3answers
8k views

Using CMOS Schmitt trigger inverters in quartz crystal oscillator circuit

In all sources I've seen about quartz crystal oscillators using CMOS inverters there's a note like this: But why Schmitt inverter is needed? Won't classic 74HC04 work?
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3answers
1k views

Do I need to duplicate the 4th “substrate” connection when building CMOS gates out of discrete transistors?

All CMOS digital integrated circuits I've ever seen connect all the nFET substrates together to GND. In particular, the IC CMOS NAND gate has one nFET that has its substrate connected to GND, but its ...
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1answer
1k views

Precise differences between DRAM and CMOS processes

There are a couple of questions that mention the difference between standard CMOS processes and DRAM manufacture: Why do microcontrollers have so little RAM? How do they integrate logic into a DRAM ...
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1answer
487 views

measurement of output impedance of a CMOS inverter

I am measuring output impedance of CMOS inverter using ngspice. No matter how I measure the output impedance, the result can never come any close to the following theoretical calculation if I reduce ...
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3answers
10k views

How are CPUs designed?

I've started playing with electronics a while ago and making simple logic gates using transistors. I know modern integrated circuits use CMOS instead of transistor-transistor logic. The thing I can't ...
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5answers
2k views

In theory, is it possible to make a logic gate that uses zero current?

CMOS greatly reduces the current draw of ICs because one of the complementary FETs is always in the non-conducting mode, so there is only a flow of current during the transition between states, which ...
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7answers
27k views

What' so great about CMOS?

I've read lot of topics here. I read some people saying I prefer to "have CMOS characteristics" & so on , also in some data sheets (like AVR), they say it have CMOS characteristics, etc... I ...
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5answers
579 views

How necessary is ESD protection, really?

I'm not asking about manufacturing. I'm asking about designing electronics to survive normal use in the field. I want to figure out just how necessary it is to include TVS diodes in my design. As I ...
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1answer
30k views

Q-Point of a circuit

In a BJT or MOSFET circuit we have this curve: What is that q-point? From my research I have the following information: The operating point of a device, also known as bias point or quiescent point ...
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2answers
2k views

CMOS vs TTL Logic Gates?

This is probably a simple question but how come CMOS Logic Gates built from Only Transistors is completely different from one that uses TTL Logic (Like BJT's). I know BJT aren't really used anymore ...
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1answer
433 views

Random clock Generation with unequal 1s and 0s distribution?

We need a pseudo-random clock with a length N, in such a way that out of every N clock pulses, ...
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2answers
2k views

Why is a capacitor used to protect CMOS chips? [duplicate]

I am studying digital electronics. A book says that "use a 0.1 μF capacitor between Vcc and ground for each IC". What does this mean? Why can a capacitor protect CMOS chips? Does it mean that a ...
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2answers
2k views

CMOS (or CMOS compatible) shift register with latched open-drain outputs

I've been looking for a 3.3V compatible shift register (SIPO) with latched open-drain outputs. I've settled on a 74xx596 (not a '595!), but of all the 74xx CMOS series I've been looking at omit this ...
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3answers
8k views

Simplifying CMOS schematic to reduce number of transistors

I know the basics in creating a schematic in CMOS, wherein in a(n inverted) boolean expression, if there is a: NOR - NMOS should be in parallel, PMOS in series; NAND - NMOS in series, PMOS in ...
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1answer
8k views

Measure the leakage current of a CMOS inverter

I would like to measure the leakage current of a CMOS inverter. As this current depends on the input, I decided to measure something average, namely, the leakage current of a ring with two CMOS ...
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3answers
477 views

Will this circuit suffer from Shoot-Through? and is there a quick fix?

I'm considering a high-side, low-side driver using the DMG1016UDW COMPLEMENTARY PAIR ENHANCEMENT MODE MOSFET from diodes. The datasheet says The ON voltage is about 0.5V and ON the delays+rises is ...
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4answers
852 views

Reliability of anti-static packaging

OK, DILs are on the way out, but from time to time you still can see CMOS DILs packaged like this as ESD protection: That's aluminium foil on EPS (expanded polystyrene). The EPS isn't conductive, ...
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3answers
9k views

In IC design, what is the Buffer for ?

In CMOS design, we always use two inverters as a buffer, but at some point, I dont quite understand the functions or importances of the buffer. As I was told before, 1) the buffer could smooth the ...
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3answers
2k views

Understanding CMOS performance and complexity for ASIC : 350nm to 45nm process

I am trying to build an ASIC chip with the help of the MOSIS project. (They make it cheaper by combining multiple small project into a single fab). I have a choice between 350nm to 45nm, and ...
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2answers
1k views

Which logic families interpret a floating input as a definite value?

From what I remember, from decades ago, 1980's 5v TTL chips would see a floating input as a zero (because they switched on current, rather than voltage). Update: it seems they were interpreted as ...
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1answer
2k views

Silicon Controlled Switches: applications&suppliers

I came across this description of what are called "silicon controlled switches." I always look to balance n/p-channel electronics for stability, and using these silicon controlled switches seemed like ...
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2answers
185 views

Does CMOS J/K trigger need pull-up resistor

I want to use J/K trigger and I was told that usually IC outputs need pull-up resistor, but if I understand it correctly the following J/K trigger is based on CMOS: TI J/K trigger And it seems to me ...
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2answers
1k views

Effective transconductance of a CMOS inverter

If we have a CMOS inverter operating in its' linear region, what would be the effective trans conductance of the inverter?
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2answers
135 views

Signal path switching for effect circuits

I'm trying to build a method of switching signal order with three circuits in a rack unit. I've been researching different methods, using relays, using CMOS etc but I'm getting a bit overwhelmed and ...
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3answers
4k views

Circuit to switch about 5W of 12V using CMOS logic inputs using N-channel MOSFET?

I want to switch some 12V landscape light LEDs, totaling about 5 watts, using MOSFETs, with the control signal provided by a digital output line from an Arduino microcontroller running at 5V. I ...
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2answers
288 views

What is the true reason for the rolling shutter effect on modern CMOS camera?

I was wondering what is the true reason for the rolling shutter effect that can be observed on many CMOS camera. I've done some research on the internet and found an excellent article about it: link. ...
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0answers
2k views

Common source circuit with current source and diode connected load

Could anyone explain why the output bias voltage of the common source in figure a is not well defined and needs a common mode feedback while the circuit in figure b is well defined? Here is what I ...
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2answers
122 views

Binary counter and load capacitance

Im desiging a circuit with a binary counter which rates it's maximum count frequency in terms of load capacitance. Im quite confused and having a lot of trouble wrapping my head around how to ...
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2answers
2k views

How do I set the speed of a 4060B chip?

Apologies if this is a bit simple, but I'm new to this! How do I set the speed for a 4060B chip? I want it to trigger every 5 minutes (fairly accurately). I've looked at the instructions here: http:/...
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1answer
90 views

Correct configuration for CMOS inverter

I need to get 4 outputs from a 5V digital output as follows: 2 of them inverted and 2 of them non-inverted. I thought about using a 74 HCT 04 hex inverter in the following configuration: simulate ...
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1answer
139 views

Non-trivial logic function to CMOS schematic

I wanted to implement the function: $$Y = \neg (A \land (B \lor C))$$ This is what I came up with, it looks correct to me but I would like a second opinion on that. simulate this circuit – ...
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2answers
3k views

CMOS OR gate using 4 Transistors

Can an OR gate be implemented using 4 CMOS transistors? The circuit would have two n-type transistors in parallel in the pull-up network, and two p-type transistors in series for the pull-down network....