Questions tagged [cmos]

"Complementary Metal-Oxide Semiconductor" is a process which implements a combination of PMOS and NMOS transistors. Most current digital logic is implemented in CMOS. Its cost-effectiveness due to being so widespread means many other applications have become common as well, such as in analog design, image sensors, telecommunication, etc.

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51 views

MOSFET treshold voltage

Does anyone know how MOS treshold voltage varies if the physical distance between source and drain decreases ?
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Shot or thermal noise of a MOS transistor

I'm trying to compare the shot and thermal noise contributions in a MOS transistor. In the literature, the above-threshold MOS transistor has only thermal noise, which is found by integrating the ...
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62 views

zero AC gain of CMOS inverter

Why is the following AC analysis of CMOS inverter resulted in zero AC gain (vout/vin) ?
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68 views

Current to Voltage Converter in CMOS [closed]

If I want to use a 2-stage opamp for the current to voltage converter application, How should I check for the stability of the circuit? Will it need any kind of stability correction? An uncompensated ...
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Why is it not sensible to connect many (MOS) transistors in series?

For example a NAND-gate with 3 inputs has 3 NMOS in series and 3 PMOS in parallel. But why aren't there cmos gates with e.g. 10 inputs?
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dc sweep convergence issue for cmos inverter

I am having some convergence issue with DC sweep for a CMOS inverter. To duplicate the exact issue, see the following log as well as the attached netlist files, together with modelcard.nmos and ...
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How does this circuit with inverters work?

What this does this circuit do? I suspect it is an amplifier, but don't know how it amplifies. For example Inv 5 and Inv 6 are connected in parallel with reverse sides but there is a wire between ...
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70 views

CMOS Inverter circuit

I want to design CMOS Inverter which gives: 0 volt input --> 5 V output Any positive input voltage above threshold voltage --> 0 V output. On simulating, it is giving me alternatively +2.5v and -2....
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Measurement of Cmos Parasitic capacitors

i've had a question which asks if we assume that capacitance of capacitors with w/l of 1u/0.5 are then what are capacitance of capacitors (with the actual w/l) now i know cgs in saturation for ...
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Common Mode and differential Mode gain of this Cmos diff Amp inverter

This is one of questions our prof gave to students in recent years and im preparing myself for this exam. What is Common Mode and differential Mode gain of this Cmos diff Amp inverter? i understand ...
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Understanding CMOS Circuit Behaviour with Resistive Loads using Thevenin theorem

I have been reading the Digital Design: Principles and Practices 3rd Edition as a hobby. Unfortunately, I am stuck at page 103 of Section 3.5.2: Circuit Behavior with Resistive Loads. In Figure 3-27: ...
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IC layouts - Transistors (Body)

I'm trying to get into IC layouts... Why do I see some IC layouts with or without the body terminal on the transistors. Do MOSFet transistors need a body terminal in an integrated circuit? Or should ...
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Latch-Up in CMOS-Devices

I recently read something about the latch-up effect in CMOS-Structures but I don't understand why are MOSFETs affected by this effect. I understand that high currents through the source-drain path ...
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Measuring transconductance of any circuit

May I know if the following transconductance measurement test circuit is correct because I am getting quite small Gm values ? I suspect that I need to use some derivative function because changing ...
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78 views

Force the state of floating digital input to particular level

Given: a microcontroller in QFP package. A pin is configured as digital input, no pullups/pulldowns. The physical pin is not connected to anything else, besides the pad on PCB. Is there a way to ...
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31 views

Are there ways/technologies to use High negative voltages in flash memories?

I am using an FGMOSFET with tunneling gate and control gate as an analog memory for simulation in SPICE. I use -25V to inject electrons into the floating gate and 25V to remove electrons. Everything ...
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Wiring of body terminal in a network of MOSFET switches

I am trying to design a set of switches in a cmos design. The switches are supposed to control a number of capacitors and I want to implement them as single NMOS or PMOS transistors. Based on my ...
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Why do we use a CMOS for inverting a circuit when the PMOS already achieves that?

The output in a PMOS is as follows: I/P O/P 0 1 1 0 Why can't I just use this instead of using a CMOS for inverting logic? (Please ...
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71 views

Operational amplifier for higher slew rate

what are the possible ways to improve slew rate of an operational amplifier in CMOS technology?
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Resetting CD4017 Counter when power source is OFF

I found the circuit below online and I have two questions about the reset switch. Does it help to click the reset button when power is OFF? I mean, does it clears the memory of the CD4017 chip when ...
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74AS TTL to CMOS pull up resistor and maximum speed (or lowest delay)

Hello I have to pilot a CMOS input 5V chip device with a 7474 flip flop with the lowest possible delay to minimize clock jitter. Signal is about 11.3 Mhz I have two options: 1) 74HC74 (CMOS ...
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Implement an 8 input AND gate with least delay

I'm trying to implement an 8-input AND gate using CMOS technology with the best number of stages and least delay (I have attached the schematic in the link given). Using logical effort I have so far ...
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2answers
103 views

Weird Current Mirror

I just encountered this circuit and I'm a bit confused by it I see that it's an NMOS current mirror. At first I thought it's a cascode current mirror due to M3 on the right but it isn't. I have two ...
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103 views

Why does my AND cmos gate have less dissipation than my NAND gate?

I've just started taking a course in VLSI and from the little I know, this result seems a bit off. Below you can see the layout for the AND and NAND gate I designed : They both seem to be working ...
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Do cascoded MOSFETs need to be in their own wells in order to properly connect bulk to source?

I am learning to design CMOS layouts. When creating the layout for something like a cascoded current mirror, are individual wells needed to properly connect the bulk to source? For example, for the ...
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What is the response curve of a CMOS sensor cell to the amount of light?

Using my Nikon D5100, shooting RAW pictures and using Darktable to disable absolutely all contrast curves, white balancing, sharpening and even the debayering, I've measured the average value of the ...
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CMOS implementation of D flip-flop

I am trying to implement edge triggered flip-flop using CMOS logic. Google search provides following diagram on wikipedia: Upon simulating this using tanner, I find out that output resembles positive ...
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CMOS Inverter-based question from Sedra&Smith, Microelectronic Circuits

Exercise 4.47 from Microelectronic Circuits, 6th edition, Sedra & Smith. I am unable to analyze the following question. Can anyone help me solve it? I only know that the circuit won't remain ...
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Increased current consumption of micro-power devices

I've been working with microwatt and nanowatt power consumption devices for a while and I've mentioned that sometimes, due to unknown reason, current consumption increases in order of magnitude. ...
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97 views

Replace a relay with an analog switch

I'm trying to replace a relay with a SPDT cmos analog switch MAX4678 for switching a sine wave, The switch is powered with dual power supply +5/-5 and +5 to its V_logic pin. This is what i got in ...
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421 views

What is the difference between CMOS and Pass-Transistor Logic?

My friend and I are taking our first digital systems designs course this semester. Our professor has introduced to us two different type of circuit designs; CMOS and Pass-Transistor Logic. The ...
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CMOS Technology [closed]

Why is dynamic CMOS faster than static CMOS? One reason is that the load capacitance is small. I can not understand how they are related to the speed of CMOS. Another reason is the lower number of ...
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148 views

Output voltage in MOS cascode amplifier

I'll give a background to my main question:- In a simple NMOS as shown, while constructing the small signal model of the MOSFET, when there is no resistance between Vdd and drain, NMOS is modeled ...
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Jellybean Radio Button logic Chip

Below is an LTSpice simulation of a 'radio button' circuilt. Ignore the bottom button, I am working on a 'reset' mechanism to unlatch any of the other buttons. The idea is that the button you push, ...
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What is the lowest voltage a cmos transistor can operate?

I am trying to do some hspice simulation with some free 45nm CMOS transistor models. I found that an inverter can simulate properly with voltage as low as 0.25V, though it's slower. My question is, ...
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How to amplify RF signal to high enough level for a CMOS downconverting mixer?

I've been reading original academic papers on mixers and now a RF textbook and I have been unable to understand a very basic thing, which is how do I get a RF signal, say -65 dBm, at a high enough ...
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Finding drain voltage for a resistor loaded CMOS inverter with 0V at input terminal

Introduction: The following example is from the textbook Sedra/Smith Microelectronic Circuits. It is stated in the solution to this example that since both \$Q_n\$ and \$Q_p\$ are both matched and \$|...
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120 views

Replacing CMOS SRAM with equivalent TTL SRAM

I want to replace an IS62WV51216BLL-55 (http://www.issi.com/WW/pdf/62WV51216ALL.pdf) with an AS7C4098A-12 (https://au.mouser.com/datasheet/2/12/as7c4098a_v1.2-1288279.pdf), as the latter has much ...
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MCU sinking current from a higher voltage source

In previous designs, I have used an MCU digital output to drive the lower side of a resistor ladder to the supply voltage, to prevent power consumption when the ladder is not being sampled: Schematic ...
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How to manufacture chip on board?

I am a developer of a cheap product and i have no experience in mass production. Device is fully functional and represents a single sided PCB, a microcontroller, a bunch of diodes and a few passive ...
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5V to 3.3V Converter

I have a problem in connecting Raspberry PI to an MCP3202. I am using MCP3202 at 5V and knowing that raspberry pi works on 3.3v. I have found a solution to convert from 3.3V to 5V using 74HCT244. And ...
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Maximize output signal swing in digital circuit design

Please help me understand the following paragraph in chapter CMOS Digital Logic Circuit from book"Sedra/Smith micro electronics circuit 6e". An ideal VTC is one that maximizes the OUTPUT signal ...
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How can I reduce loading effect in dc common drain source follower?

I want to make a dc voltage buffer using an nmos source follower. I found that by making Rs as large as possible or even open, Vs= Vgs-Vth. I verified it using multisim. The problem is it suffers from ...
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Why isn't the BIOS' ROM chip made using CMOS technology?

After reading a computer hardware course on BIOS/CMOS, I'm still unable to determine the reason why the BIOS' ROM chip isn't built using CMOS technology, and why it is connected to a separate chip ...
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measurement of output impedance of a CMOS inverter

I am measuring output impedance of CMOS inverter using ngspice. No matter how I measure the output impedance, the result can never come any close to the following theoretical calculation if I reduce ...
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Adiabatic CMOS circuits in low power design

There are several techniques to reduce dynamic power consumption in low power design, but I could not understand the basic concepts of Adiabatic circuits and how will it reduce the dynamic power ...
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CMOS NAND Image

I was looking at this image which shows a CMOS NAND standard cell. However, how can I see this depicts a NAND? A CMOS NAND has parallel PMOS and serial NMOS transistors but somehow I can't see this ...
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Why is the input voltage of transistors in the CMOS circuit set to Vdd when calculating the equivalent resistance?

When deriving the equivalent resistance formula of NMOS inverter the graph which is used in derivation is as shown: $$R_{eq} = \frac{1}{-V_{dd}/2} \int_{V_{dd}}^{V_{dd}/2} \frac{V}{I_{Dsat}(1+\...
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Monostable multivibrator problem

As you see in the picture above, diode voltage drop is 0V, and the monostable multivibrator is made in CMOS technology with protection diodes. I have problem finding the output of this circuit in some ...
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Identifying the logic function of this specific MOS layout

I am not sure about the functionality of the following MOS layout. I came up with the logic function AND(NOT(AB),C). Can anyone confirm or correct me ? PS: The steps I made are attached