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Questions tagged [cmos]

"Complementary Metal-Oxide Semiconductor" is a process which implements a combination of PMOS and NMOS transistors. Most current digital logic is implemented in CMOS. Its cost-effectiveness due to being so widespread means many other applications have become common as well, such as in analog design, image sensors, telecommunication, etc.

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94 views

Do cascoded MOSFETs need to be in their own wells in order to properly connect bulk to source?

I am learning to design CMOS layouts. When creating the layout for something like a cascoded current mirror, are individual wells needed to properly connect the bulk to source? For example, for the ...
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137 views

What is the response curve of a CMOS sensor cell to the amount of light?

Using my Nikon D5100, shooting RAW pictures and using Darktable to disable absolutely all contrast curves, white balancing, sharpening and even the debayering, I've measured the average value of the ...
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CMOS implementation of D flip-flop

I am trying to implement edge triggered flip-flop using CMOS logic. Google search provides following diagram on wikipedia: Upon simulating this using tanner, I find out that output resembles positive ...
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CMOS Inverter-based question from Sedra&Smith, Microelectronic Circuits

Exercise 4.47 from Microelectronic Circuits, 6th edition, Sedra & Smith. I am unable to analyze the following question. Can anyone help me solve it? I only know that the circuit won't remain ...
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83 views

Increased current consumption of micro-power devices

I've been working with microwatt and nanowatt power consumption devices for a while and I've mentioned that sometimes, due to unknown reason, current consumption increases in order of magnitude. ...
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131 views

Replace a relay with an analog switch

I'm trying to replace a relay with a SPDT cmos analog switch MAX4678 for switching a sine wave, The switch is powered with dual power supply +5/-5 and +5 to its V_logic pin. This is what i got in ...
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463 views

What is the difference between CMOS and Pass-Transistor Logic?

My friend and I are taking our first digital systems designs course this semester. Our professor has introduced to us two different type of circuit designs; CMOS and Pass-Transistor Logic. The ...
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60 views

CMOS Technology [closed]

Why is dynamic CMOS faster than static CMOS? One reason is that the load capacitance is small. I can not understand how they are related to the speed of CMOS. Another reason is the lower number of ...
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170 views

Output voltage in MOS cascode amplifier

I'll give a background to my main question:- In a simple NMOS as shown, while constructing the small signal model of the MOSFET, when there is no resistance between Vdd and drain, NMOS is modeled ...
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0answers
80 views

Jellybean Radio Button logic Chip

Below is an LTSpice simulation of a 'radio button' circuilt. Ignore the bottom button, I am working on a 'reset' mechanism to unlatch any of the other buttons. The idea is that the button you push, ...
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1answer
61 views

What is the lowest voltage a cmos transistor can operate?

I am trying to do some hspice simulation with some free 45nm CMOS transistor models. I found that an inverter can simulate properly with voltage as low as 0.25V, though it's slower. My question is, ...
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241 views

How to amplify RF signal to high enough level for a CMOS downconverting mixer?

I've been reading original academic papers on mixers and now a RF textbook and I have been unable to understand a very basic thing, which is how do I get a RF signal, say -65 dBm, at a high enough ...
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79 views

Finding drain voltage for a resistor loaded CMOS inverter with 0V at input terminal

Introduction: The following example is from the textbook Sedra/Smith Microelectronic Circuits. It is stated in the solution to this example that since both \$Q_n\$ and \$Q_p\$ are both matched and \$|...
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147 views

Replacing CMOS SRAM with equivalent TTL SRAM

I want to replace an IS62WV51216BLL-55 (http://www.issi.com/WW/pdf/62WV51216ALL.pdf) with an AS7C4098A-12 (https://au.mouser.com/datasheet/2/12/as7c4098a_v1.2-1288279.pdf), as the latter has much ...
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114 views

MCU sinking current from a higher voltage source

In previous designs, I have used an MCU digital output to drive the lower side of a resistor ladder to the supply voltage, to prevent power consumption when the ladder is not being sampled: Schematic ...
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How to manufacture chip on board?

I am a developer of a cheap product and i have no experience in mass production. Device is fully functional and represents a single sided PCB, a microcontroller, a bunch of diodes and a few passive ...
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118 views

5V to 3.3V Converter

I have a problem in connecting Raspberry PI to an MCP3202. I am using MCP3202 at 5V and knowing that raspberry pi works on 3.3v. I have found a solution to convert from 3.3V to 5V using 74HCT244. And ...
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125 views

Maximize output signal swing in digital circuit design

Please help me understand the following paragraph in chapter CMOS Digital Logic Circuit from book"Sedra/Smith micro electronics circuit 6e". An ideal VTC is one that maximizes the OUTPUT signal ...
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83 views

How can I reduce loading effect in dc common drain source follower?

I want to make a dc voltage buffer using an nmos source follower. I found that by making Rs as large as possible or even open, Vs= Vgs-Vth. I verified it using multisim. The problem is it suffers from ...
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6k views

Why isn't the BIOS' ROM chip made using CMOS technology?

After reading a computer hardware course on BIOS/CMOS, I'm still unable to determine the reason why the BIOS' ROM chip isn't built using CMOS technology, and why it is connected to a separate chip ...
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639 views

measurement of output impedance of a CMOS inverter

I am measuring output impedance of CMOS inverter using ngspice. No matter how I measure the output impedance, the result can never come any close to the following theoretical calculation if I reduce ...
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37 views

Adiabatic CMOS circuits in low power design

There are several techniques to reduce dynamic power consumption in low power design, but I could not understand the basic concepts of Adiabatic circuits and how will it reduce the dynamic power ...
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114 views

CMOS NAND Image

I was looking at this image which shows a CMOS NAND standard cell. However, how can I see this depicts a NAND? A CMOS NAND has parallel PMOS and serial NMOS transistors but somehow I can't see this ...
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165 views

Why is the input voltage of transistors in the CMOS circuit set to Vdd when calculating the equivalent resistance?

When deriving the equivalent resistance formula of NMOS inverter the graph which is used in derivation is as shown: $$R_{eq} = \frac{1}{-V_{dd}/2} \int_{V_{dd}}^{V_{dd}/2} \frac{V}{I_{Dsat}(1+\...
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143 views

Monostable multivibrator problem

As you see in the picture above, diode voltage drop is 0V, and the monostable multivibrator is made in CMOS technology with protection diodes. I have problem finding the output of this circuit in some ...
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80 views

Identifying the logic function of this specific MOS layout

I am not sure about the functionality of the following MOS layout. I came up with the logic function AND(NOT(AB),C). Can anyone confirm or correct me ? PS: The steps I made are attached
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651 views

D FLIP FLOP Cadence

Basically I am designing D flip flop. While doing my pre-layout simulations, not getting the output Q for the inputs. See the attached attachments. But when I tried to take the output from CLKPULSE, ...
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Why is there no rolling shutter when using a mechanical shutter?

So I know it might not be the best place to ask this question, but maybe some of you are familiar with the mechanics of digital mirrorless cameras and the technology of CMOS sensors. I don't quite ...
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189 views

What is comparison of readout times of global and rolling shutter cameras? [closed]

Rolling shutter will take more time because of sequential readout and global will take less time.But what are the exact values of image readout time?
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92 views

PSPICE simulation

I have a PSPICE file that contains approximately 200+ transistors. Naturally, simulating the whole circuit everytime I make a change takes a while. Is there anyway to run a simulation measuring only ...
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1answer
59 views

Bump Circuit in PSPICE

I am designing a bump circuit in PSPICE to determine if two voltages are equal. The schematic is shown in the figure below. The parameters are set in the subthreshold region, with a VDD of 2 volts. ...
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1answer
267 views

Is a TXB0108 apt for level-shifting in SPI programming?

I plan to use a TXB0108 to level-shift between the cheap CH341A programmer voltage and the Winbond W25Q64FW from 3.3V to 1.8V On the silicon I can read: ...
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264 views

Subthreshold Transconductance Amplifier

As part of a broader project, I am designing IC circuit using CMOS to one of the first steps I'm working on is the filtering a series of pulses with of the noise. The actual pulses are around 1 kHz so ...
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251 views

How could I put an Enable pin on a standard two-stage CMOS op-amp?

I need to design an LDO regulator that only sources supply voltage and current to the load whenever it receives a logic-1 signal. Since the main element used in the LDO regulator is a differential ...
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77 views

Dynamic power dissipation of a Cmos inverter with relation to it's geometry

I know that the dynamic power dissipation of a CMOS inverter is defined by the equation: Pd = (Cl)(Vdd^2)(fb). My teacher challenged us to find ways to reduce power dissipation besides the obvious ...
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123 views

Why do we measure \$I_{ds}\$ for CMOS instead of \$I_{sd}\$?

The standard way to write current across a MOS seems to be along the \$I_{ds}\$, i.e. from drain to source. Why don't we use \$I_{sd}\$ instead? I understand both ways are equivalent, but would it not ...
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82 views

How to send to pulses to a CMOS Counter

I have tried to find answers to this many times, and the only solution I have been able to find is having two 555 Timers (or a 556) one in astable, and one in monostable. I could easily do this with ...
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124 views

1Hz pulse generator - LVCMOS 1.8 output

I am pretty new to electronic design so sorry in advance if the question is too naive. I need to build a small portable 1Hz pulse generator and connect it to a FPGA input pin, configured in LVCMOS 1....
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35 views

Deriving the Transistor Width for NOR

I'm an undergraduate electrical engineer and my universities notes are not the best, I have an assignment in which I do not want the answers to but the question has given me the oxide capacitance, ...
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398 views

Why not switching extra inverters with opposite MOSFETs in CMOS XOR gate?

Below you can see a CMOS XOR gate. I wonder why we do not change extra inverters like A' or B' with opposite MOSFETs. For example, could not we just put the green construction in the place of red ...
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508 views

What is the use of pull-down networks in CMOS gates?

Below you can see the basic CMOS inverter. What I don't understand about this particular design is the purpose of the n-channel mosfet which is the part referred as pull-down network. What if we ...
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How necessary is ESD protection, really?

I'm not asking about manufacturing. I'm asking about designing electronics to survive normal use in the field. I want to figure out just how necessary it is to include TVS diodes in my design. As I ...
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62 views

How did we find Vin in this CMOS?

Why did the lecturer decided that Vin is vGSn - vGSp + vDD , Why did he not go through the drain path and used vGDn and vGDp ?
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what logic family does tri state logic fall into?

Here is a good Wikipedia on logic families. This seemed like a particularly important line. Of these families, only ECL, TTL, NMOS, CMOS, and BiCMOS are currently still in widespread use. I'...
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89 views

Unexpected Behavior of a MOSFET Two Stage Differential Op-Amp

Trying to come-up with a basic default MOSFET-transistor amplifier simulation (for educational purposes). I don't get something. In the simulation below "out" is -1.84V while I expect something more ...
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64 views

Are D flipflop inputs and clock thresholds the same for a given logic family?

I'm using an SOIC20 74ACT574 octal flipflop in a design. Vcc is 5 V, and GND is 0 V. The datasheets give V_IH (logic high input, guaranteed minimum) as 2.0 V and V_IL (logic low input, guaranteed ...
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MOSFET Terminals in Layout

I am currently doing layouts in CMOS VLSI Design and I have gotten to drawing stick diagrams. The schematic of the 2 input NAND gate is shown below. In drawing the layouts I have trouble deciding ...
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Can I create a CMOS AND gate with 2 serial n-type and 2 paralel p-type CMOS transistors?

So I know that a CMOS AND gate is made with 2 parallel p-type transistors and 2 serial n-type transistors and an inverter on the output. But can we just make the AND gate similar to the NOR gate -...
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418 views

How to detect pulse duration with cmos circuit

I have created a circuit where I want to detect a pulse width , but unfortunately I can't get what I want. I think my circuit is totally wrong, I am looking online to find a solution, but the closest ...
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300 views

Cascode Amplifier vs Cascode Amplifier with CMOS current source

So I studied the gain cascode amplifier as follows, I understand that the gain for this circuit is approximately -(gmro)^2 Now, here is a different circuit using the cascode amplifier but instead of ...