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Questions tagged [cmos]

"Complementary Metal-Oxide Semiconductor" is a process which implements a combination of PMOS and NMOS transistors. Most current digital logic is implemented in CMOS. Its cost-effectiveness due to being so widespread means many other applications have become common as well, such as in analog design, image sensors, telecommunication, etc.

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773 views

Minimum number of complementary CMOS to implement \$F=ABC+\overline{(A+B+C)}\$?

Minimum number of complementary CMOS transistors pair will be required to implement function,\$F=ABC+\overline{(A+B+C)}\$ are? \$(A)6\$ \$(B)7\$ \$(C)8\$ \$(D)9\$ I tried like ...
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550 views

Given a pull-up network, draw the complimentary pull-down network (CMOS gates)

this is for my computer organization class (I am a CS major), but I figured this post belongs better here than on stackoverflow. I am asked to draw out the complimentary pull down network for the ...
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2answers
183 views

How to find power efficiency in DC-DC converter circuit

We are currently simulating a dcdc converter called the LTC3108. The input voltage is 500mV and the output is 3.3V through the dcdc converter. Here we have to calculate the efficiency of the circuit ...
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2answers
108 views

Another solution for all MOS are in cutoff saturation region

Here is a two stage amplfier with a beta multiplier bias(lab3),the schematic of lab3 is in the second picture. I simulate them when VDC is 1.8v and 1.98v for tt-corner and ff corner in 25 degree ...
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0answers
41 views

Need help understanding a fairly vague solution to example problem (the topic is noise in CMOS circuits)

So I have the solution to the following example problem I am working on: Now the issue is that I am trying to understand the solution I was given: The thing is this solution is simply quite vague. ...
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1answer
72 views

Question on feedback (the topic is in CMOS circuits)

So right now I'm studying feedback in CMOS circuits (i.e. when there is some sort of connection between the input and the output like in the picture below): Now during the next step in the example I ...
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86 views

How do voltages at outputs drop as current increases?

As I looked at some 74xxTxx ICs, such as this simple NAND gate, I noticed that the minimum \$V_{OH}\$ decrease as current flowing from the outputs increase. But, from my understanding of Ohm's law, \$...
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92 views

Existence (or reason of lack) of simple cmos LIFO registers IC

There's a project I'm working on that needs a simple LIFO register. What I mean by simple is to support the PUSH & POP operations, and I guess EMPTY and FULL indicators. I must be searching with ...
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135 views

Signal path switching for effect circuits

I'm trying to build a method of switching signal order with three circuits in a rack unit. I've been researching different methods, using relays, using CMOS etc but I'm getting a bit overwhelmed and ...
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1answer
257 views

CD4521 frequency divider warms up while RESET is HIGH

I have a peculiar problem involving the CD4521 frequency divider of which I use two in a redundant configuration as shown in my schematic snippet below: I noticed that while the devices are held ...
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593 views

Worst case delay for a CMOS gate

I want to determine the input pattern for the worst case tpHL of this CMOS gate. I think there may be more than one input pattern that give worst case tpHL. The following is my reasoning: The ...
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1answer
344 views

How to make full wave rectifier?

I observed one paper [A highly efficient interface circuit for ultra-low-voltage energy harvesting] and i tried Full-wave rectifier [attached in below]. But this circuit generating output wave form ...
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1answer
89 views

Energy Harvesting IC datasheet question

I am experimenting with energy harvesting using electromagnetic induction. I am using the [LTC3108(Ultralow Voltage Step-Up Converter and Power Manager) circuit. ==>http://cds.linear.com/docs/en/...
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1answer
100 views

Diffusion capacitence

I am trying to figure out the capacitance seen at each node, given that the source and drain diffusion capacitance is shared in the nmos stack. Given that the fingered layout uses a finger width of W=...
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246 views

4.5 volts voltage with the 74HC logic family?

I'm sorry if my question is too specific to the 74HC logic family, but as the answer may vary by family, I place myself on the safe side. The 74HC family runs from 2 to 6 volts or 4.5 to 5.5 volts as ...
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73 views

What is the reason CMOS took over as an inverter for fabrication of gates?

I get to know that the static power dissipation is zero in case of CMOS where as there is some static power dissipation in NMOS with saturated load and linear load and with NMOS with depleted load. ...
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3answers
98 views

Can I power 4000 series CMOS ICs from two AA batteries?

The specs (for TI chips) say anywhere from 3 - 18V, and I've measured two alkaline AA batteries at just over 3 volts. I'm wondering if that dips below 3V when the batteries get old, whether or not ...
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44 views

Looking for the logical equation from this PMOS circuit

I am looking for the logical equation that describes the given circuit below. Unfortunately I don't have information whether \$U_b\$ is positive or negative - would that make a difference? I derived ...
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2answers
258 views

Pull down resistor value in debouncer circuit

I am from computer background and have made debouncer circuit (SR) using NOR gate IC HD74LS02P as a part of digital electronics project. I have used pull down resistor at all inputs of the gates used. ...
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1answer
114 views

Printed Circuit Board Layout

I am working on a printed circuit board layout. I understand the circuitry within the red box, however, I am having trouble deciphering the purpose of the purple lines and why the bottom-most ...
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5answers
1k views

Why do TTL pulse generators generate an asymmetrical square wave (unlike CMOS)?

I've read that the asymmetrical (about 1/3 mark-to-space) output waveform is due to input gate characteristics of a TTL inverter, but I want to know more about which characteristics of the TTL input ...
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4answers
552 views

Resistance on Vcc and input pins CMOS

Sorry if my the answers to my question is just "look up the specs of CMOS", I wasn't able to find it, only data on the manufactoring process. Doing research on a project, being new, I found a forum ...
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2-input CMOS NOR gate circuit operation

Someone please explain to me how the circuit below operates as NOR gate. I have created a truth table next the diagram based on my understanding of basic MOSFET switching. For the output to be equal ...
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1answer
5k views

How to draw stick diagram of a function

I am a student of computer science and engineering. We have VLSI design in current semester. Now i am having trouble drawing stick diagram for a given equation. What is the step by step procedure for ...
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1answer
128 views

Logic shutdown for CMOS oscillator

I would like to add a !(SLEEP) line for this CMOS oscillator in a way that in case of low input on !(SLEEP) line, the output PWM line is constant low. 2 questions for the circuit: In this case do I ...
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3answers
188 views

Differential Amplifier with Hard Limiting

I'm currently going through RF Microelectronics by Razavi. In chapter 3 he presents an example where the following signal is applied to a differential amplifier with a tail current source. $$Acos(...
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1answer
231 views

are 100K resistors too weak for connecting HC to cmos?

I have created two identical circuits. The only difference between them apart from the number of lines on the LCD is that the old circuit uses 10K pull-up resistors instead of 100K pull-up resistors. ...
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1answer
65 views

Problem with mixed CMOS op-amp supply voltages on a square to saw wave converter

I am designing a square wave to saw wave converter by first integrating the square wave into a triangle wave, then toggling between the triangle wave and it's inverse, using 2 CMOS 4066 switches ...
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1answer
1k views

Cascode Current Mirror, Minimum output voltage

I can say that I understand simple current mirrors fairly well, but what i do not understant is the minimum output voltage requierd for the circuit to work properly...for the transistors to be in ...
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5answers
3k views

CMOS logic Gates XOR

I'm currently doing the practice problems for CMOS VLSI Design 4th Edition. Question 1.6 says to use a combination of CMOS gates to generate the following functions (solution attached below function ...
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1answer
362 views

In cmos, why connect bulk to source instead of vdd/gnd?

In cmos, both p and n type mosfets have their bulk connected to their source. Then p-types sources are strictly connected to vdd, and n-types sources to gnd. 1: Why not have bulk connected directly ...
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2answers
147 views

CMOS NAND VS an Alternative NAND Structure

The CMOS version of a NAND gate has two NMOSes series on the bottom and two PMOSes in parallel on the top. We can replace the PMOSes with a resistor and the circuit works (alternative NAND). What are ...
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1answer
139 views

Non-trivial logic function to CMOS schematic

I wanted to implement the function: $$Y = \neg (A \land (B \lor C))$$ This is what I came up with, it looks correct to me but I would like a second opinion on that. simulate this circuit – ...
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1answer
410 views

Cascode Amplifier Gain

I've been going through Design of Analog CMOS integrated circuits 2nd Edition by Razavi. I'm currently at the Cascode amplifier section. The author does an example for calculating the gain for the ...
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1answer
203 views

Inverted inputs with CMOS transistors

Lets say I want to realize a logic function in CMOS gates. I have a function like this $$Y = (¬A *¬B) + ¬C + ¬D$$ If I had a function without inverted inputs: $$ Y = ( A*B) +C +D $$ it does not ...
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51 views

How CMOS transistors might be used as a capacitive sensor for biopotential?

I was wondering how CMOS-based capacitive electrodes might be designed (e.g. in this article I stumbled on). It seems to me, that it would make sense to capacitively couple the input of the transistor ...
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1answer
426 views

What is the significance of FO4 inverters in CMOS static circuits?

With regards to the image above, I wanted to know what is the importance of Fan Out of 4 (FO4) for optimum design and what improvements does it incur over designs that are either higher or lower than ...
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5answers
667 views

Using Transistors as Logic Gates

I am curious if this could work. I have 3 inputs (A,B,C) and I know that Input A takes the longest to calculate. Is it possible to use single Transistors in place of normal AND Gates so that a signal ...
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1answer
249 views

Why ring oscillator showing irregular graph ?

I'm trying to design ring oscillator in CADENCE using 180 CMOS .Instead of showing inverted clocking output , output changes in less then millivolt ranges. When I connect only 9 inverter like this ...
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1answer
125 views

How can I have an ECL logic input for a CMOS logic gate

I'm working on a triggering system that uses a comparator to check if the signal is below a threshold value. I found a great comparator for the job, except its output is ECL logic. I wanted to use the ...
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1answer
221 views

Inversion Coefficient Based Design in CMOS amplifiers

I have designed amplifiers, using potential division method. What are the steps to design differential amplifier using inversion coefficient based design methodology? Please provide links/...
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1answer
114 views

CMOS Inverter DC charecteristics steepness

I was trying to solve the following multiple choice question(only one option is correct). I simulated the inverter for varying W with L constant. What I found is the absolute value of dVout/dVin ...
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1answer
517 views

How does this CMOS OTA with common-mode feedback work?

In class I learned about the circuit shown below. It is basically a simple CMOS OTA with a common-mode feedback realized by a resistive divider. But I am not quite sure how it works. Lets say that I ...
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1answer
165 views

convert TTL/CMOS output signals to 0V and 5V [duplicate]

Is there an easy way to convert TTL/CMOS output signals to 0 and 5V? For example, if an ic outputs 0.1V as "0", I'd like to convert it to 0V and if it outputs something like 3.9V as "1", I'd like to ...
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5answers
2k views

Will multiple chips outputing onto a bus for a few nanoseconds cause damage?

I'm working on a home-brew CPU design, with the usual mix of parallel EEPROMs, static RAMs and registers, tri-stated onto a single 8 bit bus. My /output-enable logic for three tristate-able chips on ...
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2answers
436 views

How does an output switching from HI or LO to HI-Z effect an input in CMOS?

Let's say we have a tri-state buffer output connected to an inverter input, implemented in 7400 series CMOS chips. If the buffer output is HI, the inverter output is LO. If the buffer output is LO, ...
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3answers
1k views

Analyzing a transistor relay driver

I found this circuit for a relay driver. It is similar to others I have seen, though it appears to have two extra parts that others do not have. I mostly understand how it works, but I would like to ...
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186 views

Digital output won't go from 5V to 0V with a diode attached

Edit I did a poor job of soldering and forgot to solder the pull-down resistor on the input to the buffer. My mistake for posting a question too soon. I built a circuit to read a button with a ...
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2answers
1k views

Which logic families interpret a floating input as a definite value?

From what I remember, from decades ago, 1980's 5v TTL chips would see a floating input as a zero (because they switched on current, rather than voltage). Update: it seems they were interpreted as ...
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1answer
925 views

CMOS and Pseudo NMOS

Im trying design this function : (NOT Y)=A+BCD in CMOS my design in pic below now i want to design this function in Pseudo NMOS but i dont know how to design it in Pseudo NMOS.anyone can help please??