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Questions tagged [cmos]

"Complementary Metal-Oxide Semiconductor" is a process which implements a combination of PMOS and NMOS transistors. Most current digital logic is implemented in CMOS. Its cost-effectiveness due to being so widespread means many other applications have become common as well, such as in analog design, image sensors, telecommunication, etc.

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928 views

CMOS and Pseudo NMOS

Im trying design this function : (NOT Y)=A+BCD in CMOS my design in pic below now i want to design this function in Pseudo NMOS but i dont know how to design it in Pseudo NMOS.anyone can help please??
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161 views

Finding Vds in a CMOS without info. on channel modulation?

"What would (ideally) be the DC voltage at the output in the following circuit?" That's how the question was formulated. Can it be found without having any information on \$V_A\$ or on \$\lambda\$? ...
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836 views

Is it ok to leave analog switch inputs floating?

Will I run into problems if I leave a few of the analog pins on a CMOS switch (such as the DG409) floating? I know that CMOS digital inputs should never be left floating due to the fact that the ...
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49 views

Source/Sink on 74AHCT2G125DC not driving WS2712bs

Per advice in this post I am using a 74AHCT2G125DC (datasheet) to drive a Neopixel/WS2812b strip's data pin from a 3.3v MCU. The MCU is driving A1, and the addressable LEDs are chained from Y1. VCC on ...
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334 views

13-bit Latch Pedal Sustain IC M147 - Old Datasheet Questions

My questions are as follows: F1 is the way out for an applier? If the outputs are 1 ', 2', 4 ', 8' and 16', what kind of filters are these? Acronyms TS and TP, what are they? It is the first time ...
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3answers
354 views

Choosing LEDs/resistors to drive directly from 3v3 HC CMOS logic

I'm building a home-brew CPU and I would like to add some blinkenlights, to show the logic state of various signals. (It will run at 1Hz - 100kHz.) Can I directly drive an LED from a 3v3 74HCxxx ...
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227 views

Understanding a CMOS logic gate with strange details

I'm trying to understand which logic is implemented by the following CMOS gate. Comparing with the following CMOS NAND gate, I feel like the above logic gate could be a NOR gate, I'm not sure. My ...
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106 views

CMOS Circuit, Finding Output Switching Frequency

I'm tasked to analyze the power usage of a CMOS circuit, but I cannot figure out the output switching frequency. Every 10ns, the circuit is stimulated with input vectors 1110, 1111, 1101, 1111, ...
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2answers
206 views

I/V converter + analog switch

I am trying to switch the ranges of an I/V amplifier, such that I can measure from 100nA to ~1mA of current up to 100kHz (similar to this question). I make the switching using an TS5A3357 analog ...
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1answer
580 views

CMOS Schmitt Trigger: contradictionary information

Weste and Harris in "CMOS VLSI Design" describe the CMOS trigger as follows: Let's call the transistors in the first columns from bottom to top M1,M2; M4,M6 and the transistors in the second column ...
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2answers
895 views

Why aren't latch based designs common these days?

Almost every ASIC out there if flip-flop based. In summary, DFF is two latches pushed closely together. While in a latch based design you can "separate" these two latches apart and squeeze logic in-...
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812 views

Master-Slave D-FF vs Edge triggered: timing issues, simulation shoot-through

There is a thing that bugs me about flipflops: usually, the edge-triggered flops are used, which sample D and update their Q on the posedge, i.e. master latch has inverted clock and slave latch has ...
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1answer
161 views

In what direction is the photodiode placed in a CMOS image sensor?

I am currently trying to understand how a CMOS Active Pixel Sensor (APS) works. I came across two different diagrams (one in a presentation, the other one from wikipedia). Which is the correct way to ...
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1answer
1k views

Will this 4069-based CMOS low frequency oscillator schematic work?

I'm into building synthesizers from scratch. I've recently built a low frequency oscillator as part of an instrument which works well, based on a TL074 quad op amp. However, it uses a heck of a lot of ...
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1answer
2k views

Sizing transistors for a CMOS circuit?

Say we have this cmos circuit any advice how you would size up the transistors assuming that the gate is minimum-sized. Ive done some reading and I am struggling to understand. Is there an definition ...
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1answer
76 views

Logical effort and delay estimation

So as I have understood the logical effort for a 2 input nand gate with only one of the inputs active = 4/3. Furthermore the net logical effort is 8/3 (considering both the inputs). Now given that the ...
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74 views

multiplexer with floating outputs

I have actually a solution based on a multiplexer (CD4051) which drives 8 outputs, either at 0V or 3.3V (the input is at 3.3V). Each output of the multiplexer drive a NMOS and the goal is to have a ...
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2answers
1k views

Spike in inverter output waveform due to Cgd coupling

So while analysing the waveforms, I have noticed spikes in the ouput during input transitions for gates like inverter, nand etc. and so I was asked to look up Miller effect to explain the phenomenon. ...
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112 views

Turning on/off MOSFET using 4000 series CMOS

I intend to use 4000 series CMOS running at 12V to turn on some power MOSFETs (SUM55P06 and IRF2903) handling 8A at 12V. However, the arrangement of logic gates I need to simplify the driving s/w ...
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Why doesn't the output of the rectifier come out?

Hello, I made a rectifier circuit. I also include a comparator. I referred to this paper --> An ultra-low-voltage self-powered energy harvesting rectifier with digital switch control. The circuit ...
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2answers
2k views

Fast bidirectional 3.3 to 5V level shifter

For a hobby project of mine, I'm thinking about connecting some old 5V SRAM chips like this one to a 3.3V - capable FPGA. The target frequency is 50MHz. After some simulator experiments I found out ...
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115 views

static power of digital CMOS

hello there i want to find static power consumption of IC in following question i know about static power and dynamic power Static power is power consumed while there is no circuit activity PSP = ...
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335 views

DC Analysis of CMOS-inverter

I am studying about CMOS inverter and in my book provided the transfer characteristic as follows (actually i simulated it): and then I changed the parameters and I got something like this: I found ...
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1answer
134 views

Developing corner CMOS models from a typical model

I am looking to develop fast-fast, fast-slow, slow-fast, and slow-slow (FF, FS, SF, SS) CMOS models from a typical model for a particular mature CMOS process (say, 0.25 um minimum feature size and ...
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432 views

Design CMOS comparator

I made the circuit. like this paper, But It's not working. When you insert the AC input, a square waveform should appear. I can not interpret the circuit well. If you know anything, please answer ...
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1answer
643 views

How to design CMOS bridge rectifier?

I designed the bridge rectifier circuit. I wnat to make a full-wave rectification. so, I made a CMOS circuit. I refered to other papers. Figure2. "An ultra-low-voltage self-powered energy harvesting ...
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6answers
3k views

Can camera sensors be damaged by light?

Suppose a 3.3 V white (or any colour) LED with a current draw of 20 mA is shone into the lens of a cheap webcam (or any budget camera) at close range (< 3 cm) for a long period of time (24 hrs) or ...
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280 views

How can I raise a CMOS 1.8V output to 5V LVTTL input with a MOSFET?

simulate this circuit – Schematic created using CircuitLab I'm trying to drive a 5V LVTTL UART input on a ATMega32u4 with a 1.8V CMOS ouput on a Telit UL865. I'm using the NTE2987 enhancement ...
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2answers
133 views

Is it safe to instantaneously discharge 100nF 5V through an HC CMOS gate?

Consider the classic "pulse stretcher" circuit shown in Fairchild AN-140, Figure 12. When the first gate drives low, the instantaneous capacitor discharge current will easily exceed the absolute ...
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3answers
195 views

Driving a CMOS 1.8V input with a CMOS 5V output

I'm trying to drive a Telit UL865 UART 1.8V input with a ATMega32u4 UART 5.0V output. Both of these gates are CMOS. The datasheet for the Telit says that it has a 5K to 12K pullup on the input. I ...
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2answers
177 views

How do CMOS switches behave when Vdd is grounded? What are the alternatives if they behave undesirably?

Say, I have a SPST CMOS switch, does it break the connection between two terminals when the power is out (Meaning Vdd=Vcontrol=0)? Or does it ground one terminal? If it doesn't completely break the ...
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2answers
385 views

cmos push-pull configuration

Why here http://www.talkingelectronics.com/projects/MOSFET/MOSFET.html they say that push-pull configuration with high-side transistor as PMOS and lowside as NMOS is incorrect? I have found many ...
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112 views

Figure out logical function from a CMOS logic circuit

"Given that Vdd > 0, determine the logical function that this CMOS circuit represents." Any help on how to approach this problem would be great. Many thanks!
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134 views

Delay calculation in CMOS devices

I've noticed that CMOS delays are only up to 50% of output instead of 100%. Why do some people use 50% delay? Is there an advantage as opposed to 100% delay?
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1answer
115 views

Are source and drain terminals of Access Transistors in 6T SRAM interchangeable?

My textbook understanding is that the source terminals (S) of the access transistors in a 6T SRAM cell are to be connected to the bit lines (BL/BLB) while the drain terminals (D) to the storage nodes (...
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1answer
87 views

What could be a good project to realize neural network in hardware (VLSI) for a beginner? [closed]

As a beginner how can I start implementing neural network using CMOS technology. I have come across implementing neural nets that mimic basic gates.
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34 views

Switching another circuit that has high current

I'm trying to use a Raspberry Pi to switch on and off another circuit. This other circuit draws a LOT of current, so I'm using a power supply dedicated to that load. I tried to do a simple op-amp ...
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1answer
125 views

why is contamination delay lower bound?

I am taking a course from edX called computation structures: 1.Digital Circuits. When the course explained about CMOS timing, there was propagation delay(tpd) and contamination delay(tcd). I ...
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2answers
668 views

Op-amps vs common drain amplifier for photodiode integration

I've been playing around with photodiodes and op-amps lately, and thought it might be fun to construct a really crude camera with a dozen pixels. I was going to model it on an active-pixel CMOS ...
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1answer
1k views

What does it mean by P:N ratio of a CMOS inverter with equal rise and fall times?

Can someone explain what does it mean when one say P:N sizing ratio of an inverter. FO=4 and equal rise and fall time.
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3answers
346 views

Are silicon microbolometers inherently more expensive than conventional CMOS light sensors?

We're finally starting to see practical thermal imaging sensors (microbolometers) entering the consumer market. However, they are still vastly more expensive than comparable visible imaging sensors. ...
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2answers
293 views

2N7002P MOSFET N channel complementary P channel

I want to start creating CMOS logic gates, maybe a binary adder or something, but first I need to know which parts I will be using. I searched for the cheapest N channel MOSFET, found it (2N7002P), ...
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1answer
182 views

Is there any characteristics difference indicated by this two symbols ? [duplicate]

During study , I am encountered with this two Inverter symbols . Sometimes this two symbols are usedn in same logic circuit. Though they are working as inverter, I'm guessing there must be some ...
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1answer
965 views

Please help me understand how this cmos mirror adder works

I can understand the left adder circuit but the right one has both the nmos and pmos network exactly same. I have learnt that the pmos and nmos are dual networks of each other. How does one arrive at ...
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3answers
2k views

Unbuffered vs. Buffered CMOS Circuits

I am somewhat confused with why someone would want to buffer a CMOS logic gate and what the advantages are to doing so. Let's say I have a certain CMOS logic gate such as a NAND gate as shown below: ...
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1answer
1k views

Transmission line simulation in LTSpice? How to model a CMOS input?

I am trying to simulate the effect of a PCB trace on a clock signal with LTSpice, see the following pictures: In my quick and dirty setup, the clock receiver is the resistor Rin. I the real world, it ...
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1answer
354 views

How did bipolar IC density compare to MOS ICs?

Historically, how did the density of bipolar (e.g. TTL) chips compare with MOS? How complex could bipolar ICs get before they hit limits? Does anyone have a Moore's law-style graph for bipolar ...
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2answers
1k views

How is this CD4013 application supposed to work?

I'm trying to troubleshoot an issue in a synthesizer I have, an early 80s synthesizer from Roland called RS-09. I'm just starting to study logic and am perplexed by what's going on. In this ...
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1answer
51 views

Verification of this CMOS realisation

I have to make the CMOS-equivalent of this function: \$A'*B'+C'\$. I made this CMOS-circuit, but I'm not sure if it's correct: simulate this circuit – Schematic created using CircuitLab The ...
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268 views

CMOS Logic Design [closed]

How to represent such an equation using CMOS inverter (The whole equation is inverted) Z=~[(A.B)+C.(A+B)] The load equation will be : [(A'+B').C'+(A'.B')] ' means it is inverted The driver equation ...