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Questions tagged [cmos]

"Complementary Metal-Oxide Semiconductor" is a process which implements a combination of PMOS and NMOS transistors. Most current digital logic is implemented in CMOS. Its cost-effectiveness due to being so widespread means many other applications have become common as well, such as in analog design, image sensors, telecommunication, etc.

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How could I put an Enable pin on a standard two-stage CMOS op-amp?

I need to design an LDO regulator that only sources supply voltage and current to the load whenever it receives a logic-1 signal. Since the main element used in the LDO regulator is a differential ...
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Practical ESD protection without latchup

My understanding has always been that any CMOS I/O pin needs external ESD protection - since the on-chip protection diodes are only there to guard against ESD events during manufacture handling. ...
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Diffusion capacitence

I am trying to figure out the capacitance seen at each node, given that the source and drain diffusion capacitance is shared in the nmos stack. Given that the fingered layout uses a finger width of W=...
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Logical effort and delay estimation

So as I have understood the logical effort for a 2 input nand gate with only one of the inputs active = 4/3. Furthermore the net logical effort is 8/3 (considering both the inputs). Now given that the ...
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1k views

Transmission line simulation in LTSpice? How to model a CMOS input?

I am trying to simulate the effect of a PCB trace on a clock signal with LTSpice, see the following pictures: In my quick and dirty setup, the clock receiver is the resistor Rin. I the real world, it ...
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290 views

How does a “bulk connected to input voltage” mos work?

This is the circuit I am supposed to analyze, but I don't understand at transistor level, what does a MOS do when its gate is grounded and its bulk is the input terminal! I mean bulk is tied to Vdd or ...
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45 views

Finding transistor width for equal rise and fall times

I am trying to understand how the below CMOS transistor schematic has approximate equal rise and fall times (resistance pull up equal to resistance pull down) Below is the schematic: I notice that ...
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23 views

CMOS IC Dynamic Edge-Triggered Flip Flop setup and hold time calculation

Before explaining i should point out that i refer to changes of signals in the text as a reference change on which i will calculate these times as 50% change of one signal to 50% change of the other ...
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107 views

Detect Infrared beam projected onto X-Y plane. Save and display coordinates. CMOS sensor?

I'm working on a project in which an IR laser is pointed perpendicular to the surface of an X-Y plane (Think like the old game "Duck Hunt"). I don't know where the IR beam will land on the plane but ...
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This SR latch built with 180nm CMOS does not work in ltspice. How do I fix its behavior and parameters?

EDIT: I copied over the latch from another larger model that had Vdd defined, but missed it when copying over the design. However, after adding in Vdd, I still run into this confusing issue where the ...
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51 views

Understanding CMOS Circuit Behaviour with Resistive Loads using Thevenin theorem

I have been reading the Digital Design: Principles and Practices 3rd Edition as a hobby. Unfortunately, I am stuck at page 103 of Section 3.5.2: Circuit Behavior with Resistive Loads. In Figure 3-27: ...
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446 views

D FLIP FLOP Cadence

Basically I am designing D flip flop. While doing my pre-layout simulations, not getting the output Q for the inputs. See the attached attachments. But when I tried to take the output from CLKPULSE, ...
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72 views

PSPICE simulation

I have a PSPICE file that contains approximately 200+ transistors. Naturally, simulating the whole circuit everytime I make a change takes a while. Is there anyway to run a simulation measuring only ...
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52 views

Bump Circuit in PSPICE

I am designing a bump circuit in PSPICE to determine if two voltages are equal. The schematic is shown in the figure below. The parameters are set in the subthreshold region, with a VDD of 2 volts. ...
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70 views

Dynamic power dissipation of a Cmos inverter with relation to it's geometry

I know that the dynamic power dissipation of a CMOS inverter is defined by the equation: Pd = (Cl)(Vdd^2)(fb). My teacher challenged us to find ways to reduce power dissipation besides the obvious ...
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54 views

How to send to pulses to a CMOS Counter

I have tried to find answers to this many times, and the only solution I have been able to find is having two 555 Timers (or a 556) one in astable, and one in monostable. I could easily do this with ...
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Frequency Divider Analog Circuit issue

I am trying to implement a divide-by-two circuit quoted from the book "Low power CMOS circuits : technology logic design and CAD tools" by Christian Piguet Could anyone advise about the spice error "...
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52 views

MOSFET switching on

I have a doubt. Consider an N-MOSFET: which is the voltage that can switch on it? The voltage between Gate and? Sometimes I read "between Gate and Bulk", sometimes "between Gate and Source", sometimes ...
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259 views

L298 distorts signal

I connected STM32 F334R8 microcontroller to L298 H-bridge. I made some measurements. The problem is output signal on L298 has quite slow slopes and is not as sharp as input signal. I do not understand ...
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Rise and fall times typical values for a switching signal in 90 nm technology

I have fabricated NMOS and PMOS devices on simulation using Silvaco software, the fabricated device (CMOS) is shown below. Now, I want to find the dynamic power dissipation of the CMOS inverter by ...
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leakage power with respect to Switching activity

Can anyone explain me relation of leakage current or power with respect to Switching activity(S.A). I'm assuming that with increase of S.A, the power dissipation of circuit increases in-turn ...
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42 views

dc sweep convergence issue for cmos inverter

I am having some convergence issue with DC sweep for a CMOS inverter. To duplicate the exact issue, see the following log as well as the attached netlist files, together with modelcard.nmos and ...
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Jellybean Radio Button logic Chip

Below is an LTSpice simulation of a 'radio button' circuilt. Ignore the bottom button, I am working on a 'reset' mechanism to unlatch any of the other buttons. The idea is that the button you push, ...
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Is a cascode better current source than current mirror ? Which option is better?

I have simulated a cascode and made a M2 in saturation so it will act as a current source. I want to understand which current source is better. Is cascode better because it has a higher output ...
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588 views

Worst case delay for a CMOS gate

I want to determine the input pattern for the worst case tpHL of this CMOS gate. I think there may be more than one input pattern that give worst case tpHL. The following is my reasoning: The ...
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Why doesn't the output of the rectifier come out?

Hello, I made a rectifier circuit. I also include a comparator. I referred to this paper --> An ultra-low-voltage self-powered energy harvesting rectifier with digital switch control. The circuit ...
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332 views

DC Analysis of CMOS-inverter

I am studying about CMOS inverter and in my book provided the transfer characteristic as follows (actually i simulated it): and then I changed the parameters and I got something like this: I found ...
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260 views

Latch-Up in CMOS Design

I am currently stock on a concept I should understand but I cannot get my head around it quite yet: "Latch-up" in CMOS devices. It is a condition where a significant amount of current flows through ...
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342 views

Cross coupled-gm boosting stage

From this paper, a wideband differential LNA is proposed with structure below: The first stage is called "cross coupled- gm boosting stage". I am wondering if there is a mistake here. As seen from ...
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325 views

Negative Charge Pump- How to analyze this?

I am using CMOS 4069 inverter and wired up this circuit. I want to generate a \$-V_{dd}\$ negative pulse and \$2V_{dd}\$ positive pulse. The circuit above is for the negative voltage. However, I get ...
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CMOS op amp subtractor deviation

I constructed a single stage differential amp and used it to make a subtractor. The input amplitudes are 2 mV and 3 mV, however the output is about 1.4 mV. Can anyone tell me why?
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What is the best way to take multiple near-simultaneous pictures from 6 cameras on a development board?

I thought I could use a powered usb hub, connect the 6 cameras to it, connect the hub to the raspberry pi and capture the images one after the other quickly using the motion package. But I can't find ...
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70 views

opamp constant-gm bias circuit

I try to incorporate the constant-gm bias circuit (Figure 6 in Improvements_in_biasing_and_compensation_of_CMOS_opamp) into the PFC (positive feedback frequency compensation) opamp, but it resulted in ...
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Can the scanning speed of an electronic rolling shutter CMOS sensor be controlled?

I'm not certain I'm asking this correctly as I don't entirely understand how such a camera sensor works, so help me out with a couple of areas please! I want to program something that makes use of ...
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Performance issues when using CMOS SR Latch with 180nm transistor models in circuit simulator

I am trying to incorporate a CMOS SR latch made with 180nm Level +49 transistors into a larger circuit but am running into issues. I am hoping this community can point me in the right direction of ...
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Drain capacitance of CMOS inverter

How to find the total drain( NMOS+PMOS) capacitance of CMOS inverter in cadence virtuoso?
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CMOS Inverter output for a given transfer characteristics

I have tried solving the below CMOS problem with a given transfer characteristics but my answer is wrong. Answer should be 0.25. Could someone please point out where I went wrong ?
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How does this circuit with inverters work?

What this does this circuit do? I suspect it is an amplifier, but don't know how it amplifies. For example Inv 5 and Inv 6 are connected in parallel with reverse sides but there is a wire between ...
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How can I reduce loading effect in dc common drain source follower?

I want to make a dc voltage buffer using an nmos source follower. I found that by making Rs as large as possible or even open, Vs= Vgs-Vth. I verified it using multisim. The problem is it suffers from ...
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Why does this spice simulation produce a strange output?

I tried to design a CMOS inverter in LayoutEditor schematic editor and tried to simulate the generated spice file on LTSpice and the resulting output was not what I expected. For the simple DC sweep ...
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Need help understanding a fairly vague solution to example problem (the topic is noise in CMOS circuits)

So I have the solution to the following example problem I am working on: Now the issue is that I am trying to understand the solution I was given: The thing is this solution is simply quite vague. ...
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How CMOS transistors might be used as a capacitive sensor for biopotential?

I was wondering how CMOS-based capacitive electrodes might be designed (e.g. in this article I stumbled on). It seems to me, that it would make sense to capacitively couple the input of the transistor ...
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181 views

Digital output won't go from 5V to 0V with a diode attached

Edit I did a poor job of soldering and forgot to solder the pull-down resistor on the input to the buffer. My mistake for posting a question too soon. I built a circuit to read a button with a ...
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Source/Sink on 74AHCT2G125DC not driving WS2712bs

Per advice in this post I am using a 74AHCT2G125DC (datasheet) to drive a Neopixel/WS2812b strip's data pin from a 3.3v MCU. The MCU is driving A1, and the addressable LEDs are chained from Y1. VCC on ...
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CMOS Circuit, Finding Output Switching Frequency

I'm tasked to analyze the power usage of a CMOS circuit, but I cannot figure out the output switching frequency. Every 10ns, the circuit is stimulated with input vectors 1110, 1111, 1101, 1111, ...
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109 views

Turning on/off MOSFET using 4000 series CMOS

I intend to use 4000 series CMOS running at 12V to turn on some power MOSFETs (SUM55P06 and IRF2903) handling 8A at 12V. However, the arrangement of logic gates I need to simplify the driving s/w ...
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Switching another circuit that has high current

I'm trying to use a Raspberry Pi to switch on and off another circuit. This other circuit draws a LOT of current, so I'm using a power supply dedicated to that load. I tried to do a simple op-amp ...
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Connect bulk in diode-connected transistor in synchronous rectifier

The diode-connected transistor is used for synchronous rectifier. I have just drawn bulk diode as below. The fist one is mosfet with its bulk-source, bulk-drain diodes. Second and third pictures are ...
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Common source circuit with current source and diode connected load

Could anyone explain why the output bias voltage of the common source in figure a is not well defined and needs a common mode feedback while the circuit in figure b is well defined? Here is what I ...
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Small signal analysis common source

I'm trying to get the small signal model for this circuit: This is my attempt I'm not sure where W1 should go. Should it be shorting out RD? Also R2 = RD on this circuit diagram