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Questions tagged [cmos]

"Complementary Metal-Oxide Semiconductor" is a process which implements a combination of PMOS and NMOS transistors. Most current digital logic is implemented in CMOS. Its cost-effectiveness due to being so widespread means many other applications have become common as well, such as in analog design, image sensors, telecommunication, etc.

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Practical ESD protection without latchup

My understanding has always been that any CMOS I/O pin needs external ESD protection - since the on-chip protection diodes are only there to guard against ESD events during manufacture handling. ...
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286 views

L298 distorts signal

I connected STM32 F334R8 microcontroller to L298 H-bridge. I made some measurements. The problem is output signal on L298 has quite slow slopes and is not as sharp as input signal. I do not understand ...
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313 views

Rise and fall times typical values for a switching signal in 90 nm technology

I have fabricated NMOS and PMOS devices on simulation using Silvaco software, the fabricated device (CMOS) is shown below. Now, I want to find the dynamic power dissipation of the CMOS inverter by ...
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46 views

What is the actual cmos technology node of China and Russia not licensing major process technology from outside?

There are a number of Russian fabs but from what I can see they are just using liscened technology ie Sitronics using STmicroelectronics at 90nm node or Angstrem-T using AMD see yet in the past there ...
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1answer
83 views

LNA circuit not working

I am trying to simulate a LNA circuit from the book "Design of CMOS RF Integrated Circuits and Systems" However, the LNA circuit still does not give POSITIVE GAIN. Any help ?
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1answer
97 views

Calculating Rs Value for 32kHz Pierce-Gate Crystal Oscillator Circuit

Edit: My primary objective is to learn the mathematical model to compute the load resistor \$R_s\$ to satisfy a given crystal's drive level, not just fixing the one instance below. I'm building a ...
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1answer
35 views

Uncertainty(jitter) in setup and hold calculation

In setup calculation, the launch flop is triggered by 1st edge and capture flop is triggered by next edge. And in calculation we take jitter into account only for the clock path of capture flop. There ...
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24 views

What is propagation delay in cmos nets?

I have read somewhere that signal travels as electromagnetic waves in wires near to speed of light. The signals are brought to destination by EM waves. Then what does electrons do? If signals travel ...
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24 views

leakage power with respect to Switching activity

Can anyone explain me relation of leakage current or power with respect to Switching activity(S.A). I'm assuming that with increase of S.A, the power dissipation of circuit increases in-turn ...
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0answers
48 views

dc sweep convergence issue for cmos inverter

I am having some convergence issue with DC sweep for a CMOS inverter. To duplicate the exact issue, see the following log as well as the attached netlist files, together with modelcard.nmos and ...
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0answers
80 views

Jellybean Radio Button logic Chip

Below is an LTSpice simulation of a 'radio button' circuilt. Ignore the bottom button, I am working on a 'reset' mechanism to unlatch any of the other buttons. The idea is that the button you push, ...
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0answers
63 views

Is a cascode better current source than current mirror ? Which option is better?

I have simulated a cascode and made a M2 in saturation so it will act as a current source. I want to understand which current source is better. Is cascode better because it has a higher output ...
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649 views

Worst case delay for a CMOS gate

I want to determine the input pattern for the worst case tpHL of this CMOS gate. I think there may be more than one input pattern that give worst case tpHL. The following is my reasoning: The ...
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3answers
214 views

Differential Amplifier with Hard Limiting

I'm currently going through RF Microelectronics by Razavi. In chapter 3 he presents an example where the following signal is applied to a differential amplifier with a tail current source. $$Acos(...
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1answer
82 views

Logical effort and delay estimation

So as I have understood the logical effort for a 2 input nand gate with only one of the inputs active = 4/3. Furthermore the net logical effort is 8/3 (considering both the inputs). Now given that the ...
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0answers
62 views

Why doesn't the output of the rectifier come out?

Hello, I made a rectifier circuit. I also include a comparator. I referred to this paper --> An ultra-low-voltage self-powered energy harvesting rectifier with digital switch control. The circuit ...
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345 views

DC Analysis of CMOS-inverter

I am studying about CMOS inverter and in my book provided the transfer characteristic as follows (actually i simulated it): and then I changed the parameters and I got something like this: I found ...
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276 views

Latch-Up in CMOS Design

I am currently stock on a concept I should understand but I cannot get my head around it quite yet: "Latch-up" in CMOS devices. It is a condition where a significant amount of current flows through ...
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386 views

Cross coupled-gm boosting stage

From this paper, a wideband differential LNA is proposed with structure below: The first stage is called "cross coupled- gm boosting stage". I am wondering if there is a mistake here. As seen from ...
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384 views

Negative Charge Pump- How to analyze this?

I am using CMOS 4069 inverter and wired up this circuit. I want to generate a \$-V_{dd}\$ negative pulse and \$2V_{dd}\$ positive pulse. The circuit above is for the negative voltage. However, I get ...
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94 views

CMOS op amp subtractor deviation

I constructed a single stage differential amp and used it to make a subtractor. The input amplitudes are 2 mV and 3 mV, however the output is about 1.4 mV. Can anyone tell me why?
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361 views

What is the best way to take multiple near-simultaneous pictures from 6 cameras on a development board?

I thought I could use a powered usb hub, connect the 6 cameras to it, connect the hub to the raspberry pi and capture the images one after the other quickly using the motion package. But I can't find ...
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1answer
121 views

Diffusion capacitence

I am trying to figure out the capacitance seen at each node, given that the source and drain diffusion capacitance is shared in the nmos stack. Given that the fingered layout uses a finger width of W=...
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1answer
1k views

Transmission line simulation in LTSpice? How to model a CMOS input?

I am trying to simulate the effect of a PCB trace on a clock signal with LTSpice, see the following pictures: In my quick and dirty setup, the clock receiver is the resistor Rin. I the real world, it ...
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1answer
26 views

What does worst-case gate capacitance mean in a MOS transistor?

I have searched the statement; MOS worst-case gate capacitance in various forms but no avail. Keep in mind I'm a student. The course I am taking has no reference material. With note slides with ...
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32 views

How to connect a CMOS sensor to a OLED display?

I'm going to ask something I didn't find. Also my level of knowledge is basic, so I would appreciate the help. Do you know to connect a CMOS sensor like this: https://www.aliexpress.com/item/...
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1answer
25 views

FIFO Clock Setup for CMOS Detector

When attempting to construct a miniature laser beam profiler with the Omnivision OV7740 CMOS detector and an Arduino Due, I am running into some problems with FIFO reading/writing. From the datasheet, ...
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20 views

Short Channel MOSFET model

I was reading on a book (Thomas Lee, The Design of CMOS Radio Frequency Integrated Circuits) that in a short channel model, since the phenomenon of drift speed saturation is very relevant, it is a ...
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1answer
26 views

Finding node voltages in a MOSFET circuit

simulate this circuit – Schematic created using CircuitLab Considering Vdd=5v I want to calculate the node voltages at P,Q and R.
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1answer
35 views

Deriving PU / PD given a sketch of a PMOS

For the PMOS given below I can derive the function f, such that f inverted in its variables corresponds to the expression of PMOS(f) and f inverted equals NMOS(f). For this specific problem I have ...
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46 views

MOSFET input and output capacitances

I need some explanations about the MOSFET parasitic capacitances. Precisely, what I studied is that there are those parasitic capacitances: But generally in digital electronics texts I see that they ...
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1answer
48 views

Effects of input capacitance on propagation delay (with Logical Effort analysis)

Let's consider the logical effort methodology for the propagation delay's computation. Here there are some informations (https://en.wikipedia.org/wiki/Logical_effort). Let's consider a generic CMOS ...
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83 views

Deciding between ULN2804 or ULN2803 with 74HC595

I'm making a circuit with Arduino + 74HC595 + (ULN2804 / ULN2803) to drive a few 12 V Motors. I'm trying to decide whether to use the ULN2804 or ULN2804. On testing, performance of both is fine, ...
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47 views

Can I use Highspeed Opamp as differential clock driver?

I want to use high speed Opamp LT1364 as +/- 15V clock driver of same voltage instead of typical CMOS / CCD clock drivers with lower voltage and slew rate. CMRR : 90dB PSRR : 100dB Slew rate : 1kV/uS ...
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2answers
77 views

Mosfet Threshold Voltage

from MOS theory we know that, in case of a P substrate, a Gate-Bulk voltage higher than a certain threshold value creates an inversion layer, in this case made of negative charges. This is also ...
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1answer
53 views

Fundamental CMOS astable multivibrator

So i need to perform analysis of simple astable multivibrator circuit shown in the following picture: These Vdd and GND are just the power rails of those CMOS inverters. Now, i need to perform ...
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43 views

Obtaining D flip-flop mosfet-level schematics from CMOS layout

Could anyone help to derive D flip-flop mosfet-level schematics from the following CMOS layout described in this conference document : Open Cell Library in 15nm FreePDK Technology ?
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1answer
37 views

Mos circuit amplifier with multiple stages , overall gain

I have the following circuit and i am trying to find uin/vout. My thought process is that M3-M4 is a Cmos inverter so i can calculate the gain until that point as A1= -gm3(ro3//ro5) How can i find the ...
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1answer
186 views

Finding transistor width for equal rise and fall times

I am trying to understand how the below CMOS transistor schematic has approximate equal rise and fall times (resistance pull up equal to resistance pull down) Below is the schematic: I notice that ...
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1answer
28 views

CMOS IC Dynamic Edge-Triggered Flip Flop setup and hold time calculation

Before explaining i should point out that i refer to changes of signals in the text as a reference change on which i will calculate these times as 50% change of one signal to 50% change of the other ...
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91 views

opamp constant-gm bias circuit

I try to incorporate the constant-gm bias circuit (Figure 6 in Improvements_in_biasing_and_compensation_of_CMOS_opamp) into the PFC (positive feedback frequency compensation) opamp, but it resulted in ...
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26 views

Can the scanning speed of an electronic rolling shutter CMOS sensor be controlled?

I'm not certain I'm asking this correctly as I don't entirely understand how such a camera sensor works, so help me out with a couple of areas please! I want to program something that makes use of ...
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2answers
123 views

CMOS Inverter Circuit Analysis

So I have a circuit shown below, that looks to me likes it's a CMOS inverter circuit. In this question, we're asked to find the current and voltage across drain-source voltage of the NMOS component. ...
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2answers
59 views

Single Stage Amplifier CMOS - Biasing Issues

So this is kind of vague question. I'm wondering what the approach to biasing MOSFETs in saturation is. For the following circuit, I really have no specifications - I'm just trying to play around ...
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1answer
65 views

This SR latch built with 180nm CMOS does not work in ltspice. How do I fix its behavior and parameters?

EDIT: I copied over the latch from another larger model that had Vdd defined, but missed it when copying over the design. However, after adding in Vdd, I still run into this confusing issue where the ...
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71 views

Performance issues when using CMOS SR Latch with 180nm transistor models in circuit simulator

I am trying to incorporate a CMOS SR latch made with 180nm Level +49 transistors into a larger circuit but am running into issues. I am hoping this community can point me in the right direction of ...
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21 views

Drain capacitance of CMOS inverter

How to find the total drain( NMOS+PMOS) capacitance of CMOS inverter in cadence virtuoso?
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42 views

CMOS Inverter output for a given transfer characteristics

I have tried solving the below CMOS problem with a given transfer characteristics but my answer is wrong. Answer should be 0.25. Could someone please point out where I went wrong ?
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81 views

How does this circuit with inverters work?

What this does this circuit do? I suspect it is an amplifier, but don't know how it amplifies. For example Inv 5 and Inv 6 are connected in parallel with reverse sides but there is a wire between ...
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1answer
68 views

Understanding CMOS Circuit Behaviour with Resistive Loads using Thevenin theorem

I have been reading the Digital Design: Principles and Practices 3rd Edition as a hobby. Unfortunately, I am stuck at page 103 of Section 3.5.2: Circuit Behavior with Resistive Loads. In Figure 3-27: ...