Questions tagged [cmos]

"Complementary Metal-Oxide Semiconductor" is a process which implements a combination of PMOS and NMOS transistors. Most current digital logic is implemented in CMOS. Its cost-effectiveness due to being so widespread means many other applications have become common as well, such as in analog design, image sensors, telecommunication, etc.

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Current mirrors inside an OTA (Operational Transconductance Amplifier)

let's consider this transconductance amplifier (OTA) (reference): I have a very basic question. Why do wee need the mirrors M5,M6,M7,M8,M10? Why is the output taken from that current source? Why ...
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Difference between transfer gate and NMOS switch in CMOS image sensors

I would like to know the difference between the transfer gate (TX) which is used in 4T CMOS Active Pixel Sensor (APS) as mentioned in the below image and a normal NMOS switch. As far as I know, the ...
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LDO transient performance enhancement circuit understanding

For the following LDO circuit, how does the transient performance enhancement circuit sub-block in green color works ?
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Modelling effects of unbuffered library characterization cell outputs on timing constraint tables

Can someone explain to me or point me to a resource that will shed some light on how (instead of using a buffered library cell, we use a unbuffered library cell) including the effects of unbuffered ...
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List of output currents in test conditions in CMOS buffer's datasheets

in datasheets of commonly used CMOS buffers output low voltages are given at specific currents (100uA, 4mA, 8mA, 12mA, 16mA). 100uA current shows that the buffer has CMOS output driver, but i still ...
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Two Stage CMOS Operational Amplifier

While learning about two stage CMOS operational amplifier it is mentioned that the there is a phase shift of about -90 degrees so is there always a phase shift between an input and output signal? and ...
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Simulation LTSpice a two stages Operational Amplifier with CMOS

I need to simulate this circuit on LTspice. In the exercise I have to balance the parameter to makes it work and estimate the gain in the center of the band. The inputs are v+ and v- (differential ...
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79 views

CMOS Flip-Flop Design

I'm new in Transistor-Level Design and for that reason, I have practiced and learned from designs that I found on google. When I tried to design a mux from scratch without relying on the design of ...
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What happens to the body effect and the channel length modulation for the short channel devices?

Does body effect and channel length modulation effective for both, short and long channel devices?
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What is the resulting Voltage Transfer characteristics of the modified CMOS-inverter circuit if NMOS and PMOS are interchanged?

What is the resulting Voltage Transfer characteristics of the modified CMOS-inverter circuit, if the positions of \$NMOS\$ and \$PMOS\$ are interchanged?
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Minimum number of transistors to implement cmos logic of this function

I have designed the following circuit to implement cmos logic of : \$out=\overline{(a+b).\overline{c}+e.(\overline{f}+\overline{g})}\$ I’m looking for optimal circuit with minumum number of ...
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What is the pad-etching process in standard CMOS fabrication process

What is the pad etching process? Is it possible to etch to the bottom metal layers or vias in standard CMOS fabrication?
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38 views

Is there such a thing as analog and digital compatible cmos or ccd sensors?

I'm way over my head with this one but I am trying to learn about cmos/ccd(preferred) sensors in order to build my own camera. Looking to get analog video from a sensor in a very small package size &...
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size pmos and Nmos in inverter for same rise and fall time

I want to design a minimum sized CMOS inverter with same rise/fall time. I am making use of 45nm technology(FREEPDK45). If i make the NMOS minimum width size, so 90nm. I don't know how to define the ...
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32 views

dynamic charge sharing between multiple gates

Based on this video: https://www.youtube.com/watch?v=CN4oIcAPIV4 hopefully it is legitimate I understand what is being done here. However, I don't understand it well enough for a more complex case ...
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What are the most common compounds used today in CMOS IC pn junctions?

Many many moons ago I was using germanium-based transistors but I know we have been able to exponentially speed up switching response times with newer doping compounds. I believe newer IC’s also ...
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FIFO Clock Setup for CMOS Detector

When attempting to construct a miniature laser beam profiler with the Omnivision OV7740 CMOS detector and an Arduino Due, I am running into some problems with FIFO reading/writing. From the datasheet, ...
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Short Channel MOSFET model

I was reading on a book (Thomas Lee, The Design of CMOS Radio Frequency Integrated Circuits) that in a short channel model, since the phenomenon of drift speed saturation is very relevant, it is a ...
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50 views

Finding node voltages in a MOSFET circuit

simulate this circuit – Schematic created using CircuitLab Considering Vdd=5v I want to calculate the node voltages at P,Q and R.
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Deriving PU / PD given a sketch of a PMOS

For the PMOS given below I can derive the function f, such that f inverted in its variables corresponds to the expression of PMOS(f) and f inverted equals NMOS(f). For this specific problem I have ...
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170 views

MOSFET input and output capacitances

I need some explanations about the MOSFET parasitic capacitances. Precisely, what I studied is that there are those parasitic capacitances: But generally in digital electronics texts I see that they ...
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Effects of input capacitance on propagation delay (with Logical Effort analysis)

Let's consider the logical effort methodology for the propagation delay's computation. Here there are some informations (https://en.wikipedia.org/wiki/Logical_effort). Let's consider a generic CMOS ...
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176 views

Deciding between ULN2804 or ULN2803 with 74HC595

I'm making a circuit with Arduino + 74HC595 + (ULN2804 / ULN2803) to drive a few 12 V Motors. I'm trying to decide whether to use the ULN2804 or ULN2804. On testing, performance of both is fine, ...
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Can I use Highspeed Opamp as differential clock driver?

I want to use high speed Opamp LT1364 as +/- 15V clock driver of same voltage instead of typical CMOS / CCD clock drivers with lower voltage and slew rate. CMRR : 90dB PSRR : 100dB Slew rate : 1kV/uS ...
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170 views

Mosfet Threshold Voltage

from MOS theory we know that, in case of a P substrate, a Gate-Bulk voltage higher than a certain threshold value creates an inversion layer, in this case made of negative charges. This is also ...
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Obtaining D flip-flop mosfet-level schematics from CMOS layout

Could anyone help to derive D flip-flop mosfet-level schematics from the following CMOS layout described in this conference document : Open Cell Library in 15nm FreePDK Technology ?
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Mos circuit amplifier with multiple stages , overall gain

I have the following circuit and i am trying to find uin/vout. My thought process is that M3-M4 is a Cmos inverter so i can calculate the gain until that point as A1= -gm3(ro3//ro5) How can i find the ...
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508 views

Finding transistor width for equal rise and fall times

I am trying to understand how the below CMOS transistor schematic has approximate equal rise and fall times (resistance pull up equal to resistance pull down) Below is the schematic: I notice that ...
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CMOS IC Dynamic Edge-Triggered Flip Flop setup and hold time calculation

Before explaining i should point out that i refer to changes of signals in the text as a reference change on which i will calculate these times as 50% change of one signal to 50% change of the other ...
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114 views

opamp constant-gm bias circuit

I try to incorporate the constant-gm bias circuit (Figure 6 in Improvements_in_biasing_and_compensation_of_CMOS_opamp) into the PFC (positive feedback frequency compensation) opamp, but it resulted in ...
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219 views

CMOS Inverter Circuit Analysis

So I have a circuit shown below, that looks to me likes it's a CMOS inverter circuit. In this question, we're asked to find the current and voltage across drain-source voltage of the NMOS component. ...
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Single Stage Amplifier CMOS - Biasing Issues

So this is kind of vague question. I'm wondering what the approach to biasing MOSFETs in saturation is. For the following circuit, I really have no specifications - I'm just trying to play around ...
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This SR latch built with 180nm CMOS does not work in ltspice. How do I fix its behavior and parameters?

EDIT: I copied over the latch from another larger model that had Vdd defined, but missed it when copying over the design. However, after adding in Vdd, I still run into this confusing issue where the ...
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Performance issues when using CMOS SR Latch with 180nm transistor models in circuit simulator

I am trying to incorporate a CMOS SR latch made with 180nm Level +49 transistors into a larger circuit but am running into issues. I am hoping this community can point me in the right direction of ...
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110 views

How does this circuit with inverters work?

What this does this circuit do? I suspect it is an amplifier, but don't know how it amplifies. For example Inv 5 and Inv 6 are connected in parallel with reverse sides but there is a wire between ...
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195 views

74AS TTL to CMOS pull up resistor and maximum speed (or lowest delay)

Hello I have to pilot a CMOS input 5V chip device with a 7474 flip flop with the lowest possible delay to minimize clock jitter. Signal is about 11.3 Mhz I have two options: 1) 74HC74 (CMOS ...
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How can I reduce loading effect in dc common drain source follower?

I want to make a dc voltage buffer using an nmos source follower. I found that by making Rs as large as possible or even open, Vs= Vgs-Vth. I verified it using multisim. The problem is it suffers from ...
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D FLIP FLOP Cadence

Basically I am designing D flip flop. While doing my pre-layout simulations, not getting the output Q for the inputs. See the attached attachments. But when I tried to take the output from CLKPULSE, ...
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PSPICE simulation

I have a PSPICE file that contains approximately 200+ transistors. Naturally, simulating the whole circuit everytime I make a change takes a while. Is there anyway to run a simulation measuring only ...
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Bump Circuit in PSPICE

I am designing a bump circuit in PSPICE to determine if two voltages are equal. The schematic is shown in the figure below. The parameters are set in the subthreshold region, with a VDD of 2 volts. ...
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91 views

Dynamic power dissipation of a Cmos inverter with relation to it's geometry

I know that the dynamic power dissipation of a CMOS inverter is defined by the equation: Pd = (Cl)(Vdd^2)(fb). My teacher challenged us to find ways to reduce power dissipation besides the obvious ...
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How to send to pulses to a CMOS Counter

I have tried to find answers to this many times, and the only solution I have been able to find is having two 555 Timers (or a 556) one in astable, and one in monostable. I could easily do this with ...
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Deriving the Transistor Width for NOR

I'm an undergraduate electrical engineer and my universities notes are not the best, I have an assignment in which I do not want the answers to but the question has given me the oxide capacitance, ...
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552 views

Depletion mosfet inverter

I know that if both transistor in a cmos inverter are enhancement then the output will be as shown in the figure: But I wonder, what if one of them is enhancement and the other is Depletion?
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Arduino/Mosfet control of CMOS logic chip

So I've found a basic composite video "synth" which I'm trying to manipulate with an arduino. The device was originally controlled by NO tact switches between pins on the CMOS MCU, a Signetics ...
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Why does this spice simulation produce a strange output?

I tried to design a CMOS inverter in LayoutEditor schematic editor and tried to simulate the generated spice file on LTSpice and the resulting output was not what I expected. For the simple DC sweep ...
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Need help understanding a fairly vague solution to example problem (the topic is noise in CMOS circuits)

So I have the solution to the following example problem I am working on: Now the issue is that I am trying to understand the solution I was given: The thing is this solution is simply quite vague. ...
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Looking for the logical equation from this PMOS circuit

I am looking for the logical equation that describes the given circuit below. Unfortunately I don't have information whether \$U_b\$ is positive or negative - would that make a difference? I derived ...
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How CMOS transistors might be used as a capacitive sensor for biopotential?

I was wondering how CMOS-based capacitive electrodes might be designed (e.g. in this article I stumbled on). It seems to me, that it would make sense to capacitively couple the input of the transistor ...
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252 views

Inversion Coefficient Based Design in CMOS amplifiers

I have designed amplifiers, using potential division method. What are the steps to design differential amplifier using inversion coefficient based design methodology? Please provide links/...