Questions tagged [cmos]

"Complementary Metal-Oxide Semiconductor" is a process which implements a combination of PMOS and NMOS transistors. Most current digital logic is implemented in CMOS. Its cost-effectiveness due to being so widespread means many other applications have become common as well, such as in analog design, image sensors, telecommunication, etc.

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Differential Amplifier with Hard Limiting

I'm currently going through RF Microelectronics by Razavi. In chapter 3 he presents an example where the following signal is applied to a differential amplifier with a tail current source. $$Acos(...
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2answers
80 views

CMOS Inverter Circuit Analysis

So I have a circuit shown below, that looks to me likes it's a CMOS inverter circuit. In this question, we're asked to find the current and voltage across drain-source voltage of the NMOS component. ...
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Single Stage Amplifier CMOS - Biasing Issues

So this is kind of vague question. I'm wondering what the approach to biasing MOSFETs in saturation is. For the following circuit, I really have no specifications - I'm just trying to play around ...
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78 views

74AS TTL to CMOS pull up resistor and maximum speed (or lowest delay)

Hello I have to pilot a CMOS input 5V chip device with a 7474 flip flop with the lowest possible delay to minimize clock jitter. Signal is about 11.3 Mhz I have two options: 1) 74HC74 (CMOS ...
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367 views

Depletion mosfet inverter

I know that if both transistor in a cmos inverter are enhancement then the output will be as shown in the figure: But I wonder, what if one of them is enhancement and the other is Depletion?
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71 views

Dynamic power dissipation of a Cmos inverter with relation to it's geometry

I know that the dynamic power dissipation of a CMOS inverter is defined by the equation: Pd = (Cl)(Vdd^2)(fb). My teacher challenged us to find ways to reduce power dissipation besides the obvious ...
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1answer
59 views

How to send to pulses to a CMOS Counter

I have tried to find answers to this many times, and the only solution I have been able to find is having two 555 Timers (or a 556) one in astable, and one in monostable. I could easily do this with ...
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34 views

Deriving the Transistor Width for NOR

I'm an undergraduate electrical engineer and my universities notes are not the best, I have an assignment in which I do not want the answers to but the question has given me the oxide capacitance, ...
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1answer
300 views

Why not switching extra inverters with opposite MOSFETs in CMOS XOR gate?

Below you can see a CMOS XOR gate. I wonder why we do not change extra inverters like A' or B' with opposite MOSFETs. For example, could not we just put the green construction in the place of red ...
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1k views

Can I create a CMOS AND gate with 2 serial n-type and 2 paralel p-type CMOS transistors?

So I know that a CMOS AND gate is made with 2 parallel p-type transistors and 2 serial n-type transistors and an inverter on the output. But can we just make the AND gate similar to the NOR gate -...
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1answer
149 views

Arduino/Mosfet control of CMOS logic chip

So I've found a basic composite video "synth" which I'm trying to manipulate with an arduino. The device was originally controlled by NO tact switches between pins on the CMOS MCU, a Signetics ...
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1answer
44 views

Looking for the logical equation from this PMOS circuit

I am looking for the logical equation that describes the given circuit below. Unfortunately I don't have information whether \$U_b\$ is positive or negative - would that make a difference? I derived ...
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1answer
126 views

How can I have an ECL logic input for a CMOS logic gate

I'm working on a triggering system that uses a comparator to check if the signal is below a threshold value. I found a great comparator for the job, except its output is ECL logic. I wanted to use the ...
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1answer
221 views

Inversion Coefficient Based Design in CMOS amplifiers

I have designed amplifiers, using potential division method. What are the steps to design differential amplifier using inversion coefficient based design methodology? Please provide links/...
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1answer
74 views

multiplexer with floating outputs

I have actually a solution based on a multiplexer (CD4051) which drives 8 outputs, either at 0V or 3.3V (the input is at 3.3V). Each output of the multiplexer drive a NMOS and the goal is to have a ...
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432 views

Design CMOS comparator

I made the circuit. like this paper, But It's not working. When you insert the AC input, a square waveform should appear. I can not interpret the circuit well. If you know anything, please answer ...
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1answer
1k views

normalized parasitic delay

I am confused why many books and sites call normalized parasitic delay as " ratio of diffusion capacitance to gate capacitance in a particular process" . According to me its delay of gate when it ...
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1answer
568 views

How can I use a NPN transistors to convert from 3.3v to VCC (3.9-3.0v)

I'm wanting to drive a NeoPixel from a CMOS device. The power for the neopixel is a 4v LiPo battery and will fall from around 3.9v to 3v before it cuts off. I have a few PN2222 NPN transistors, I'm ...
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CMOS LOGIC GATE DIAGRAM

I have my solution for the logic gate diagram to implement the function f=(a+(b*(c+d)))' Would anyone be able to confirm if this is legitimate?
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How to draw stick diagram of a function

I am a student of computer science and engineering. We have VLSI design in current semester. Now i am having trouble drawing stick diagram for a given equation. What is the step by step procedure for ...