Questions tagged [computer-architecture]

Computer architecture refers to both the design of a computer's external interfaces (instruction sets) and a computer's internal implementation (microarchitecture). The goal of these design decisions is to optimize speed, power efficiency, size, or cost while satisfying constraints on the rest.

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DRAM Self-Refresh not the Lowest Power Mode

I have a DDR3L Samsung DRAM on my Laptop. Based on page 23 of its datasheet, IDD6 or the ...
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parallel snooping and processor requests - Design bug

In a multicore, MESI based cache coherent system what happens if there are parallel processor and snoop requests that affect the same address? Consider the following case CPU0 writes to an address ...
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MESI based MULTICORE cache coherent system - bug issue

For this particular architectural design, in general, what happens when there are parallel processor and snoop side requests? How is such a corner case handled? We have the following information about ...
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DMA SPI performance

I am currently writing an SD card driver for a Microcontroller using SPI and DMA. The SPI has a FIFO that can store 4 data values from the data register which has the capable of storing 32 bit. But it ...
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What are common ways that modern processors handle data hazards with asynchronous registers

I'm trying to design a processor in VHDL. While the base instruction set is done, I'm having trouble building on top of it. Specifically, I'm implementing control and status registers (CSRs), which ...
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How to use only BEQ to perform other conditional branch

Given "Branch if equal(BEQ)" as the only conditional branch and other instruction like arithmetic and unconditional branch instructions, is it possible to perform other conditional branching like ...
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1answer
77 views

Do 64-bit CPUs consume more power than 32-bit ones?

In this lecture about efficient computing for deep learning, the benchmarks show a 3-fold increase in power usage between 8-bit and 32-bit addition operations. Between 8-bit and 32-bit multiplication, ...
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3answers
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Why is GPU memory fixed? [closed]

In pretty much all modern computers and mobile devices, the CPU can have varying amounts of memory (either to be configured by the user or fixed at point of assembly). Apart from historical form-...
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Why do computer circuits tend to have so many resistors and capacitors? [duplicate]

As someone who has a decent understanding of computer architecture (but not of electrical engineering) I've always wondered why computer circuits tend to have so many resistors, capacitors, and other ...
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Computer Instruction Format - Calculating the number of Opcodes

I found the following question on a different site: A processor has 64 registers and uses 16-bit instruction format. It has two types of instructions: I-type and R-type. Each I-type instruction ...
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In Directed-mapped cache, a problem in exercise!

5.2 Caches are important to providing a high-performance memory hierarchy to processors. Below is a list of 32-bit memory address references, given as word addresses. 3, 180, 43, 2, 191, 88, ...
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Exercise in cache, in particular about AMAT

I have a question in computer organization and Design textbook, Tutorial 5.6 (b) p. 487, 5.7. In this exercise, cache access time is proportional to capacity. Assume that main memory accesses take ...
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A problem dealing with a two-way set-associative cache

This is Problem 13-4 from the book "Logic and Computer Design Fundamentals" by M. Morris Mano and Charles R. Kime. I did the problem. I would like somebody to confirm that my answer is correct or tell ...
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A Problem dealing with Cache memory on a computer

This is Problem 13-3 from the book "Logic and Computer Design Fundamentals" by M. Morris Mano and Charles R. Kime. I believe I have the answer right for part a and part b. That is, they match the ...
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5answers
540 views

How does a microprocessor control its transistors? [closed]

Or in other words, what is the more fundamental building block of an IC below transistors? When I load a code onto my microprocessor, how (fundamentally, sure some people here could write books about ...
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2answers
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What does “Cycle \$\mu\$s” mean in this context?

I'm reading a paper about the architecture of the IBM system/360. There is a diagram which lays out the machine structure and implementation in the storage and control tables there is a metric which I ...
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1answer
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Need Help Identifying [closed]

This is a Board off a 8tb WD Hard Drive. I plug in the wrong power and i believe the little thing with the S on it is bad. I do not know what it is call or where i could find another, any help would ...
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Register File Writeback Scheduling - CPU Architecture

I'm designing a single issue, out of order CPU (modified from a single-issue in-order RISCV CPU). One of the problems I'm struggling to solve is how to schedule the writebacks to the register file to ...
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23 views

Cache Memory Read and Write Miss/hit policies: details of a real processor

All the references I have checked so far explain the Read Miss,Write Hit/Miss policies at the same level of detail. I understand their concepts but I am looking for more details on their ...
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1answer
83 views

MIPS clock cycle calculation formula

How many clock cycles will take execution of this segment on the simple pipeline without forwarding or bypassing when result of the branch instruction (new PC content) is available after WB stage. ...
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1answer
92 views

How does a computer shutdown really work [closed]

I don't know if this is the right place to ask, but i'm asking anyway. How does a computer shutdown really work? I want to know the electronics (or physics) behind it. Like, how does a system signal ...
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42 views

Why is a Flush needed in the MSI cache coherency protocol when moving from Modified to Invalid?

While studying the MSI protocol as described in different sources such as: https://en.wikipedia.org/w/index.php?title=MSI_protocol&oldid=941977299 http://courses.csail.mit.edu/6.888/spring13/...
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5answers
272 views

Has a CPU with Highlevel language (C/C++) as machine code ever been designed?

I got a question popping directly from reading Tanenbaum's Structured Computer Organization. Stating from Chap. 1 Sec. 1.1 : A machine with C++ or COBOL as its machine language would be complex ...
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1answer
90 views

SRAM and D-flip flop instead of transistor

I have read about the internal structure of SRAM and we need 6 transistors to store 1 bit. But what bothers me is why can't it be made using D-flip flops instead of going deep to transistor-level. It ...
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124 views

How does ROM work? [closed]

ROM is a major part of a computer, and even more so in gaming consoles. How exactly do they work, and how can you make them with logic gates/transistors? I'm currently working on many projects, ...
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Effect of doubling clock frequency on computer performance

If we double the clock frequency of a CPU, does that translate to a doubling of the CPU performance? Assuming that the number of instructions and CPI are constant, we have an inverse relationship ...
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I am trying to implement a datapath using sequential logic . Trying to implement this C program

I was thinking of creating three registers , namely X, Y and Z. I initialize x and y to constants of '0', then I make register Z an active low register. I send a constant ' 0 ' to the input line of ...
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Sequence Detector forced to wait a specific number of bits

So I have this little problem, where I am supposed to build a sequence detector which is forced to wait a specific number of bits before going into the reset state. It's kind of like pin codes work. ...
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3answers
80 views

What consumes the most power in a computer

I have a quite basic question: As far as I understand (correct me if I am wrong), we can summarize a computer by saying it is composed of wiring, transistors and some electronic components like ...
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3answers
89 views

Implementing ADD instruction for RiSC-16 processor

I'm trying to implement the RiSC-16 (not RISC) processor documented here using Verilog. The processor is really simple, however there is a problem when you try to perform ADD instructions ...
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34 views

Does stage Sy of instruction have to wait till all earlier instructions has executed their corresponding stage

I am trying to understand execution of instruction in RISC pipeline. Can stage Sy of instruction I2 execute before stage Sy of I1? That is, in below example, will it be allowed to run I2's ID in C3 as ...
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2answers
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What differentiates Laptops from PCs in terms of power consumption?

Today I as a Computer Scientist stumbled about some strange facts. Recently, I bought a new Macbook Model 16" inch. Today I tried to stress test it because I wondered if the 96 Watt charging cable ...
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1answer
96 views

What is an emulator POD?

Jack Ganssle - The Firmware Handbook States ...
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77 views

Cortex-M3, Code region vs SRAM/RAM

In the ARM Cortex-M3 processor core, the memory map contains: a Code region, SRAM and a RAM. What makes the use of the code region different than the other memories? In addition, what is the nature of ...
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What is the effect of multiple Register file ports of a CPU?

Register file ports are a means to get data in and out of registers in a CPU. The concept of having multiple ports is not too clear to me. QUESTION Assuming you have 2 read ports, does it mean ...
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1answer
106 views

How come decimal to BCD encoder has 10 input lines

Came across to study about decimal to BCD encoder and noticed it has 10 input lines, and four output lines but encoder should have 2 pow n input lines, so I doubt 10 cannot be in the form of 2 pow n!...
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Worst case scenerio in carry skip adder?

I am having trouble understanding this. worst case operation time takes place when carry is generated in the first block carry skips intermediate stages carry is killed in the last ...
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1answer
71 views

Are Tri-state buffers even necessary?

I'm trying to make a 1-bit computer, and I'm stuck on the registers. I think I am going to have 2 of them, and I want a way to separate their outputs. Let me explain. Let's say Register A has a 0, and ...
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1answer
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Why did only a few companies make microcomputers to begin with? [closed]

I was watching a program about Clive Sinclair and they used to advertise a computer and then design and build it within 3-6 months. So 8-bit computers must have been fairly simple to design and build....
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1answer
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Where in the instruction pipeline is machine code to microcode translation?

In my computer architecture courses on the N-stage pipeline, I never encountered the concept of microcode. I was surprised, then, when in a performance analysis course assignment, I discovered that ...
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1answer
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Thoughts & questions on custom CPU architecture

I'm designing a CPU architecture. I've come up with a preliminary design: I'd like general thoughts on what I can improve in the design and also I have some specific questions: Is it overkill to ...
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1answer
142 views

The accurate time latency for 'lw' instruction in a single-cycle datapath

I want to calculate the cycle time of a single-cycle datapath. Then from the course, I know the time should be the execution time of the longest instruction, which is 'lw' in MIPS. So I try to ...
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2answers
105 views

Designing a cryptographic S-Box in Logisim

I am currently working in Logisim and was wondering if I can design some ciphers in the same. One such cipher is PRESENT cipher which is essentially a block cipher. I did get that I need to design the ...
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2answers
322 views

How many ALUs (and threads) are in a Pentium CPU?

I'm reading a book bottom up where it said: The Arithmetic Logic Unit (ALU) is the heart of the CPU operation. It takes values in registers and performs any of the multitude of operations the ...
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1answer
33 views

CPU cache write policy - evict already dirty? + storage of memory address

I'm reading about cache in wiki https://en.m.wikipedia.org/wiki/CPU_cache and the following phrase seems not clear. Also, a write to a main memory location that is not yet mapped in a write-back ...
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3answers
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how to determine architecture core detail of ARM11 processor

I'm cross-compiling for an embedded Linux board, based in BCM5892 ARM11 processor. I need to know about architecture detail of this processor(‘armv6’, ‘armv6j’, ‘armv6k’, ‘armv6kz’, ‘armv6t2’, ‘...
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154 views

Is there any memory cell that can store more than one bit? [closed]

SRAM, DRAM, Flash, EPROM - all of the memory cells contain one bit of data each. Is there any memory cell that can store more than one bit, e.g. 2 bits/4bits?
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Why must a block in NAND SSDs be erased before it can be reprogammed? [closed]

Before programming a NAND based SSD in page-level we have to always erase by block-level which increases write amplification. why is it so and how do we mitigate it? what is the necessity of erasing ...
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7answers
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Why is the Digital 0 not 0V in computer systems?

I'm taking a computer system design course and my professor told us that in digital systems, the conventional voltages used to denote a digital 0 and a digital 1 have changed over the years. ...
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3answers
196 views

How does a computer chip read code, interpret it, and convert it into action? [closed]

I understand that binary is effectively functioning as a “virtual representation” of low voltage and high voltage. However, I do not understand how the instruction set to MAKE the voltage high or low ...

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