Questions tagged [computer-architecture]

Computer architecture refers to both the design of a computer's external interfaces (instruction sets) and a computer's internal implementation (microarchitecture). The goal of these design decisions is to optimize speed, power efficiency, size, or cost while satisfying constraints on the rest.

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Data flip flop - I don't understand its purpose

The data flip flop can delay operation based on the time of the cycle of the clock. If the clock's cycle is fast, the DFF is useless because it's like an instant change. Is it possible to change the ...
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How to find Base CPU Time and Memory-Stall Time

The program described below runs on a multiple issue processor with a 3-level CPU cache, a 4 GHz clock frequency, and the following performance metrics: Miss Penalty R/W Data Miss Rate Instruction ...
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What does the 8086 CPU do with the data returned from an address in RAM?

I understand how a CPU works fairly well, but there is this one thing which I've never really gotten the hang of. Say we have an Intel 8086 CPU (16 bits wide registers) which is about to fetch its ...
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Cache comparator usage

Referring to the photo below, in direct-mapping cache design, why we need a comparator to compare between the tag in the address and the tag in the cache? Isn't a valid bit enough?
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How do I set a value within an if statement using logic gates? [closed]

I have a value B that I want to set if a variable A = 1. I know how to create the if statement by applying an AND gate on a 1 constant and A, but how do I set B within that if statement using logic ...
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How do I create a 1-bit full adder that outputs a 2-bit sum?

I am trying to build a 1-bit full adder that outputs a 2-bit sum. I know that the standard 1-bit FA outputs a 1-bit sum and a carry bit, but I was wondering how can I modify the FA such that the carry ...
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Building a 2x8 memory using flip-flops and logic gates

The image represents a 4x3 memory.Build a 2x8 memory.
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1answer
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A computer architecture joke [closed]

Background Some months ago, I watched a Youtube video posted by the channel Numberphile. The video was on famous world mathematician Terence Tao, and in the video, he seemed to be struggling with ...
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3answers
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Would this type of design be scale-able? [closed]

With current technologies within a modern system, we have pushed the limits of computations within the CPU portion of the system where it now exceeds that of the memory units. Moving memory is slow ...
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What is the origin of the “iso [frequency/voltage/power]” terminology?

In the VLSI and computer architecture world, it is common to hear terms like "iso frequency" or "iso power" when comparing the performance of different designs. My understanding is ...
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Soft errors from SEUs/SETs in early 8-bit microprocessors?

Why is it that soft errors due to single-event upsets/transients never seemed to be a problem in early 8-bit microprocessors, like the MOS 6502 or the Zilog Z80? The microprocessors themselves were ...
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Has there been any deliberate implementation of combinational logic soft error correction in any consumer-level product, like a CPU/microcontroller? [closed]

Prologue It is well known that many error detection, mitigation, and correction methods, such as parity or ECC, have been available in large memory banks, like for RAM, for decades now, and even in ...
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Clarification of “strobe pin” 4-bit latch/4 to 16 line decoder

I'm wondering if I can get a specific behavior out of this chip. I have read the data sheet and am having some trouble understanding the usage of the Strobe pin. CD4515BM96 Datasheet PDF USE CASE I'm ...
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How do USB cameras encode video streams to be sent over USB? [closed]

Generic USB cameras can be used plug-and-play without the need for any additional drivers. How is the video stream compressed and sent over a USB connection? What are the standardized drivers that ...
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How can I modify single-cycle MIPS processor to implement jal command?

Hello Stack exchange community I was wondering which modification should I have to make in order to enable single-cycle MIPS processor to run a jal(jump and link) command? My most pressing confusion ...
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5answers
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What are the disadvantages of CISC architecture?

I took the computer architecture exam today. Our teacher asked a question. What are the disadvantages of CISC architecture ? Increases the number of commands while writing the program Makes ...
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1answer
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BJT transistor max switching frequency vs FET in high frequency computer architecture

Why arent BJTs used with RISC architectures to produce very high speed relatively sparse CPUs? My understanding is that BJTs don't have the forward bias gate capacitance requirements of FETs which is ...
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119 views

How does a 32-bit DSP address 2³² values without enough RAM?

A 32-bit CPU in a PC is capable of addressing 2³² individual bytes. How do DSPs and microprocessors handle such a large address space when they have RAMs only in MBs at the most?
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MU0 register transfer level organization by adding index register

Q. Write the MU0 register transfer level organization by adding index register. Give the control logic for the following instructions and explanations. LDA S,X ; A:=mem((S)+[X]) STA S,X ; mem((S)+[X])...
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1answer
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Linkage pointer in procedure

https://ocw.mit.edu/courses/electrical-engineering-and-computer-science/6-004-computation-structures-spring-2017/c12/c12s3/procedures_answers.pdf I don't understand how the linkage pointer can be the ...
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1answer
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What is the difference between Computer Organization and Computer Architecture?

I am still not getting a clear picture from any textbooks. Anyone, please elaborate with examples. What does 8086 architecture block diagram refer to?
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1answer
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electrification of all transistors

We discussed a topic in the computer organization course. The professor told us that when the computer first turned on, all the transistors on the CPU are instantly electrified. So he said, keeping ...
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1answer
103 views

Why do magnetic disks not have multiple heads per disk?

So it seems to me that when trying to improve performance of a external memory device (HDD), the thing that is increased is RPM. Why not have multiple read/write heads per substrate instead of just ...
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3answers
191 views

Why do displays have limited bit-depth?

As far as I am aware, HDMI 2.1 does support 12-bit 4K 60fps, Also it doesn't use TMDS, rather FRL. Sends upto 48Gbps GPUs can do calculation in fp32 and from some reference, I think that it can send ...
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How to find the dynamic energy of a processor without using capacitive load?

I have the following question: A cell phone performs very different tasks, including streaming music, streaming video, and reading email. These tasks perform very different computing tasks. Battery ...
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what were the ENIAC's equivalent to the modern CPU's elements?

If a modern CPU contains these elements: - 3 or more register units - ALU - control unit and the CPU is connected to a RAM composed of several addresses, what ...
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2answers
174 views

What's the relationship between chips, wafers, and dies in a computer?

I have the following question: If your demand is 50,000 RedDragon chips per month and 25,000 Phoenix chips per month, and your facility can fabricate 70 wafers a month, how many wafers should you ...
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1answer
514 views

4-bit decrementer using four Half Adders

Like the title mentions, is it possible to design a 4-bit decrementer using just four Half Adders? I know it's possible using 3 Full Adders + 1 Half Adder, but I don't seem to find a way to do that ...
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What processor architecture is in a 230GMULps KPU design?

While AI products are becoming popular recently, when looking at the "Seeed Studio Grove AI HAT for Edge Computing Artificial Intelligence Board" it mentions a RISC-V, a 230GMULps 16-bit KPU ...
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How did the arithmetic organ in ENIAC?

I have been reading the book of Goldstine on computers and I was wondering how ENIAC could activate a computation using numbers (the antecedent of the stored program concept). Goldstine wrote that ...
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247 views

Expression calculated at assembly time

I don't understand the explanation. Doesn't the assembler have to calculate 3 * 4 + 5 so it takes longer to execute? Also since 3 * 4 +5 has more characters why does it not take more storage? From ...
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2answers
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Using boolean algebra, simplify $$y = \bar{s} \cdot \bar{u} + s \cdot \bar{u}+s \cdot u$$

I have the following function, that I want to minimise using boolean algebra: $$y = \bar{s} \cdot \bar{u} + s \cdot \bar{u}+s \cdot u$$ Here's my attempt: $$\bar{s} \cdot \bar{u} + s \cdot \bar{u}+s \...
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DRAM Rank-Level Allocations

I want to do allocations on a specific DRAM rank. The smallest allocation unit in an OS such as Linux is at the page size ...
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2answers
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Designing a Combination Lock FSM: Converting State Diagram to Logic Gates

I am trying to design a Synchronous combination lock for my digital logic class. I have the state diagram, as I understand how to draw out the logic which I want to follow. However, I am struggling to ...
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How to cascade IC 74HC161 correctly?

Currently I have this 4 bit CPU as shown in the schematic diagram below. What I wish to achieve: Add one more output register to make the CPU output a total of 8 bits Show alphabet using the 8 bits ...
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1answer
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How does cache coherency and DMA work together?

I am currently reading about caches and how they are used in Computer Science. The explanation of how the cache is always up to date with the actual memory is understandable as long writing and ...
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1answer
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What is the difference in design between a von Neumann and the Harvard's machines?

Although there are many webpages talkink about the difference between the Aiken (prototype: Harvard Mark I) and von Neumann (prototype: ENIAC) architecture, the actual divergence remain uncertain to ...
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5 pipeline stage of mips cpu

If I want to make changes in the pipeline of MIPS CPU like: In Mem stage, ALU operator (add, sub and like this...) write the result to the destination register, while load and store stay the same as ...
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Pipelined Stack Based ISA [closed]

Most of the pipelined CPU, that I can find, is either an accumulator or general purpose register based ISA but is there a CPU with Stack Based ISA that is pipelined?
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DRAM Self-Refresh not the Lowest Power Mode

I have a DDR3L Samsung DRAM on my Laptop. Based on page 23 of its datasheet, IDD6 or the ...
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MESI based MULTICORE cache coherent system - bug issue

For this particular architectural design, in general, what happens when there are parallel processor and snoop side requests? How is such a corner case handled? We have the following information about ...
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DMA SPI performance

I am currently writing an SD card driver for a Microcontroller using SPI and DMA. The SPI has a FIFO that can store 4 data values from the data register which has the capable of storing 32 bit. But it ...
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What are common ways that modern processors handle data hazards with asynchronous registers

I'm trying to design a processor in VHDL. While the base instruction set is done, I'm having trouble building on top of it. Specifically, I'm implementing control and status registers (CSRs), which ...
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How to use only BEQ to perform other conditional branch

Given "Branch if equal(BEQ)" as the only conditional branch and other instruction like arithmetic and unconditional branch instructions, is it possible to perform other conditional branching like ...
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1answer
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Do 64-bit CPUs consume more power than 32-bit ones?

In this lecture about efficient computing for deep learning, the benchmarks show a 3-fold increase in power usage between 8-bit and 32-bit addition operations. Between 8-bit and 32-bit multiplication, ...
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3answers
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Why is GPU memory fixed? [closed]

In pretty much all modern computers and mobile devices, the CPU can have varying amounts of memory (either to be configured by the user or fixed at point of assembly). Apart from historical form-...
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7answers
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Why do computer circuits tend to have so many resistors and capacitors? [duplicate]

As someone who has a decent understanding of computer architecture (but not of electrical engineering) I've always wondered why computer circuits tend to have so many resistors, capacitors, and other ...
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Computer Instruction Format - Calculating the number of Opcodes

I found the following question on a different site: A processor has 64 registers and uses 16-bit instruction format. It has two types of instructions: I-type and R-type. Each I-type instruction ...
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In Directed-mapped cache, a problem in exercise!

5.2 Caches are important to providing a high-performance memory hierarchy to processors. Below is a list of 32-bit memory address references, given as word addresses. 3, 180, 43, 2, 191, 88, ...
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Exercise in cache, in particular about AMAT

I have a question in computer organization and Design textbook, Tutorial 5.6 (b) p. 487, 5.7. In this exercise, cache access time is proportional to capacity. Assume that main memory accesses take ...

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