Questions tagged [computer-architecture]

Computer architecture refers to both the design of a computer's external interfaces (instruction sets) and a computer's internal implementation (microarchitecture). The goal of these design decisions is to optimize speed, power efficiency, size, or cost while satisfying constraints on the rest.

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Why do we need nonlinear electronics for computing?

When I read about photonics, I always see that they can be used for linear transformations (just matrix multiplications), and that this is a limitation that makes them unsuitable for building a ...
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Implementing functional design of a computer system into physical hardware [duplicate]

I have recently started studying computer organisation and found that in most of the books the design of computer system is not discussed beyond functional design abstraction level (as shown in the ...
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Functional design implementation of computer system into actual physical hardware

I have recently started studying computer organisation and found that in most of the books the design of computer system is not discussed beyond functional design abstraction level (as shown in the ...
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1 vote
2 answers
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How is sll implemented in MIPS?

I don't understand how MIPS would implement the sll (shift left logical) instruction using the hardware present in its ALU as shown in the diagrams below. Would ...
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Verilog code execution in gate level modeling

The following is Verilog code an SR latch. ...
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3 answers
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Why do we see one, unified memory address space in ARM Cortex-M core based MCUs even though they have Harvard architecture?

Most of the ARM Cortex-M core based MCUs have Harvard architecture (except for Cortex-M0 and M0+.) The thing I do not understand is that why we see only one memory address space. For example, in tge ...
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What drives an input from 0 to 1 inside of a digital circuit?

Inside of a digital circuit, like a computer, what is acting as the switch that drives the inputs or internal values from 0 to 1, and how does this work? Like in instructions for a computer, how are ...
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Do PCI Express devices' interrupts always go through a PIC or an APIC?

My Question is PCI/PCIe interrupt path to CPU is through a PIC or an APIC? https://people.freebsd.org/~jhb/papers/bsdcan/2007/...
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Processor Design: Just how complex is a real CPU datapath?

We're doing a course on Computer Architecture, and the course project involves creating an ARM-based processor. We're supposed to create the processor in stages, and add significant features in each ...
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1 answer
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How do computer memories interact with each other (registers, cache, RAM, ROM)?

After Googling around for some time, I have managed to get a good understanding what makes these components different, but I've yet to find any clear computer architecture-focused article/thread on ...
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Understanding Forwarding unit

I am new to this subject and am having trouble understanding this topic. Suppose I have the following circuit to control the forwarding of a MIPS pipeline processor: So the forwarding control will be ...
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-1 votes
1 answer
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How do I assign one of the outputs of a module to the output of a different module?

...
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What do the diagonal lines in these circuits mean? [duplicate]

What exactly do these diagonal lines represent in these circuits? (I have them circled in red.)
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2 votes
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Is it usual design that the addition operation in the arithmetic-logic unit is performed by default as other instructions are executed?

The book But How Do It Know? presents an 8-bit computer architecture in which arithmetic-logic instructions (that is, instructions which are executed by the ALU) have 1 as the most significant bit, ...
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4 answers
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How do processor transistor counts keep increasing, without geometric scaling?

Reading into the history of the semiconductor industry and Moore's Law, and looking at the ITRS/IRDS documents, I understand that scaling down and modern node names (7nm, 5nm etc) are now "...
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Confusion about IJVM

I was reading the chapter 4 of the book 'Computer Architecture' by Tanenbaum (since my copy is not in English maybe the title of the English version is not exactly that one), however it is the chapter ...
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Does the memory bus span multiple layers on die?

My question is if you take any model desktop CPU such as the ones manufactured by Intel would the design of the memory bus span multiple layers of a single die or would it be contained on a single ...
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Are coarse-grained reconfigurable architectures a subset of dataflow architecture?

By definition, dataflow architectures consist of large modules in the dataflow path, such as adders and multipliers for integer, floating-point, or fixed-point computation. Hence, are coarse-grained ...
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What is the cost of increasing the number of register names?

Increasing the number of registers in a CPU, has the upside that more values can be kept in registers instead of having to spill to stack. It has some downsides, one of which is that more instruction ...
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Computers: How signals in the bus can travel in either direction [closed]

I'm reading J. Clark Scott's book But How Do It Know. When he is describing registers and the bus he illustrates this at one point as five registers sequentially parallel-connected to a bus. As you ...
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How does CDB mastering work in Tomasulo's algorithm?

I understand that implementations of Tomasulo's algorithm feature a common data bus (CDB) that each functional unit writes its output to. Each reservation station can listen on the CDB for its ...
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0 votes
1 answer
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How does CPU control implement pipeline stall [closed]

The original question was deemed lack of focus. This post is specifically about cpu pipeline stall. How does synchronous microarchitecture implement pipeline stall when a cache miss occurs during ...
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2 votes
1 answer
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How does Asynchronous DRAM perform self-timing

The original question was deemed lack of focus. This post is specifically about dram chip. When DRAM controller talks to an asynchronous DRAM, how does DRAM itself know when a write is completed and ...
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3 votes
1 answer
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Are processor instruction sets royalty free? (e.g. ARM v9, x86)

I asked a general question on Law SE with one example (ARM) and for that example, I was directed to What exactly does ARM sell to vendors?. I've read that QA that ARM sells actual core designs. I've ...
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0 votes
2 answers
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Transistors collector input output of other transistor?

I'm new to computer science and trying to learn the basics. Have learnt how to create logical gates using simple components like relays, thanks to nandgame.com. This was easy, boolean functions, have ...
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0 votes
1 answer
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Can a pin to DDR4 be as thin as household tinfoil? (0.016 mm)

Edit: I think using the term "bus" might be wrong here. A "bus" needs to be large enough to facilitate an entire DDR4 stick's bandwidth to the Northbridge. The connection to each ...
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2 votes
2 answers
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Which bus protocol(s) does a motherboard use to connect to RAM?

I'm trying to learn about the protocols busses use in computer engineering and so far I've learned about the CAN bus protocol, where you can even watch traffic on the busses with wireshark, but this ...
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0 votes
3 answers
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Question about computer engineering circuits (noob question) [closed]

I'm currently self learning computer engineering stuff right now and I was wondering how RAM would work in terms of input and output and I stumbled upon this image I think it's somewhat wrong from ...
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9 votes
6 answers
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Estimating current draw for a single instruction

I am a software engineer concerned about current draw. I am aware that there are ways to reduce the current draw of a program, for example: using a hlt instruction ...
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2 votes
1 answer
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Internal differences between CPUs of the same architecture

What is the difference between, for example an Intel i3-4005U (1.7 GHz) and an Intel i3-4025U (1.9 GHz)? These CPUs are from the same generation, have the same amount of cores, cache, iGPU, and ...
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What is the difference between stalling and flushing in a microprocessor?

As the title suggests, I want to understand the difference. Attaching the reference.
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2 answers
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What is a hardware thread in RISC-V?

RISC-V PMP limits the physical addresses accessible by software running on a hart (hardware thread). Source: edX course on Introduction to RISC-V, Chapter 4. Developing RISC-V, The Privileged ...
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1 answer
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Is it true that CISC architectures generally consume more power than RISC architectures?

I keep hearing CISC architectures consume more power than RISC architectures. This is said to be the reason for using RISC architectures for low-power applications. I am a skeptic, I think it could be ...
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10 votes
3 answers
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How does an operating system or program detect the CPU model name? [closed]

What kind of binary compatibility is present for 2 processors sharing an Instruction Set?. I had asked a question on Computer Science Stack Exchange, to which I got an answer which said: As a trivial ...
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1 vote
1 answer
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Where is the RAM stored on a RISC-V CPU? [closed]

Does RISC-V have any opinion on whether the RAM is stored on the same chip as the CPU (like on ARM devices) or on a separate chip somewhere on the motherboard (like on an x86 desktop)? I assume that ...
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0 votes
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What mechanism prevents me from initializing multiple peripherals on the same GPIO pin?

Can I initialize multiple peripherals on the same GPIO pin? For example, if I bind a GPIO with a peripheral, can I still manipulate this pin with the GPIO interface? With pseudo-code: ...
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2 votes
1 answer
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Why can't an Asynchronous CPU use a simple "completion bit" to signal completion?

I've been reading about how asynchronous CPUs work, but they always seem to involve some complicated way of communication. Wikipedia talks about a two-way and four-way handshake. I found a pdf from ...
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2 votes
1 answer
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Size of a memory cache

Assuming we have a virtual address issued by a model CPU that contains a total of 32 bits and 20 bits of this address are reserved for the tag + the cache comprises a total of 1024 cache lines. Should ...
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1 answer
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Logisim: Implementing a control unit for "Addition", "Logic bitwise AND" and "right logic shift" in ALU [closed]

I'm very new to circuit design. I've built an ALU and now I only need a control unit for three operations, "Addition", "Logic bitwise AND" and "right logic shift". What ...
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Read after Write and Write after write dependencie at the same time

Assuming the following pseudo-code down bellow: 1)r1 = 4 2)r2 = 5 3)r3 = r1 + 5 4)r4 = r2 + r1 5)r4 = r4 + r3 6)r1 = 10 7)r7 = r1 - 1 the r4 on line 5 is both name ...
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3 votes
2 answers
174 views

How can I fix delay between Instruction and Program Counter?

I am designing the MIPS processor, this includes Data Memory and Instruction memory for testing. I had a problem with IM synthesis covered in this question (How to make a synthesizable Instruction ...
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2 votes
0 answers
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The concept of DDR rank

I have an understanding of DDR rank which I think is incorrect. If someone could join the dots then there would be more clarity. Here is what I know A DDR rank is a 64bit interface consisting of x8 ...
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Can I have some help compacting this?

I am trying to build a transistor computer, and I want to save as much resources as possible. However, I also want it to be practical, so I am implementing a binary-decimal conversion. In order to ...
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How much faster is the ideal machine without the memory structural hazard versus the machine with the hazard?

I am learning computer architecture and organization. I have the following doubt. Given below is a question along with its solution but I think that the solution is wrong. You can see the question ...
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3 votes
1 answer
109 views

With what stage of the branch instruction does the IF stage executes if the branch is taken?

I am learning computer architecture and organization. I have the following doubt. Given below is a question along with its solution but I think that the solution is wrong. Consider an instruction ...
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-1 votes
2 answers
97 views

What is the most important CPU price factor [closed]

I have two intel CPUS with distinct features. intel i7 8550U intel i5 8300H Which have big performance difference with the cheaper 8300H being higher in memory ...
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1 answer
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Is bit stuffing done after 6 or 5 consecutive 1's? [closed]

I am learning computer architecture and organization. I have the following doubt. I have read that in bit stuffing a 0 is inserted whenever 6 consecutive 1’s are encountered. However, it may be noted ...
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0 votes
1 answer
275 views

Why is programmed I/O not suitable for high-speed data transfer?

I am learning about computer architecture and organization. I have read that programmed I/O is not suitable for high-speed data transfer because it does not support synchronous mode of data ...
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-2 votes
2 answers
155 views

Can synchronous data transfer be used for transferring large data in case of computer architecture and organization? [closed]

I am learning computer architecture and organization. I have this confusion, can synchronous data transfer be used for transferring large data in case of computer architecture and organization? I ...
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2 votes
4 answers
965 views

Why is asynchronous data transfer only suitable for slow devices?

I have read that asynchronous data transfer is wasteful of CPU time for slow devices like keyboard or mouse. Then how is it possible that it is suitable only for slow devices like keyboard or mouse ...
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