Questions tagged [computer-architecture]

Computer architecture refers to both the design of a computer's external interfaces (instruction sets) and a computer's internal implementation (microarchitecture). The goal of these design decisions is to optimize speed, power efficiency, size, or cost while satisfying constraints on the rest.

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24 views

Literal white noise [migrated]

My friend has a work desktop computer with some non-fancy hardware. The onboard audio is output via a 3.5mm cable to some speakers in the room. These speakers produce a constant hum while the computer ...
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MU0 register transfer level organization by adding index register

Q. Write the MU0 register transfer level organization by adding index register. Give the control logic for the following instructions and explanations. LDA S,X ; A:=mem((S)+[X]) STA S,X ; mem((S)+[X])...
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4 kByte size of memory address connected to CPU

Let's say I have a memory of 4 kByte size (4096 memory cells) connected to a CPU. If I want the lowest as well as the highest address in hexadecimal notation , how can I calculate them When I don't ...
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34 views

Linkage pointer in procedure

https://ocw.mit.edu/courses/electrical-engineering-and-computer-science/6-004-computation-structures-spring-2017/c12/c12s3/procedures_answers.pdf I don't understand how the linkage pointer can be the ...
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What is the difference between Computer Organization and Computer Architecture?

I am still not getting a clear picture from any textbooks. Anyone, please elaborate with examples. What does 8086 architecture block diagram refer to?
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103 views

electrification of all transistors

We discussed a topic in the computer organization course. The professor told us that when the computer first turned on, all the transistors on the CPU are instantly electrified. So he said, keeping ...
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100 views

Why do magnetic disks not have multiple heads per disk?

So it seems to me that when trying to improve performance of a external memory device (HDD), the thing that is increased is RPM. Why not have multiple read/write heads per substrate instead of just ...
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154 views

Why do displays have limited bit-depth?

As far as I am aware, HDMI 2.1 does support 12-bit 4K 60fps, Also it doesn't use TMDS, rather FRL. Sends upto 48Gbps GPUs can do calculation in fp32 and from some reference, I think that it can send ...
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How to find the dynamic energy of a processor without using capacitive load?

I have the following question: A cell phone performs very different tasks, including streaming music, streaming video, and reading email. These tasks perform very different computing tasks. Battery ...
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what were the ENIAC's equivalent to the modern CPU's elements?

If a modern CPU contains these elements: - 3 or more register units - ALU - control unit and the CPU is connected to a RAM composed of several addresses, what ...
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What's the relationship between chips, wafers, and dies in a computer?

I have the following question: If your demand is 50,000 RedDragon chips per month and 25,000 Phoenix chips per month, and your facility can fabricate 70 wafers a month, how many wafers should you ...
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152 views

4-bit decrementer using four Half Adders

Like the title mentions, is it possible to design a 4-bit decrementer using just four Half Adders? I know it's possible using 3 Full Adders + 1 Half Adder, but I don't seem to find a way to do that ...
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What processor architecture is in a 230GMULps KPU design?

While AI products are becoming popular recently, when looking at the "Seeed Studio Grove AI HAT for Edge Computing Artificial Intelligence Board" it mentions a RISC-V, a 230GMULps 16-bit KPU ...
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How did the arithmetic organ in ENIAC?

I have been reading the book of Goldstine on computers and I was wondering how ENIAC could activate a computation using numbers (the antecedent of the stored program concept). Goldstine wrote that ...
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243 views

Expression calculated at assembly time

I don't understand the explanation. Doesn't the assembler have to calculate 3 * 4 + 5 so it takes longer to execute? Also since 3 * 4 +5 has more characters why does it not take more storage? From ...
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Using boolean algebra, simplify $$y = \bar{s} \cdot \bar{u} + s \cdot \bar{u}+s \cdot u$$

I have the following function, that I want to minimise using boolean algebra: $$y = \bar{s} \cdot \bar{u} + s \cdot \bar{u}+s \cdot u$$ Here's my attempt: $$\bar{s} \cdot \bar{u} + s \cdot \bar{u}+s \...
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74 views

DRAM Rank-Level Allocations

I want to do allocations on a specific DRAM rank. The smallest allocation unit in an OS such as Linux is at the page size ...
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2answers
57 views

Designing a Combination Lock FSM: Converting State Diagram to Logic Gates

I am trying to design a Synchronous combination lock for my digital logic class. I have the state diagram, as I understand how to draw out the logic which I want to follow. However, I am struggling to ...
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How to cascade IC 74HC161 correctly?

Currently I have this 4 bit CPU as shown in the schematic diagram below. What I wish to achieve: Add one more output register to make the CPU output a total of 8 bits Show alphabet using the 8 bits ...
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1answer
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How does cache coherency and DMA work together?

I am currently reading about caches and how they are used in Computer Science. The explanation of how the cache is always up to date with the actual memory is understandable as long writing and ...
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What is the difference in design between a von Neumann and the Harvard's machines?

Although there are many webpages talkink about the difference between the Aiken (prototype: Harvard Mark I) and von Neumann (prototype: ENIAC) architecture, the actual divergence remain uncertain to ...
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5 pipeline stage of mips cpu

If I want to make changes in the pipeline of MIPS CPU like: In Mem stage, ALU operator (add, sub and like this...) write the result to the destination register, while load and store stay the same as ...
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Pipelined Stack Based ISA [closed]

Most of the pipelined CPU, that I can find, is either an accumulator or general purpose register based ISA but is there a CPU with Stack Based ISA that is pipelined?
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DRAM Self-Refresh not the Lowest Power Mode

I have a DDR3L Samsung DRAM on my Laptop. Based on page 23 of its datasheet, IDD6 or the ...
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MESI based MULTICORE cache coherent system - bug issue

For this particular architectural design, in general, what happens when there are parallel processor and snoop side requests? How is such a corner case handled? We have the following information about ...
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DMA SPI performance

I am currently writing an SD card driver for a Microcontroller using SPI and DMA. The SPI has a FIFO that can store 4 data values from the data register which has the capable of storing 32 bit. But it ...
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What are common ways that modern processors handle data hazards with asynchronous registers

I'm trying to design a processor in VHDL. While the base instruction set is done, I'm having trouble building on top of it. Specifically, I'm implementing control and status registers (CSRs), which ...
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How to use only BEQ to perform other conditional branch

Given "Branch if equal(BEQ)" as the only conditional branch and other instruction like arithmetic and unconditional branch instructions, is it possible to perform other conditional branching like ...
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1answer
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Do 64-bit CPUs consume more power than 32-bit ones?

In this lecture about efficient computing for deep learning, the benchmarks show a 3-fold increase in power usage between 8-bit and 32-bit addition operations. Between 8-bit and 32-bit multiplication, ...
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3answers
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Why is GPU memory fixed? [closed]

In pretty much all modern computers and mobile devices, the CPU can have varying amounts of memory (either to be configured by the user or fixed at point of assembly). Apart from historical form-...
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Why do computer circuits tend to have so many resistors and capacitors? [duplicate]

As someone who has a decent understanding of computer architecture (but not of electrical engineering) I've always wondered why computer circuits tend to have so many resistors, capacitors, and other ...
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Computer Instruction Format - Calculating the number of Opcodes

I found the following question on a different site: A processor has 64 registers and uses 16-bit instruction format. It has two types of instructions: I-type and R-type. Each I-type instruction ...
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In Directed-mapped cache, a problem in exercise!

5.2 Caches are important to providing a high-performance memory hierarchy to processors. Below is a list of 32-bit memory address references, given as word addresses. 3, 180, 43, 2, 191, 88, ...
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Exercise in cache, in particular about AMAT

I have a question in computer organization and Design textbook, Tutorial 5.6 (b) p. 487, 5.7. In this exercise, cache access time is proportional to capacity. Assume that main memory accesses take ...
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A problem dealing with a two-way set-associative cache

This is Problem 13-4 from the book "Logic and Computer Design Fundamentals" by M. Morris Mano and Charles R. Kime. I did the problem. I would like somebody to confirm that my answer is correct or tell ...
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A Problem dealing with Cache memory on a computer

This is Problem 13-3 from the book "Logic and Computer Design Fundamentals" by M. Morris Mano and Charles R. Kime. I believe I have the answer right for part a and part b. That is, they match the ...
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5answers
557 views

How does a microprocessor control its transistors? [closed]

Or in other words, what is the more fundamental building block of an IC below transistors? When I load a code onto my microprocessor, how (fundamentally, sure some people here could write books about ...
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2answers
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What does “Cycle \$\mu\$s” mean in this context?

I'm reading a paper about the architecture of the IBM system/360. There is a diagram which lays out the machine structure and implementation in the storage and control tables there is a metric which I ...
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1answer
48 views

Need Help Identifying [closed]

This is a Board off a 8tb WD Hard Drive. I plug in the wrong power and i believe the little thing with the S on it is bad. I do not know what it is call or where i could find another, any help would ...
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Cache Memory Read and Write Miss/hit policies: details of a real processor

All the references I have checked so far explain the Read Miss,Write Hit/Miss policies at the same level of detail. I understand their concepts but I am looking for more details on their ...
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1answer
94 views

MIPS clock cycle calculation formula

How many clock cycles will take execution of this segment on the simple pipeline without forwarding or bypassing when result of the branch instruction (new PC content) is available after WB stage. ...
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1answer
93 views

How does a computer shutdown really work [closed]

I don't know if this is the right place to ask, but i'm asking anyway. How does a computer shutdown really work? I want to know the electronics (or physics) behind it. Like, how does a system signal ...
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2answers
44 views

Why is a Flush needed in the MSI cache coherency protocol when moving from Modified to Invalid?

While studying the MSI protocol as described in different sources such as: https://en.wikipedia.org/w/index.php?title=MSI_protocol&oldid=941977299 http://courses.csail.mit.edu/6.888/spring13/...
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5answers
280 views

Has a CPU with Highlevel language (C/C++) as machine code ever been designed?

I got a question popping directly from reading Tanenbaum's Structured Computer Organization. Stating from Chap. 1 Sec. 1.1 : A machine with C++ or COBOL as its machine language would be complex ...
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122 views

SRAM and D-flip flop instead of transistor

I have read about the internal structure of SRAM and we need 6 transistors to store 1 bit. But what bothers me is why can't it be made using D-flip flops instead of going deep to transistor-level. It ...
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3answers
219 views

How does ROM work? [closed]

ROM is a major part of a computer, and even more so in gaming consoles. How exactly do they work, and how can you make them with logic gates/transistors? I'm currently working on many projects, ...
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167 views

Effect of doubling clock frequency on computer performance

If we double the clock frequency of a CPU, does that translate to a doubling of the CPU performance? Assuming that the number of instructions and CPI are constant, we have an inverse relationship ...
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1answer
73 views

I am trying to implement a datapath using sequential logic . Trying to implement this C program

I was thinking of creating three registers , namely X, Y and Z. I initialize x and y to constants of '0', then I make register Z an active low register. I send a constant ' 0 ' to the input line of ...
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2answers
74 views

Sequence Detector forced to wait a specific number of bits

So I have this little problem, where I am supposed to build a sequence detector which is forced to wait a specific number of bits before going into the reset state. It's kind of like pin codes work. ...
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3answers
82 views

What consumes the most power in a computer

I have a quite basic question: As far as I understand (correct me if I am wrong), we can summarize a computer by saying it is composed of wiring, transistors and some electronic components like ...

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