Questions tagged [computer-architecture]

Computer architecture refers to both the design of a computer's external interfaces (instruction sets) and a computer's internal implementation (microarchitecture). The goal of these design decisions is to optimize speed, power efficiency, size, or cost while satisfying constraints on the rest.

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The concept of DDR rank

I have an understanding of DDR rank which I think is incorrect. If someone could join the dots then there would be more clarity. Here is what I know A DDR rank is a 64bit interface consisting of x8 ...
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Can I have some help compacting this?

I am trying to build a transistor computer, and I want to save as much resources as possible. However, I also want it to be practical, so I am implementing a binary-decimal conversion. In order to ...
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How much faster is the ideal machine without the memory structural hazard versus the machine with the hazard?

I am learning computer architecture and organization. I have the following doubt. Given below is a question along with its solution but I think that the solution is wrong. You can see the question ...
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1answer
62 views

With what stage of the branch instruction does the IF stage executes if the branch is taken?

I am learning computer architecture and organization. I have the following doubt. Given below is a question along with its solution but I think that the solution is wrong. Consider an instruction ...
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2answers
89 views

What is the most important CPU price factor [closed]

I have two intel CPUS with distinct features. intel i7 8550U intel i5 8300H Which have big performance difference with the cheaper 8300H being higher in memory ...
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1answer
110 views

Is bit stuffing done after 6 or 5 consecutive 1's? [closed]

I am learning computer architecture and organization. I have the following doubt. I have read that in bit stuffing a 0 is inserted whenever 6 consecutive 1’s are encountered. However, it may be noted ...
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1answer
165 views

Why is programmed I/O not suitable for high-speed data transfer?

I am learning about computer architecture and organization. I have read that programmed I/O is not suitable for high-speed data transfer because it does not support synchronous mode of data ...
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2answers
130 views

Can synchronous data transfer be used for transferring large data in case of computer architecture and organization? [closed]

I am learning computer architecture and organization. I have this confusion, can synchronous data transfer be used for transferring large data in case of computer architecture and organization? I ...
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4answers
529 views

Why is asynchronous data transfer only suitable for slow devices?

I have read that asynchronous data transfer is wasteful of CPU time for slow devices like keyboard or mouse. Then how is it possible that it is suitable only for slow devices like keyboard or mouse ...
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Difficulty in understanding the concept of operand forward in pipeling and when to use split phase

Given below is a question from \$\text{GATE } 2015 \text{ CS}\$ paper, Consider the sequence of machine instruction given below: \begin{array}{ll} \text{MUL} & \text{R5, R0, R1} \\ \text{DIV} &...
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Is it correct that in a hard disk both surfaces of each disk are capable of storing data?

I have read that in a hard disk both surfaces of each disk are capable of storing data except the top and bottom disk where only the inner surface is used. Is it correct if yes then why is are there ...
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1answer
67 views

Average data transfer rate

I am learning computer architecture and organization I am stuck in the following question. Consider a hard disk with sector size 1024 bytes, 5000 tracks per surface, 64 sectors per track, and 8 ...
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1answer
67 views

How to calculate the bandwidth of a synchronous bus with overlap in bus transfer and reading next data?

I am working through problems in Saylor Academy's computer architecture course. I can't understand how this kind of problem is solved: Consider a 32-bit synchronous bus with f = 125 Mhz, an 8 nsec ...
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1answer
88 views

Throughput increase/decrease by how much percent

I am learning computer architecture and organization. I am stuck in the following question. Can someone please help me? The stage delays in a 5-stage pipeline are 300, 200, 100, 400 and 350 ...
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1answer
68 views

How is the exponent expressed in single precision floating-point number representation using IEEE-754 format

I am learning computer architecture and organization. I am stuck in the following question. Can someone please help me? How is the exponent expressed in single precision floating-point number ...
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2answers
183 views

The minimum (negative) value of the exponent in decimal

I am learning computer architecture and organization. I am stuck in the following question. Can someone please help me? For a floating-point representation with 35 bits in the mantissa and 15 bits in ...
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1answer
50 views

differences between mini pcie vs half height mini pcie

I want to use a mini- PCIe half height to connect a communication module to my PCB. For example- to use a board like the raspberry pi 4 compute module io board with a WiFi expansion board. Given that ...
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1answer
279 views

Is it possible to remove the write back stage in 5-stage pipeline?

In this graph, can we simply remove the write back stage since the mux is pushed back into the memory access stage and there is no logic in the write back stage. Is it because of the register file ...
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2answers
313 views

How are irrational numbers best represented and processed by computers?

My question is closely related to this one: How do computers understand decimal numbers? However, that question deals with rational numbers only. I was wondering if irrational numbers can be ...
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2answers
116 views

VHDL: port declaration design for a feedback signal

I am a Computer Engineering student currently learning computer architecture, and working on modeling a booth's algorithm in VHDL. My design hierarchy contains a datapath and a control unit. The ...
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4answers
145 views

Can an FPGA/ASIC have an Operating System?

I know FPGA/ASIC are for a specific task and they are not microprocessors and an OS is needed mainly if multiple processes(tasks) need to be run concurrently. Just wondering if an FPGA/ASIC can have ...
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2answers
55 views

VHDL: on variable declarations to act as register

I am currently a CPE student taking up computer architecture, learning how to model major computer components using VHDL. Currently, I am working on a shift register as a sub component for a top-level ...
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2answers
114 views

Difference between ARM7 and intel i3, i5 & i7 processors

I am just starting out on a journey to understand microcontroller and microprocessor design. Have read briefly on their differences (ARM7 and Intel i3, i5 & i7). Couldn't find any information on ...
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Module not giving correct output when the input is changed - verilog

I am trying to implement a 32-bit floating point divider. When I give only the mantissa as input, the divider gives correct output whereas when I change the input to 32-bit floating point number(...
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1answer
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doubt in pipelining forwarding in mips

I am fairly new to computer architecture and having a tough time solving problems based on pipelining. I was trying to solve a problem from this pdf I found on Google I have a doubt in part ...
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1answer
98 views

Data flip flop - I don't understand its purpose

The data flip flop can delay operation based on the time of the cycle of the clock. If the clock's cycle is fast, the DFF is useless because it's like an instant change. Is it possible to change the ...
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How to find Base CPU Time and Memory-Stall Time

The program described below runs on a multiple issue processor with a 3-level CPU cache, a 4 GHz clock frequency, and the following performance metrics: Miss Penalty R/W Data Miss Rate Instruction ...
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3answers
227 views

What does the 8086 CPU do with the data returned from an address in RAM?

I understand how a CPU works fairly well, but there is this one thing which I've never really gotten the hang of. Say we have an Intel 8086 CPU (16 bits wide registers) which is about to fetch its ...
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1answer
44 views

Cache comparator usage

Referring to the photo below, in direct-mapping cache design, why we need a comparator to compare between the tag in the address and the tag in the cache? Isn't a valid bit enough?
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1answer
76 views

How do I set a value within an if statement using logic gates? [closed]

I have a value B that I want to set if a variable A = 1. I know how to create the if statement by applying an AND gate on a 1 constant and A, but how do I set B within that if statement using logic ...
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2answers
65 views

How do I create a 1-bit full adder that outputs a 2-bit sum?

I am trying to build a 1-bit full adder that outputs a 2-bit sum. I know that the standard 1-bit FA outputs a 1-bit sum and a carry bit, but I was wondering how can I modify the FA such that the carry ...
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2answers
133 views

Building a 2x8 memory using flip-flops and logic gates

The image represents a 4x3 memory.Build a 2x8 memory.
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1answer
159 views

A computer architecture joke [closed]

Background Some months ago, I watched a Youtube video posted by the channel Numberphile. The video was on famous world mathematician Terence Tao, and in the video, he seemed to be struggling with ...
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3answers
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Would this type of design be scale-able? [closed]

With current technologies within a modern system, we have pushed the limits of computations within the CPU portion of the system where it now exceeds that of the memory units. Moving memory is slow ...
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94 views

What is the origin of the “iso [frequency/voltage/power]” terminology?

In the VLSI and computer architecture world, it is common to hear terms like "iso frequency" or "iso power" when comparing the performance of different designs. My understanding is ...
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2answers
147 views

Soft errors from SEUs/SETs in early 8-bit microprocessors?

Why is it that soft errors due to single-event upsets/transients never seemed to be a problem in early 8-bit microprocessors, like the MOS 6502 or the Zilog Z80? The microprocessors themselves were ...
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3answers
115 views

Has there been any deliberate implementation of combinational logic soft error correction in any consumer-level product, like a CPU/microcontroller? [closed]

Prologue It is well known that many error detection, mitigation, and correction methods, such as parity or ECC, have been available in large memory banks, like for RAM, for decades now, and even in ...
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2answers
57 views

Clarification of “strobe pin” 4-bit latch/4 to 16 line decoder

I'm wondering if I can get a specific behavior out of this chip. I have read the data sheet and am having some trouble understanding the usage of the Strobe pin. CD4515BM96 Datasheet PDF USE CASE I'm ...
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2answers
79 views

How do USB cameras encode video streams to be sent over USB? [closed]

Generic USB cameras can be used plug-and-play without the need for any additional drivers. How is the video stream compressed and sent over a USB connection? What are the standardized drivers that ...
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1answer
347 views

How can I modify single-cycle MIPS processor to implement jal command?

Hello Stack exchange community I was wondering which modification should I have to make in order to enable single-cycle MIPS processor to run a jal(jump and link) command? My most pressing confusion ...
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5answers
134 views

What are the disadvantages of CISC architecture?

I took the computer architecture exam today. Our teacher asked a question. What are the disadvantages of CISC architecture ? Increases the number of commands while writing the program Makes ...
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1answer
102 views

BJT transistor max switching frequency vs FET in high frequency computer architecture

Why arent BJTs used with RISC architectures to produce very high speed relatively sparse CPUs? My understanding is that BJTs don't have the forward bias gate capacitance requirements of FETs which is ...
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1answer
123 views

How does a 32-bit DSP address 2³² values without enough RAM?

A 32-bit CPU in a PC is capable of addressing 2³² individual bytes. How do DSPs and microprocessors handle such a large address space when they have RAMs only in MBs at the most?
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MU0 register transfer level organization by adding index register

Q. Write the MU0 register transfer level organization by adding index register. Give the control logic for the following instructions and explanations. LDA S,X ; A:=mem((S)+[X]) STA S,X ; mem((S)+[X])...
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1answer
44 views

Linkage pointer in procedure

https://ocw.mit.edu/courses/electrical-engineering-and-computer-science/6-004-computation-structures-spring-2017/c12/c12s3/procedures_answers.pdf I don't understand how the linkage pointer can be the ...
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1answer
618 views

What is the difference between Computer Organization and Computer Architecture?

I am still not getting a clear picture from any textbooks. Anyone, please elaborate with examples. What does 8086 architecture block diagram refer to?
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1answer
107 views

electrification of all transistors

We discussed a topic in the computer organization course. The professor told us that when the computer first turned on, all the transistors on the CPU are instantly electrified. So he said, keeping ...
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1answer
111 views

Why do magnetic disks not have multiple heads per disk?

So it seems to me that when trying to improve performance of a external memory device (HDD), the thing that is increased is RPM. Why not have multiple read/write heads per substrate instead of just ...
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3answers
216 views

Why do displays have limited bit-depth?

As far as I am aware, HDMI 2.1 does support 12-bit 4K 60fps, Also it doesn't use TMDS, rather FRL. Sends upto 48Gbps GPUs can do calculation in fp32 and from some reference, I think that it can send ...
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156 views

How to find the dynamic energy of a processor without using capacitive load?

I have the following question: A cell phone performs very different tasks, including streaming music, streaming video, and reading email. These tasks perform very different computing tasks. Battery ...

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