Questions tagged [computer-architecture]
Computer architecture refers to both the design of a computer's external interfaces (instruction sets) and a computer's internal implementation (microarchitecture). The goal of these design decisions is to optimize speed, power efficiency, size, or cost while satisfying constraints on the rest.
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Why wide demux allows the partitioning of memory bandwidth to be able to change over time? [closed]
I have recently read an article, and one of the sentences said:
For example, the demux used in the read network has the ability to direct all of the read bandwidth to any of the read ports on any ...
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Is it possible to make the "arithmetic" part of the ALU to be mircoprogrammed?
We know that the Arithmetic and Logic Unit in CPU is a hardware, it is a combinational circuit. Binary addition, for example, is very fast because it doesn't have to be microprogrammed; there is ...
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Understanding decode stage of x86 fetch-decode-execute pipeline and its (lack of) register requirements
FDE pipeline has register requirements for the F & D stages: For fetching an instruction from memory, the instruction pointer register points to the memory location of the next instruction to be ...
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How are `call` and `return` usually implemented in microarchitecture? [closed]
This is a follow-on from this question:
Are `call` and `return` usually instructions in a modern ISA?
I'd like to implement call and ...
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Are `call` and `return` usually instructions in a modern ISA?
I've been working through the problems in a game based around building a Turing Complete machine.
One of the final problems asks you to implement the call and ...
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Why does the Fused Multiply Add CSA use the inverted MSB of the addend when one multiply operand is negative?
I found one valuable paper about the "Fused Multiply Add":
Instead of using 161-bit CSA, Only the 106 least-significant bits of the
aligned A are needed as input to the 3:2 CSA, because the ...
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Alu Control output not return 010 for Addi instruction
I'm currently working on a project for a MIPS Datapath Simulation website. The project aims to demonstrate how instructions work. I've implemented the Alu Control Unit using the combinational logic ...
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Electrical/physical difference between Primary Memory and Secondary Memory connection to CPU
It is said that the difference between primary memory and secondary memory is that primary memory is "directly accessible by CPU", while secondary memory is "not directly accessible by ...
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Retrieval of information from a sequential circuit
SR-NOR Latch circuit is a sequential circuit in which there exist two, different modes Reset and Set. Electricity flows along ...
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Direct Mapping of 8GByte memory with 64-bit addressable word size
The question: A computer has 8 GByte of memory with 64-bit addressable word sizes. Each block of memory stores 16 words. The computer has a direct-mapping cache of 128 blocks
Calculate the tag bits, ...
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DRAM/DDR energy consumption
I have some questions about the origin of energy consumption in DRAM based memories/systems. In Mark Horowitz paper Computing’s Energy Problem
(and what we can do about it) the author breaks down the ...
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How does CPU's Machine Check Architecture work?
Modern CPUs can alert the OS when itself is malfunctioning, i.e. logically incorrect, and apparently, this is supported by a hardware diagnostic feature called Machine Check Architecture. I can ...
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Mark Horowitz Computing's energy problem - methodology
I have a question about the Mark Horowitz paper: Computing’s Energy Problem
(and what we can do about it). In the paper, the author breaks down the sources of energy loss in modern computing systems.
...
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Computer Board and Raspberry
I have a question for which I haven't found any source to explain it to me. For personal projects raspberry pi is usually used as computer. How it is substituted in commercial products? Do they make ...
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Is floating point IEEE754 binary digit represented using special unit/circuit for arithmetic operation?
We know that two un/signed integers arithmetic operation using special circuit called full-adder to execute arithmetic operation in Arithmetic Logic Unit (ALU).
The full-adder I mean is classical ...
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Why do we need stalls even if branches can be determined?
I am learning about pipelining and was reading about control hazards from the book Computer Organization and Design: The Hardware/Software Interface (MIPS Edition). There is a paragraph in the book (...
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Can components like EPROM or NE 555 timer be built from scratch?
I was watching some videos on building an 8-bit computer and plan to do so myself, however, I wondered if it was possible to make something like an EPROM or 555 timers from scratch using basic ...
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Can we service another memory request from L1 cache when an L1 miss is being serviced from L2?
Consider the case where L1 cache miss occurred and is being serviced by L2 cache which could take many cycles (may go to main memory in case of L2 cache miss). In the meantime L1 cache is idle, in ...
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What is a PCS accumulator?
I'm currently doing my bachelor's thesis in electronics. While reading an article, I stumbled upon the sentence "The FPU is based on a PCS accumulator...".
What does PCS stand for? I can't ...
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Which devices supply input signals for transistors in a computer?
In a computer, I understand that the transistors are used to make up logic gates. For each transistor, there is a current (voltage) that controls the base terminal with the logic "low/high ...
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What is a chip generator?
I've been trying to learn more about the RISC-V environment. I've encountered a chip generator called Rocket Chip.
What is a chip generator, and how does it differ from a core? I'm trying to ...
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Which kinds of embedded platforms can be considered well-suited for acquiring a general taste of interrupts? [closed]
I'm an application programmer without much knowledge in low-level programming. I've set up a basic toolchain for assembly programming with the ATMega328P on an Arduino Uno R3 board. One of my aims is ...
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Need help with implementing beq instruction control signals
I'm currently working on an Assignment, and I'm unsure if I did everything right, for example implementing the control signals for the beq instruction. I have added the required signals to the Control ...
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Help with Register File Implementation on Logisim
I'm currently working on an assignment that involves implementing a register file with 2 read ports and 1 write port on Logisim. I've made some progress but I'm struggling with a few questions and ...
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How to estimate how bad the wire delay can be when I am designing a chip?
I am currently working on a program involves designing a Neural Network accelerator architecture. I don't have a very deep background in digital circuit, but I know long wires may incur heavy delay ...
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Need help understanding speedup in parallel computing [closed]
I am currently studying computer architecture and I am having some trouble understanding the concept of speedup in parallel computing. I came across the following statement: "Before the multicore ...
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Designing instruction emulating swap on a MIPS ISA with only 2 registers
In a typical MIPS ISA, you have only 2 working registers. But you have a large number of ALU units.
How to design an instruction to emulate swap?
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What provides the clock signal in CSI2 interface?
What provides the clock signal for the CSI2 interface used for many cameras? Does the camera provide it or is it the processor the camera is interfacing to?
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Confirming the solution for control signals of "addi" instruction, and seeking help with other specified instructions
I am seeking clarification on a problem I have been working on related to control signals in a computer architecture. The problem is as follows:
"Consider the datapath in Figure 1 and the ...
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Are there any fields in EE that overlap with Quantum informatics/computing nowadays? [closed]
As I understand it, research in quantum information and computing has traditionally been confined to physics and applied physics/math departments. It seems to me that many of the practical challenges ...
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A simple question on pipelined MIPS
For branches/jumps the PC is always muxed from the MEM stage. Why don't we mux it from the EX stage itself instead?
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Computer architecture: Count of RAM, ROM and I/O interface addressing
I am trying to work through this question and I appreciate any help or hint. Thank you
Problem:
A computer system uses RAM chips of size 512x8 and ROM chips of size 256x8. The computer system needs 4k ...
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How do you fit so many instructions on a 8-bit processor?
I will preface this that it is highly likely that I have misunderstood how Harvard architecture works, but I cannot understand how an 8-bit instruction set, say the ATmega128 for example, can contain ...
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How different layers of cache connect in hardware?
I had a RISC-V CPU with L1 Instruction Cache and L1 Data Cache, and I want to connect these two L1 Caches to unified L2 Cache. I have the following questions:
Does the unified L2 Cache have dual port ...
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Generating Control Signals via Case statement vs Boolean function
I'm building a RISC-V processor recently, and I've encountered a question when constructing the control unit. That is, what's the difference between generating control signals through:
Case statement,...
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How to solve pipeline hazards using stalls?
So, I have the following code, which should run on a five-stage pipeline (Fetch, Decode, Execute, Memory, Write). Now, we need only to consider read-after-write data dependencies and find the total ...
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How can memories be implemented efficiently with memory blocks of different sizes?
I am unsure if I am framing the question correctly, but here's what I wanted to ask.
Let's say we want to implement a 64 kB memory. We would require a 16-bit address if we have byte-addressable memory....
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SRT division: correcting BSD quotient
I have been reading a lot about the SRT division algorithm lately and I understand that the main idea is that it allows us to skip over addition/subtraction, unlike non-restoring division where we ...
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Mitigating structural hazards in register files in processor pipelines
I am reading about structural hazards in pipelined architecture in processors. In classic RISC pipeline one such hazard is when we write and read simultaneously to same register, which may cause ...
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How to using JAL in RISCV in this example?
Write a "replace" function that replaces every character in the source string between the first occurrence of character "(" and the first following ")" with character &...
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What is the rationale behind enforcing WDATA ordering in AXI3?
While trying to understand the AXI protocol,I came across this:
Write data on the W channel must follow the same order as the address transfers on the AW channel.
from https://developer.arm.com/...
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Is there any difference between a CPU core and a CPU itself?
I was reading this article that explains the difference between a thread and a core and it says the following:
...
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How are BAR registers handled between end points in PCI Express?
I have a question related to the PCI Express protocol.
I managed to understand most of the features of the PCI Express protocol but could not entirely understand the enumeration process.
I know the ...
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Differences in capacitive loads
I'm in school and I am trying to figure out a question for homework. It reads as stated:
Version
Voltage
Clock Rate
i.
Version 1
1.75V
1.5 GHz
Version 2
1.2V
2 GHz
ii.
Version 1
1.1V
3 GHz
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How to do signed 16-bit arithmetic on an 8-bit processor?
For example, to add two 16-bit numbers on my 8 bit machine, I add the low bytes together, then the high bytes together, and then add the carry flag to the high byte of the output.
This strategy falls ...
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Program counter updating in a single-cycle ARM processor
This picture is from the book Digital Design and Computer Architecture: ARM Edition. It implements the LDR instruction.
I have one question:
R15 is supposed to be PC+8. In the picture, is R15 ...
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Why do we need nonlinear electronics for computing?
When I read about photonics, I always see that they can be used for linear transformations (just matrix multiplications), and that this is a limitation that makes them unsuitable for building a ...
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Implementing functional design of a computer system into physical hardware [duplicate]
I have recently started studying computer organisation and found that in most of the books the design of computer system is not discussed beyond functional design abstraction level (as shown in the ...
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Functional design implementation of computer system into actual physical hardware
I have recently started studying computer organisation and found that in most of the books the design of computer system is not discussed beyond functional design abstraction level (as shown in the ...
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How is sll implemented in MIPS?
I don't understand how MIPS would implement the sll (shift left logical) instruction using the hardware present in its ALU as shown in the diagrams below. Would ...
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