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Questions tagged [computer-architecture]

Computer architecture refers to both the design of a computer's external interfaces (instruction sets) and a computer's internal implementation (microarchitecture). The goal of these design decisions is to optimize speed, power efficiency, size, or cost while satisfying constraints on the rest.

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Finding speedup in instruction pipeline with branch prediction

I was solving below exercise problem from book Computer Architecture and Design by Patterson at al. This could be more mathematical / logical doubt than electronics related doubt. Breakdown of ...
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1answer
21 views

Understanding branch delay slot and branch prediction prefetch in instruction pipelining

Let me define: Branch delay slot: Typically assemblers reorder instructions to move some instructions immediately after branch instruction, such that the moved instruction will always be executed, ...
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25 views

Finding speedup when branch prediction is done in instruction decode phase of processor pipeline instead of execute stage

I was solving problems from the exercise of the book "Computer Organization and Design" by Patterson. The problem reads like this: Assume instructions: ...
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40 views

Black lines on laptop appear even laptop is switched off? [on hold]

This definitely doesn't make sense, but the persistent black horizontal lines on my laptop appear even when my laptop is switched off. The normal Color of laptop screen when switched off is a bit ...
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17 views

Finding percentage memory utilization in pipelining architecture

I was solving problems from the exercise of the book "Computer Organization and Design" by Patterson. The problem reads like this: Consider stage latencies: ...
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33 views

What are the characteristic differences between ARM and PowerPC architectures? [closed]

I am trying to study the differences between ARM and PowerPC architectures inside a microcontroller. Can someone please explain the differences ?
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46 views

Is it posible that two devices plugged in different PCI slots share single PCI bus

Let's assume we have two network cards, Foo and Bar plugged in slots 5 and 4 on motherboard, with some BDF id assigned, for example: Foo => 09:00.0 Bar => 02:00.0 That's the usual scenario. But is ...
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40 views

Intel Compute Stick & USB 4G Device

Id like to create a powerful IoT Edge device that has cellular capability (Wifi is undesirable). Right now the intel compute stick/neural stick almost fits the bill except that it does not have 4G ...
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54 views

Home brew CPU register trouble shooting

update Apparently I’m an idiot. It took me this long (hours) to check the supply voltage of the flip flops, which was at .25 volts from a bad connection. Rookie mistake. Hard lesson learnt. In the ...
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1answer
83 views

What is the purpose of Delayed Branching? [closed]

I study solutions of control hazards in a processor. One method is delayed branching. To my understanding, specific number of instructions (depending on pipeline length) are always executed subsequent ...
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34 views

Renaming a special register

I noticed that RISC-V, like some other RISC architectures, by convention treats register 1 specially, using it as the link register, holding the return address for function calls. If most code ...
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31 views

Branch Prediction in a superscalar processor?

Let's take the case of a two-wide superscalar processor (It can fetch two words from the cache every cycle). Also, the processor supports compressed instructions. So, in a single cycle, it can ...
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57 views

What is von Neumann bottleneck?

According to this Quora post, It refers to two things: A systems bottleneck, in that the bandwidth between Central Processing Units and Random-Access Memory is much lower than the speed at ...
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3answers
95 views

How did the Commodore 64 keyboard work?

I'm designing a computer using a Z80 processor (I know, not the same as the one the C64 used, it doesn't matter) I found the following schematic showing part of the C64 circuit, and I'm particularly ...
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1answer
36 views

branch address computation single-cycle vs multi-cycle vs pipeline risc-v

I'm not sure about at which stage do the address computation take place at each of the versions of the risc-v? I just wanted to make sure i got that right- Single-cycle risc-v: Branch target address ...
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60 views

Cache miss types: capacity miss vs. conflict miss

Categorizing Cache Misses I was wondering if somebody could provide an example illustrating a capacity miss in contrast to a conflict miss for a 2-way cache with arbitrarily small line size and cache ...
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1answer
81 views

Difference between a Embedded controller and a northbridge [closed]

I found the terms 'Embedded Controller' 'Northbridge' 'southbridge' 'Platform Controller Hub' 'super I-O' and I am not sure to understand the difference. Northbridge and southbride difference is ...
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3answers
150 views

Getting CPU clock signal out of computer (as to measure externally) [closed]

I've been searching on the internet some clock generator module capable of reaching up to 1GHz, when I just realized that the machine I'm using to search has one CPU with its own 2.5-3.0 GHz clock... ...
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203 views

How many stall cycles resulted by incorrectly predicted branch in instruction pipelining

I have been solving following exercise problem from book Computer Organization by Patterson and Hennessy: The importance of having a good branch predictor depends on how often conditional branches ...
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4answers
125 views

What is the purpose behind multiple addressing modes in a processor [closed]

Processors usually have multiple addressing modes. All processors do not have the same exact same list of addressing modes. When exactly was idea of different addressing modes conceived? Why do we ...
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1answer
35 views

How to calculate the cycle time of pipeline

I have an 8-stage pipeline (IF,ID,OF1,OF2,OF3,Ex1,Ex2,WB) with respective stage delays as 5ns,4ns,10ns,6ns,8ns,11ns,9ns,13ns respectively. The interstage registers have delay of 1ns. I think here the ...
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4answers
113 views

Can I calculate how much time it will take for an electrical signal to propagate through a TTL circuit?

Given a particular circuit of TTL, can I calculate how much time it will take for an electrical signal to propagate through some section, or all of, the circuit? If I wanted to know how long it ...
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1answer
70 views

There's Conflicts in the Definitions of XNOR? [duplicate]

XNOR has two definitions: \$1^{st}:XNOR=NOT(XOR)\$ \$2^{nd}: XNOR(A,B)=\overline{A}\cdot\overline{B}+A\cdot B\$ The problem is that these definitions are not equal in Odd inputs, the second ...
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1answer
96 views

Why is it that true random number generators are not in every computer? [closed]

I understand that one of the fundamental pillars of the programmable computer, is that we should implement features with software rather than hardware, anytime it is possible & more efficient (or ...
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1answer
90 views

Can a computer increase its memory in machine cycle? [closed]

For my college assignment, one of the question asks to explain how a computer increases its memory in machine cycle. I have searched and so far I have found that a computer can't increase it's own ...
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4answers
132 views

In general, how do I know if my project needs a file system? [closed]

This question gives a good high-level overview of when an operating system is appropriate on an embedded platform. The three topics mentioned are networking requirements, GUI requirements, and file ...
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1answer
75 views

How does the computer's BIOS change the clock speed?

A computer's BIOS can change either the multiplier value or the (FSB) clock frequency to overclock or underclock a CPU. While overclocking by changing the multiplier value is easier and in more often ...
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100 views

multi-cycle risc-v ZERO control line for branch

I have been having trouble to understand how exactly the execute stage in risc-v processor for branch works. what I understood is that the ZERO output from ALU calculations for branch produces zero ...
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2answers
108 views

MAR vs Stack Pointer, Whats the difference?

So I was watching some videos on a guy "Building his own 8-bit computer", and the Memory Address Register (MAR) was attached to the SRAM. The MAR took the next Program Counter value and then looked in ...
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39 views

How do I draw the truth table of an adder/subtractor that sets flags, and those flags are the inputs of a comparator?

How do I draw a truth table of a circuit that : starts off with a full adder/subtractor outputs the result F based on the two inputs (add if opcode is 0, subtract if opcode is 1) then output three ...
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1answer
101 views

Simplest display for homemade 8080 based computer-what to use? [closed]

I'm designing a 8080 processor based computer and I want it to be able to at least output something visually. I have thought about using SMD LED matrix made by myself, but even with the 160 x 120 px ...
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2answers
92 views

DIP (dual inline package) [closed]

searching on the net, but couldnt understand for what is used DIP? Is it RAM? Will be glad for your answers.
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3answers
178 views

Would a standardized graphics chip socket be sensible? [closed]

I am not an EE, and so I'm running this conjecture on breaking out the GPU from the CPU by folks who have better knowledge than me. Perhaps you can point out something I don't know about modern CPU ...
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1answer
84 views

The number of cycles needed to execute the following loop in pipeline processor?

This question was asked in an objective paper; GATE CSE Consider a 4 stage pipeline processor. The number of cycles needed by the four instructions I1, I2, I3, I4 in stages S1, S2, S3, S4 is shown ...
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Why are NAND gates used to make AND gates in computers?

Why is this a standard for AND gates when it could be made with two FETs and a resistor instead?
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2answers
423 views

mips single-cycle branch verilog

I'm fairly new to Verilog, hardware design and computer architecture. Nevertheless, I've had a go at designing a simplified MIPS processor. It seems to mostly work fine but whenever I simulate it, it ...
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8answers
8k views

Why is digital serial transmission used everywhere? i.e. SATA, PCIe, USB

While looking at SATA, PCIe, USB, SD UHS-II it struck me that they are all the same: digital serial bitstream, transmitted using differential pairs (usually 8b/10b coded), with some differences in ...
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2answers
136 views

AI hardware architecture

I am looking for more info on AI hardware architectures, but I am a bit confused. Here are my questions: Does it all come down to MACs(Multiply And Accumulate) units? Do MACs usually integrate into ...
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2answers
104 views

Are floating point numbers denormalised before the processor performs arithmetic operations on them? [closed]

Does the processor denormalise the numbers in IEEE 754 notation and normalise the result after storing or are the arithmetic operations performed on the numbers as they are? I'm asking because in case ...
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1answer
265 views

Is this microcode control store realistic as a hardware implementation?

In a simple control unit using microcoded sequencing, I use a ROM to store the sequences of control signals. The instruction forms the top 8 bits of the ROM address, and the bottom eight bits are ...
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164 views

Booth bit-pair recoding of multipliers

1) How to multiply a multiplicand with 2, using Booth' bit-pair recoding technique? 2) In booth's algorithm for multiplication/Booth's bit-pair recoding of multipliers, we must extend the sign bit of ...
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4answers
5k views

Why isn't the BIOS' ROM chip made using CMOS technology?

After reading a computer hardware course on BIOS/CMOS, I'm still unable to determine the reason why the BIOS' ROM chip isn't built using CMOS technology, and why it is connected to a separate chip ...
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1answer
83 views

Flushing in pipelined architectures

How is the flushing really implemented? I have an idea that on conditional branches, the prior instructions are flushed. But how are they actually flushed?
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0answers
43 views

DRAM write operation

In a typical read operation from a dram chip, all the banks are equipped with sense amplifiers which select one bit from each bank using column multiplexer. But how does write operation takes place? ...
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5answers
4k views

Why are DIMMs not equipped with a heat sink like a CPU?

I know that a DIMM is composed of a set of chips that contain control logic managing the decode and prefetching memory operations. According to a product specification, I found that newer RAM works at ...
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2answers
124 views

how does program counter stores the instruction memory when program is loaded? [closed]

it is mentioned in the book computer organization and design by Patterson/Hennessy page 252 that: The instruction memory need only provide read access because the datapath does not write ...
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1answer
117 views

In which CPUs will write-after-write and write-after-read dependencies cause a hazard?

I've been studying the MIPS single cycle architecture for pipeline. I noticed that read-after-write dependency causes a data hazard but two other write-after-write and write-after-read dependencies ...
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2answers
221 views

Computer architecture why is MemRead used?

Why is a control signal MemRead needed for the Data Memory element if whenever the output Read Data is not desired it will be multiplexed out via MemtoReg? Wouldn't having MemRead always enabled ...
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1answer
55 views

Thermal overload trip in chips

I have read that the thermal design power (TDP) is an important metric while considering energy and power trade off related to microcontrollers. It is said that TDP determines the cooling required and ...
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3answers
239 views

Can a processor do a for loop within 1 clock pulse?

I am in a digital circuits class. In this class we are using verilog to simulate (but not actually physically synthesize) different circuits. We have an assignment where we are supposed to simulate a ...