Questions tagged [computer-architecture]

Computer architecture refers to both the design of a computer's external interfaces (instruction sets) and a computer's internal implementation (microarchitecture). The goal of these design decisions is to optimize speed, power efficiency, size, or cost while satisfying constraints on the rest.

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How does ROM work?

ROM is a major part of a computer, and even more so in gaming consoles. How exactly do they work, and how can you make them with logic gates/transistors? I'm currently working on many projects, ...
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Effect of doubling clock frequency on computer performance

If we double the clock frequency of a CPU, does that translate to a doubling of the CPU performance? Assuming that the number of instructions and CPI are constant, we have an inverse relationship ...
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I am trying to implement a datapath using sequential logic . Trying to implement this C program

I was thinking of creating three registers , namely X, Y and Z. I initialize x and y to constants of '0', then I make register Z an active low register. I send a constant ' 0 ' to the input line of ...
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Sequence Detector forced to wait a specific number of bits

So I have this little problem, where I am supposed to build a sequence detector which is forced to wait a specific number of bits before going into the reset state. It's kind of like pin codes work. ...
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What consumes the most power in a computer

I have a quite basic question: As far as I understand (correct me if I am wrong), we can summarize a computer by saying it is composed of wiring, transistors and some electronic components like ...
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Implementing ADD instruction for RiSC-16 processor

I'm trying to implement the RiSC-16 (not RISC) processor documented here using Verilog. The processor is really simple, however there is a problem when you try to perform ADD instructions ...
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Does stage Sy of instruction have to wait till all earlier instructions has executed their corresponding stage

I am trying to understand execution of instruction in RISC pipeline. Can stage Sy of instruction I2 execute before stage Sy of I1? That is, in below example, will it be allowed to run I2's ID in C3 ...
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What differentiates Laptops from PCs in terms of power consumption?

Today I as a Computer Scientist stumbled about some strange facts. Recently, I bought a new Macbook Model 16" inch. Today I tried to stress test it because I wondered if the 96 Watt charging cable ...
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What is an emulator POD?

Jack Ganssle - The Firmware Handbook States ...
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Cortex-M3, Code region vs SRAM/RAM

In the ARM Cortex-M3 processor core, the memory map contains: a Code region, SRAM and a RAM. What makes the use of the code region different than the other memories? In addition, what is the nature of ...
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What is the effect of multiple Register file ports of a CPU?

Register file ports are a means to get data in and out of registers in a CPU. The concept of having multiple ports is not too clear to me. QUESTION Assuming you have 2 read ports, does it mean ...
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How come decimal to BCD encoder has 10 input lines

Came across to study about decimal to BCD encoder and noticed it has 10 input lines, and four output lines but encoder should have 2 pow n input lines, so I doubt 10 cannot be in the form of 2 pow n!...
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Worst case scenerio in carry skip adder?

I am having trouble understanding this. worst case operation time takes place when carry is generated in the first block carry skips intermediate stages carry is killed in the last ...
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Are Tri-state buffers even necessary?

I'm trying to make a 1-bit computer, and I'm stuck on the registers. I think I am going to have 2 of them, and I want a way to separate their outputs. Let me explain. Let's say Register A has a 0, and ...
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Why did only a few companies make microcomputers to begin with? [closed]

I was watching a program about Clive Sinclair and they used to advertise a computer and then design and build it within 3-6 months. So 8-bit computers must have been fairly simple to design and build....
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Where in the instruction pipeline is machine code to microcode translation?

In my computer architecture courses on the N-stage pipeline, I never encountered the concept of microcode. I was surprised, then, when in a performance analysis course assignment, I discovered that ...
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Thoughts & questions on custom CPU architecture

I'm designing a CPU architecture. I've come up with a preliminary design: I'd like general thoughts on what I can improve in the design and also I have some specific questions: Is it overkill to ...
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1answer
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The accurate time latency for 'lw' instruction in a single-cycle datapath

I want to calculate the cycle time of a single-cycle datapath. Then from the course, I know the time should be the execution time of the longest instruction, which is 'lw' in MIPS. So I try to ...
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Designing a cryptographic S-Box in Logisim

I am currently working in Logisim and was wondering if I can design some ciphers in the same. One such cipher is PRESENT cipher which is essentially a block cipher. I did get that I need to design the ...
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How many ALUs (and threads) are in a Pentium CPU?

I'm reading a book bottom up where it said: The Arithmetic Logic Unit (ALU) is the heart of the CPU operation. It takes values in registers and performs any of the multitude of operations the ...
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1answer
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CPU cache write policy - evict already dirty? + storage of memory address

I'm reading about cache in wiki https://en.m.wikipedia.org/wiki/CPU_cache and the following phrase seems not clear. Also, a write to a main memory location that is not yet mapped in a write-back ...
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how to determine architecture core detail of ARM11 processor

I'm cross-compiling for an embedded Linux board, based in BCM5892 ARM11 processor. I need to know about architecture detail of this processor(‘armv6’, ‘armv6j’, ‘armv6k’, ‘armv6kz’, ‘armv6t2’, ‘...
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Is there any memory cell that can store more than one bit? [closed]

SRAM, DRAM, Flash, EPROM - all of the memory cells contain one bit of data each. Is there any memory cell that can store more than one bit, e.g. 2 bits/4bits?
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Why must a block in NAND SSDs be erased before it can be reprogammed? [closed]

Before programming a NAND based SSD in page-level we have to always erase by block-level which increases write amplification. why is it so and how do we mitigate it? what is the necessity of erasing ...
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Why is the Digital 0 not 0V in computer systems?

I'm taking a computer system design course and my professor told us that in digital systems, the conventional voltages used to denote a digital 0 and a digital 1 have changed over the years. ...
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How does a computer chip read code, interpret it, and convert it into action? [closed]

I understand that binary is effectively functioning as a “virtual representation” of low voltage and high voltage. However, I do not understand how the instruction set to MAKE the voltage high or low ...
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8085 μp; Why does Read cycle take 3 T-states and not 2?

In the text I'm following, R.S.Gaonkar it's explained that, During T1, address in Program Counter(PC) is latched onto the Memory Address Register(MAR), During the falling edge of T2 \$\overline{MEMR}...
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1answer
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8085 MPU; Stepping through an instruction (Timing diagrams)

Let me write the steps of ADD B, as I've understood it till now. T0: ALE goes high Memory location(say \$2000_h\$) is taken from Program Counter to Memory Address Register(which points to the ...
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Approaches to storing and addressing microcode for homebrew CPU

I've been teaching myself about CPU architecture for a while now and have successfully designed a couple myself. They were always based around microcode to drive the CPU's control lines. The ...
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What kind of hardware multiplier do modern processors use?

I was wondering what kind of multiplier implementations modern processors use. Is it some derived variant of booth Wallace tree algorithm? Are these kinds of micro-architectural details publicized ...
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Why does Intel's Haswell chip allow floating point multiplication to be twice as fast as addition?

I was reading this very interesting question on Stack Overflow: Is integer multiplication really done at the same speed as addition on a modern CPU? One of the comments said: "It's worth nothing ...
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1answer
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Where to study Cortex R architecture? [closed]

I am interested to study Cortex-R architecture but I cannot find its details online. Is it proprietary detail or should I ask for this information from arm.com? Obviously I am not looking for the ...
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1answer
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68008 Main board Review [closed]

I'm building a retro computer around the 68008 CPU The main board will be simple, The CPU, 1MB of RAM, and a 32kB ROM (Bios/boot rom) here is the adress map $000000 - $07FFFF : RAM0 $080000 - $...
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1answer
180 views

RISC-V: building a datapath for conditional Branch instructions

I am simulating a multi-cycle 32bit RISC-V CPU in Logisim-Evolution and so far so good, i had implemented almost every instruction from the basic RV32I ISA. But im having trouble to understand how the ...
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What is the simplest instruction set that has a C++/C compiler to write an emulator for? [closed]

I'm looking into writing a little software emulator that emulates/runs instructions. The easiest would be to invent my own instruction set, but I thought it would be more fun if I write an emulator ...
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4answers
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Do smaller transistors improve computational efficiency because they decrease the duration of signal transfer?

There has been a massive improvement of computational power of computers per $ over time. As far as I understand, this has been driven almost completely by the massive increase in transistors per ...
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2answers
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What does it means that a MCU has support for OpenGL?

I am trying to understand the meaning of when someone says that PowerPC 7410 CPU has support for OpenGL based software. Does it mean that there are any specific instruction in its ISA architecture ...
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1answer
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How does the north-bridge (or analogous hardware) route memory reads and writes? [closed]

I would be tempted to think that there is some kind of parallel cache-line kind of mechanism, that works on registers that are set by the north-bridge drivers. But then, most architectures only allow ...
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1answer
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Microprocessor architecture bits vs bus sizes

I am ready following on this website: "Another big difference between 32-bit processors and 64-bit processors is the maximum amount of memory (RAM) that is supported. 32-bit computers support a ...
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1answer
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Why is wave pipelining so rarely used?

Wave pipelining (a technique of removing latch overheads by having two or more "waves" propagate through a multi-cycle pipeline stage) has been used in the past for pipelining cache access (HP PA-7000?...
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External bus interfacing

This lab requires us to extend the memory and I/O ports on our µPad using our EBI backpack. What I'm confused about is how the fully address decoded SRAM will differ from the partially addressed i/o ...
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Choosing the best approach for data selection in a datapath

For a university project, I have to design and construct a very simple CPU including the ALU. In order to select between different data lines that go into the ALU(32-bit data line), I have thought of ...
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What information exactly does an instruction cache store?

Processors use both data and instruction caches in order to reduce the number of slow accesses to main memory. However, while it is clear to me that the data cache's purpose is to store frequently ...
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1answer
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Why do we need 'R_out' in 2-BUS arch?

Given some abstract architecture of CPU: Note that this CPU has 2-BUS. Why do we need the R_out and R_in? If I use Gra/Grb/Grc then obviousely I will need R_out. The Same for R_in when I use Sra/Srb/...
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Can a classical Toffoli gate be built from irreversible gates?

The Toffoli gate is a reversible gate with three inputs (A, B, C) and three outputs (S1, S2, S3) generated as S1 = A S2 = B S3 = AB ^ C It can be implemented in a classic way using the following ...
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Finding speedup in instruction pipeline with branch prediction

I was solving below exercise problem from book Computer Architecture and Design by Patterson at al. This could be more mathematical / logical doubt than electronics related doubt. Breakdown of ...
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Understanding branch delay slot and branch prediction prefetch in instruction pipelining

Let me define: Branch delay slot: Typically assemblers reorder instructions to move some instructions immediately after branch instruction, such that the moved instruction will always be executed, ...
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Finding speedup when branch prediction is done in instruction decode phase of processor pipeline instead of execute stage

I was solving problems from the exercise of the book "Computer Organization and Design" by Patterson. The problem reads like this: Assume instructions: ...
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Finding percentage memory utilization in pipelining architecture

I was solving problems from the exercise of the book "Computer Organization and Design" by Patterson. The problem reads like this: Consider stage latencies: ...
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1answer
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Is it posible that two devices plugged in different PCI slots share single PCI bus

Let's assume we have two network cards, Foo and Bar plugged in slots 5 and 4 on motherboard, with some BDF id assigned, for example: Foo => 09:00.0 Bar => 02:00.0 That's the usual scenario. But is ...

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