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Questions tagged [computer-architecture]

Computer architecture refers to both the design of a computer's external interfaces (instruction sets) and a computer's internal implementation (microarchitecture). The goal of these design decisions is to optimize speed, power efficiency, size, or cost while satisfying constraints on the rest.

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72 views

Thoughts & questions on custom CPU architecture

I'm designing a CPU architecture. I've come up with a preliminary design: I'd like general thoughts on what I can improve in the design and also I have some specific questions: Is it overkill to ...
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25 views

The accurate time latency for 'lw' instruction in a single-cycle datapath

I want to calculate the cycle time of a single-cycle datapath. Then from the course, I know the time should be the execution time of the longest instruction, which is 'lw' in MIPS. So I try to ...
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73 views

Designing a cryptographic S-Box in Logisim

I am currently working in Logisim and was wondering if I can design some ciphers in the same. One such cipher is PRESENT cipher which is essentially a block cipher. I did get that I need to design the ...
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2answers
109 views

How many ALUs (and threads) are in a Pentium CPU?

I'm reading a book bottom up where it said: The Arithmetic Logic Unit (ALU) is the heart of the CPU operation. It takes values in registers and performs any of the multitude of operations the ...
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1answer
28 views

CPU cache write policy - evict already dirty? + storage of memory address

I'm reading about cache in wiki https://en.m.wikipedia.org/wiki/CPU_cache and the following phrase seems not clear. Also, a write to a main memory location that is not yet mapped in a write-back ...
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2answers
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how to determine architecture core detail of ARM11 processor

I'm cross-compiling for an embedded Linux board, based in BCM5892 ARM11 processor. I need to know about architecture detail of this processor(‘armv6’, ‘armv6j’, ‘armv6k’, ‘armv6kz’, ‘armv6t2’, ‘...
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3answers
119 views

Is there any memory cell that can store more than one bit? [closed]

SRAM, DRAM, Flash, EPROM - all of the memory cells contain one bit of data each. Is there any memory cell that can store more than one bit, e.g. 2 bits/4bits?
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1answer
63 views

Why must a block in NAND SSDs be erased before it can be reprogammed? [closed]

Before programming a NAND based SSD in page-level we have to always erase by block-level which increases write amplification. why is it so and how do we mitigate it? what is the necessity of erasing ...
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7answers
8k views

Why is the Digital 0 not 0V in computer systems?

I'm taking a computer system design course and my professor told us that in digital systems, the conventional voltages used to denote a digital 0 and a digital 1 have changed over the years. ...
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3answers
147 views

How does a computer chip read code, interpret it, and convert it into action? [closed]

I understand that binary is effectively functioning as a “virtual representation” of low voltage and high voltage. However, I do not understand how the instruction set to MAKE the voltage high or low ...
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1answer
64 views

8085 μp; Why does Read cycle take 3 T-states and not 2?

In the text I'm following, R.S.Gaonkar it's explained that, During T1, address in Program Counter(PC) is latched onto the Memory Address Register(MAR), During the falling edge of T2 \$\overline{MEMR}...
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1answer
53 views

8085 MPU; Stepping through an instruction (Timing diagrams)

Let me write the steps of ADD B, as I've understood it till now. T0: ALE goes high Memory location(say \$2000_h\$) is taken from Program Counter to Memory Address Register(which points to the ...
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2answers
121 views

Approaches to storing and addressing microcode for homebrew CPU

I've been teaching myself about CPU architecture for a while now and have successfully designed a couple myself. They were always based around microcode to drive the CPU's control lines. The ...
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1answer
101 views

What kind of hardware multiplier do modern processors use?

I was wondering what kind of multiplier implementations modern processors use. Is it some derived variant of booth Wallace tree algorithm? Are these kinds of micro-architectural details publicized ...
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6answers
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Why does Intel's Haswell chip allow FP multiplication to be twice as fast as addition?

I was reading this very interesting question on Stack Overflow: Is integer multiplication really done at the same speed as addition on a modern CPU? One of the comments said: "It's worth nothing ...
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1answer
83 views

Where to study Cortex R architecture? [closed]

I am interested to study Cortex-R architecture but I cannot find its details online. Is it proprietary detail or should I ask for this information from arm.com? Obviously I am not looking for the ...
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1answer
103 views

68008 Main board Review [closed]

I'm building a retro computer around the 68008 CPU The main board will be simple, The CPU, 1MB of RAM, and a 32kB ROM (Bios/boot rom) here is the adress map $000000 - $07FFFF : RAM0 $080000 - $...
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1answer
84 views

RISC-V: building a datapath for conditional Branch instructions

I am simulating a multi-cycle 32bit RISC-V CPU in Logisim-Evolution and so far so good, i had implemented almost every instruction from the basic RV32I ISA. But im having trouble to understand how the ...
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9answers
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What is the simplest instruction set that has a C++/C compiler to write an emulator for? [closed]

I'm looking into writing a little software emulator that emulates/runs instructions. The easiest would be to invent my own instruction set, but I thought it would be more fun if I write an emulator ...
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4answers
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Do smaller transistors improve computational efficiency because they decrease the duration of signal transfer?

There has been a massive improvement of computational power of computers per $ over time. As far as I understand, this has been driven almost completely by the massive increase in transistors per ...
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2answers
95 views

What does it means that a MCU has support for OpenGL?

I am trying to understand the meaning of when someone says that PowerPC 7410 CPU has support for OpenGL based software. Does it mean that there are any specific instruction in its ISA architecture ...
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1answer
44 views

How does the north-bridge (or analogous hardware) route memory reads and writes? [closed]

I would be tempted to think that there is some kind of parallel cache-line kind of mechanism, that works on registers that are set by the north-bridge drivers. But then, most architectures only allow ...
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1answer
137 views

Microprocessor architecture bits vs bus sizes

I am ready following on this website: "Another big difference between 32-bit processors and 64-bit processors is the maximum amount of memory (RAM) that is supported. 32-bit computers support a ...
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1answer
88 views

Why is wave pipelining so rarely used?

Wave pipelining (a technique of removing latch overheads by having two or more "waves" propagate through a multi-cycle pipeline stage) has been used in the past for pipelining cache access (HP PA-7000?...
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1answer
39 views

External bus interfacing

This lab requires us to extend the memory and I/O ports on our µPad using our EBI backpack. What I'm confused about is how the fully address decoded SRAM will differ from the partially addressed i/o ...
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1answer
38 views

Choosing the best approach for data selection in a datapath

For a university project, I have to design and construct a very simple CPU including the ALU. In order to select between different data lines that go into the ALU(32-bit data line), I have thought of ...
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3answers
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What information exactly does an instruction cache store?

Processors use both data and instruction caches in order to reduce the number of slow accesses to main memory. However, while it is clear to me that the data cache's purpose is to store frequently ...
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1answer
68 views

Why do we need 'R_out' in 2-BUS arch?

Given some abstract architecture of CPU: Note that this CPU has 2-BUS. Why do we need the R_out and R_in? If I use Gra/Grb/Grc then obviousely I will need R_out. The Same for R_in when I use Sra/Srb/...
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0answers
62 views

Can a classical Toffoli gate be built from irreversible gates?

The Toffoli gate is a reversible gate with three inputs (A, B, C) and three outputs (S1, S2, S3) generated as S1 = A S2 = B S3 = AB ^ C It can be implemented in a classic way using the following ...
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0answers
36 views

Finding speedup in instruction pipeline with branch prediction

I was solving below exercise problem from book Computer Architecture and Design by Patterson at al. This could be more mathematical / logical doubt than electronics related doubt. Breakdown of ...
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1answer
45 views

Understanding branch delay slot and branch prediction prefetch in instruction pipelining

Let me define: Branch delay slot: Typically assemblers reorder instructions to move some instructions immediately after branch instruction, such that the moved instruction will always be executed, ...
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29 views

Finding speedup when branch prediction is done in instruction decode phase of processor pipeline instead of execute stage

I was solving problems from the exercise of the book "Computer Organization and Design" by Patterson. The problem reads like this: Assume instructions: ...
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0answers
19 views

Finding percentage memory utilization in pipelining architecture

I was solving problems from the exercise of the book "Computer Organization and Design" by Patterson. The problem reads like this: Consider stage latencies: ...
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1answer
57 views

Is it posible that two devices plugged in different PCI slots share single PCI bus

Let's assume we have two network cards, Foo and Bar plugged in slots 5 and 4 on motherboard, with some BDF id assigned, for example: Foo => 09:00.0 Bar => 02:00.0 That's the usual scenario. But is ...
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47 views

Intel Compute Stick & USB 4G Device

Id like to create a powerful IoT Edge device that has cellular capability (Wifi is undesirable). Right now the intel compute stick/neural stick almost fits the bill except that it does not have 4G ...
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66 views

Home brew CPU register trouble shooting

update Apparently I’m an idiot. It took me this long (hours) to check the supply voltage of the flip flops, which was at .25 volts from a bad connection. Rookie mistake. Hard lesson learnt. In the ...
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1answer
107 views

What is the purpose of Delayed Branching? [closed]

I study solutions of control hazards in a processor. One method is delayed branching. To my understanding, specific number of instructions (depending on pipeline length) are always executed subsequent ...
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0answers
38 views

Renaming a special register

I noticed that RISC-V, like some other RISC architectures, by convention treats register 1 specially, using it as the link register, holding the return address for function calls. If most code ...
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0answers
32 views

Branch Prediction in a superscalar processor?

Let's take the case of a two-wide superscalar processor (It can fetch two words from the cache every cycle). Also, the processor supports compressed instructions. So, in a single cycle, it can ...
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0answers
94 views

What is von Neumann bottleneck?

According to this Quora post, It refers to two things: A systems bottleneck, in that the bandwidth between Central Processing Units and Random-Access Memory is much lower than the speed at ...
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3answers
141 views

How did the Commodore 64 keyboard work?

I'm designing a computer using a Z80 processor (I know, not the same as the one the C64 used, it doesn't matter) I found the following schematic showing part of the C64 circuit, and I'm particularly ...
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1answer
153 views

branch address computation single-cycle vs multi-cycle vs pipeline risc-v

I'm not sure about at which stage do the address computation take place at each of the versions of the risc-v? I just wanted to make sure i got that right- Single-cycle risc-v: Branch target address ...
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0answers
159 views

Cache miss types: capacity miss vs. conflict miss

Categorizing Cache Misses I was wondering if somebody could provide an example illustrating a capacity miss in contrast to a conflict miss for a 2-way cache with arbitrarily small line size and cache ...
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1answer
104 views

Difference between a Embedded controller and a northbridge [closed]

I found the terms 'Embedded Controller' 'Northbridge' 'southbridge' 'Platform Controller Hub' 'super I-O' and I am not sure to understand the difference. Northbridge and southbride difference is ...
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3answers
167 views

Getting CPU clock signal out of computer (as to measure externally) [closed]

I've been searching on the internet some clock generator module capable of reaching up to 1GHz, when I just realized that the machine I'm using to search has one CPU with its own 2.5-3.0 GHz clock... ...
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0answers
497 views

How many stall cycles resulted by incorrectly predicted branch in instruction pipelining

I have been solving following exercise problem from book Computer Organization by Patterson and Hennessy: The importance of having a good branch predictor depends on how often conditional branches ...
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4answers
209 views

What is the purpose behind multiple addressing modes in a processor [closed]

Processors usually have multiple addressing modes. All processors do not have the same exact same list of addressing modes. When exactly was idea of different addressing modes conceived? Why do we ...
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1answer
193 views

How to calculate the cycle time of pipeline

I have an 8-stage pipeline (IF,ID,OF1,OF2,OF3,Ex1,Ex2,WB) with respective stage delays as 5ns,4ns,10ns,6ns,8ns,11ns,9ns,13ns respectively. The interstage registers have delay of 1ns. I think here the ...
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4answers
116 views

Can I calculate how much time it will take for an electrical signal to propagate through a TTL circuit?

Given a particular circuit of TTL, can I calculate how much time it will take for an electrical signal to propagate through some section, or all of, the circuit? If I wanted to know how long it ...
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1answer
73 views

There's Conflicts in the Definitions of XNOR? [duplicate]

XNOR has two definitions: \$1^{st}:XNOR=NOT(XOR)\$ \$2^{nd}: XNOR(A,B)=\overline{A}\cdot\overline{B}+A\cdot B\$ The problem is that these definitions are not equal in Odd inputs, the second ...