Questions tagged [computer-architecture]

Computer architecture refers to both the design of a computer's external interfaces (instruction sets) and a computer's internal implementation (microarchitecture). The goal of these design decisions is to optimize speed, power efficiency, size, or cost while satisfying constraints on the rest.

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Confusion about IJVM

I was reading the chapter 4 of the book 'Computer Architecture' by Tanenbaum (since my copy is not in English maybe the title of the English version is not exactly that one), however it is the chapter ...
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Does the memory bus span multiple layers on die?

My question is if you take any model desktop CPU such as the ones manufactured by Intel would the design of the memory bus span multiple layers of a single die or would it be contained on a single ...
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Are coarse-grained reconfigurable architectures a subset of dataflow architecture?

By definition, dataflow architectures consist of large modules in the dataflow path, such as adders and multipliers for integer, floating-point, or fixed-point computation. Hence, are coarse-grained ...
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What is the cost of increasing the number of register names?

Increasing the number of registers in a CPU, has the upside that more values can be kept in registers instead of having to spill to stack. It has some downsides, one of which is that more instruction ...
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66 views

Computers: How signals in the bus can travel in either direction [closed]

I'm reading J. Clark Scott's book But How Do It Know. When he is describing registers and the bus he illustrates this at one point as five registers sequentially parallel-connected to a bus. As you ...
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How does CDB mastering work in Tomasulo's algorithm?

I understand that implementations of Tomasulo's algorithm feature a common data bus (CDB) that each functional unit writes its output to. Each reservation station can listen on the CDB for its ...
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1answer
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How does CPU control implement pipeline stall [closed]

The original question was deemed lack of focus. This post is specifically about cpu pipeline stall. How does synchronous microarchitecture implement pipeline stall when a cache miss occurs during ...
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1answer
77 views

How does Asynchronous DRAM perform self-timing

The original question was deemed lack of focus. This post is specifically about dram chip. When DRAM controller talks to an asynchronous DRAM, how does DRAM itself know when a write is completed and ...
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1answer
157 views

Are processor instruction sets royalty free? (e.g. ARM v9, x86)

I asked a general question on Law SE with one example (ARM) and for that example, I was directed to What exactly does ARM sell to vendors?. I've read that QA that ARM sells actual core designs. I've ...
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2answers
123 views

Transistors collector input output of other transistor?

I'm new to computer science and trying to learn the basics. Have learnt how to create logical gates using simple components like relays, thanks to nandgame.com. This was easy, boolean functions, have ...
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Can a pin to DDR4 be as thin as household tinfoil? (0.016 mm)

Edit: I think using the term "bus" might be wrong here. A "bus" needs to be large enough to facilitate an entire DDR4 stick's bandwidth to the Northbridge. The connection to each ...
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2answers
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Which bus protocol(s) does a motherboard use to connect to RAM?

I'm trying to learn about the protocols busses use in computer engineering and so far I've learned about the CAN bus protocol, where you can even watch traffic on the busses with wireshark, but this ...
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Question about computer engineering circuits (noob question) [closed]

I'm currently self learning computer engineering stuff right now and I was wondering how RAM would work in terms of input and output and I stumbled upon this image I think it's somewhat wrong from ...
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Estimating current draw for a single instruction

I am a software engineer concerned about current draw. I am aware that there are ways to reduce the current draw of a program, for example: using a hlt instruction ...
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1answer
83 views

Internal differences between CPUs of the same architecture

What is the difference between, for example an Intel i3-4005U (1.7 GHz) and an Intel i3-4025U (1.9 GHz)? These CPUs are from the same generation, have the same amount of cores, cache, iGPU, and ...
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3answers
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What is the difference between stalling and flushing in a microprocessor?

As the title suggests, I want to understand the difference. Attaching the reference.
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What is a hardware thread in RISC-V?

RISC-V PMP limits the physical addresses accessible by software running on a hart (hardware thread). Source: edX course on Introduction to RISC-V, Chapter 4. Developing RISC-V, The Privileged ...
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Is it true that CISC architectures generally consume more power than RISC architectures?

I keep hearing CISC architectures consume more power than RISC architectures. This is said to be the reason for using RISC architectures for low-power applications. I am a skeptic, I think it could be ...
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How does an operating system or program detect the CPU model name? [closed]

What kind of binary compatibility is present for 2 processors sharing an Instruction Set?. I had asked a question on Computer Science Stack Exchange, to which I got an answer which said: As a trivial ...
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1answer
154 views

Where is the RAM stored on a RISC-V CPU? [closed]

Does RISC-V have any opinion on whether the RAM is stored on the same chip as the CPU (like on ARM devices) or on a separate chip somewhere on the motherboard (like on an x86 desktop)? I assume that ...
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What mechanism prevents me from initializing multiple peripherals on the same GPIO pin?

Can I initialize multiple peripherals on the same GPIO pin? For example, if I bind a GPIO with a peripheral, can I still manipulate this pin with the GPIO interface? With pseudo-code: ...
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1answer
202 views

Why can't an Asynchronous CPU use a simple "completion bit" to signal completion?

I've been reading about how asynchronous CPUs work, but they always seem to involve some complicated way of communication. Wikipedia talks about a two-way and four-way handshake. I found a pdf from ...
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1answer
68 views

Size of a memory cache

Assuming we have a virtual address issued by a model CPU that contains a total of 32 bits and 20 bits of this address are reserved for the tag + the cache comprises a total of 1024 cache lines. Should ...
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1answer
328 views

Logisim: Implementing a control unit for "Addition", "Logic bitwise AND" and "right logic shift" in ALU [closed]

I'm very new to circuit design. I've built an ALU and now I only need a control unit for three operations, "Addition", "Logic bitwise AND" and "right logic shift". What ...
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Read after Write and Write after write dependencie at the same time

Assuming the following pseudo-code down bellow: 1)r1 = 4 2)r2 = 5 3)r3 = r1 + 5 4)r4 = r2 + r1 5)r4 = r4 + r3 6)r1 = 10 7)r7 = r1 - 1 the r4 on line 5 is both name ...
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How can I fix delay between Instruction and Program Counter?

I am designing the MIPS processor, this includes Data Memory and Instruction memory for testing. I had a problem with IM synthesis covered in this question (How to make a synthesizable Instruction ...
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The concept of DDR rank

I have an understanding of DDR rank which I think is incorrect. If someone could join the dots then there would be more clarity. Here is what I know A DDR rank is a 64bit interface consisting of x8 ...
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Can I have some help compacting this?

I am trying to build a transistor computer, and I want to save as much resources as possible. However, I also want it to be practical, so I am implementing a binary-decimal conversion. In order to ...
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How much faster is the ideal machine without the memory structural hazard versus the machine with the hazard?

I am learning computer architecture and organization. I have the following doubt. Given below is a question along with its solution but I think that the solution is wrong. You can see the question ...
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1answer
91 views

With what stage of the branch instruction does the IF stage executes if the branch is taken?

I am learning computer architecture and organization. I have the following doubt. Given below is a question along with its solution but I think that the solution is wrong. Consider an instruction ...
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2answers
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What is the most important CPU price factor [closed]

I have two intel CPUS with distinct features. intel i7 8550U intel i5 8300H Which have big performance difference with the cheaper 8300H being higher in memory ...
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1answer
194 views

Is bit stuffing done after 6 or 5 consecutive 1's? [closed]

I am learning computer architecture and organization. I have the following doubt. I have read that in bit stuffing a 0 is inserted whenever 6 consecutive 1’s are encountered. However, it may be noted ...
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1answer
240 views

Why is programmed I/O not suitable for high-speed data transfer?

I am learning about computer architecture and organization. I have read that programmed I/O is not suitable for high-speed data transfer because it does not support synchronous mode of data ...
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2answers
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Can synchronous data transfer be used for transferring large data in case of computer architecture and organization? [closed]

I am learning computer architecture and organization. I have this confusion, can synchronous data transfer be used for transferring large data in case of computer architecture and organization? I ...
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4answers
919 views

Why is asynchronous data transfer only suitable for slow devices?

I have read that asynchronous data transfer is wasteful of CPU time for slow devices like keyboard or mouse. Then how is it possible that it is suitable only for slow devices like keyboard or mouse ...
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Difficulty in understanding the concept of operand forward in pipeling and when to use split phase

Given below is a question from \$\text{GATE } 2015 \text{ CS}\$ paper, Consider the sequence of machine instruction given below: \begin{array}{ll} \text{MUL} & \text{R5, R0, R1} \\ \text{DIV} &...
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Is it correct that in a hard disk both surfaces of each disk are capable of storing data?

I have read that in a hard disk both surfaces of each disk are capable of storing data except the top and bottom disk where only the inner surface is used. Is it correct if yes then why is are there ...
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1answer
74 views

Average data transfer rate

I am learning computer architecture and organization I am stuck in the following question. Consider a hard disk with sector size 1024 bytes, 5000 tracks per surface, 64 sectors per track, and 8 ...
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1answer
203 views

How to calculate the bandwidth of a synchronous bus with overlap in bus transfer and reading next data?

I am working through problems in Saylor Academy's computer architecture course. I can't understand how this kind of problem is solved: Consider a 32-bit synchronous bus with f = 125 Mhz, an 8 nsec ...
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1answer
92 views

Throughput increase/decrease by how much percent

I am learning computer architecture and organization. I am stuck in the following question. Can someone please help me? The stage delays in a 5-stage pipeline are 300, 200, 100, 400 and 350 ...
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1answer
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How is the exponent expressed in single precision floating-point number representation using IEEE-754 format

I am learning computer architecture and organization. I am stuck in the following question. Can someone please help me? How is the exponent expressed in single precision floating-point number ...
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2answers
240 views

The minimum (negative) value of the exponent in decimal

I am learning computer architecture and organization. I am stuck in the following question. Can someone please help me? For a floating-point representation with 35 bits in the mantissa and 15 bits in ...
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1answer
91 views

differences between mini pcie vs half height mini pcie

I want to use a mini- PCIe half height to connect a communication module to my PCB. For example- to use a board like the raspberry pi 4 compute module io board with a WiFi expansion board. Given that ...
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1answer
482 views

Is it possible to remove the write back stage in 5-stage pipeline?

In this graph, can we simply remove the write back stage since the mux is pushed back into the memory access stage and there is no logic in the write back stage. Is it because of the register file ...
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349 views

How are irrational numbers best represented and processed by computers?

My question is closely related to this one: How do computers understand decimal numbers? However, that question deals with rational numbers only. I was wondering if irrational numbers can be ...
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2answers
153 views

VHDL: port declaration design for a feedback signal

I am a Computer Engineering student currently learning computer architecture, and working on modeling a booth's algorithm in VHDL. My design hierarchy contains a datapath and a control unit. The ...
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4answers
497 views

Can an FPGA/ASIC have an Operating System?

I know FPGA/ASIC are for a specific task and they are not microprocessors and an OS is needed mainly if multiple processes(tasks) need to be run concurrently. Just wondering if an FPGA/ASIC can have ...
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2answers
83 views

VHDL: on variable declarations to act as register

I am currently a CPE student taking up computer architecture, learning how to model major computer components using VHDL. Currently, I am working on a shift register as a sub component for a top-level ...
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2answers
170 views

Difference between ARM7 and intel i3, i5 & i7 processors

I am just starting out on a journey to understand microcontroller and microprocessor design. Have read briefly on their differences (ARM7 and Intel i3, i5 & i7). Couldn't find any information on ...
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1answer
113 views

Doubt in pipelining forwarding in MIPS

I am fairly new to computer architecture and having a tough time solving problems based on pipelining. I was trying to solve a problem from this pdf I found on Google I have a doubt in part ...

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