All Questions
Tagged with computer-architecture microcontroller
30 questions
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does data and instruction memory we see in the data path corresponds to the L1 Instruction and Data cache inside of the core?
In CPU data path there are blocks called data memory and instruction memory ? Are these blocks L1 Instruction and L1 data caches ?
For instance check figure 4.10 in this link.
We know that generally ...
0
votes
1
answer
92
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Is it possible to make the "arithmetic" part of the ALU to be mircoprogrammed?
We know that the Arithmetic and Logic Unit in CPU is a hardware, it is a combinational circuit. Binary addition, for example, is very fast because it doesn't have to be microprogrammed; there is ...
- 453
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2
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306
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How are `call` and `return` usually implemented in microarchitecture? [closed]
This is a follow-on from this question:
Are `call` and `return` usually instructions in a modern ISA?
I'd like to implement call and ...
- 399
3
votes
1
answer
323
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Are `call` and `return` usually instructions in a modern ISA?
I've been working through the problems in a game based around building a Turing Complete machine.
One of the final problems asks you to implement the call and ...
- 399
11
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3
answers
3k
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Why do we see one, unified memory address space in ARM Cortex-M core based MCUs even though they have Harvard architecture?
Most of the ARM Cortex-M core based MCUs have Harvard architecture (except for Cortex-M0 and M0+.)
The thing I do not understand is that why we see only one memory address space. For example, in tge ...
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6
answers
1k
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Estimating current draw for a single instruction
I am a software engineer concerned about current draw.
I am aware that there are ways to reduce the current draw of a program, for example:
using a hlt instruction ...
1
vote
0
answers
145
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DMA SPI performance
I am currently writing an SD card driver for a Microcontroller using SPI and DMA. The SPI has a FIFO that can store 4 data values from the data register which has the capable of storing 32 bit. But it ...
- 11
2
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5
answers
2k
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How does a microprocessor control its transistors? [closed]
Or in other words, what is the more fundamental building block of an IC below transistors? When I load a code onto my microprocessor, how (fundamentally, sure some people here could write books about ...
- 253
1
vote
1
answer
62
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Need Help Identifying [closed]
This is a Board off a 8tb WD Hard Drive. I plug in the wrong power and i believe the little thing with the S on it is bad. I do not know what it is call or where i could find another, any help would ...
- 19
0
votes
1
answer
2k
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SRAM and D-flip flop instead of transistor
I have read about the internal structure of SRAM and we need 6 transistors to store 1 bit.
But what bothers me is why can't it be made using D-flip flops instead of going deep to transistor-level. It ...
0
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3
answers
314
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Implementing ADD instruction for RiSC-16 processor
I'm trying to implement the RiSC-16 (not RISC) processor documented here using Verilog.
The processor is really simple, however there is a problem when you try to perform ADD instructions ...
- 163
1
vote
1
answer
507
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8085 μp; Why does Read cycle take 3 T-states and not 2?
In the text I'm following, R.S.Gaonkar it's explained that,
During T1, address in Program Counter(PC) is latched onto the Memory Address Register(MAR),
During the falling edge of T2 \$\overline{MEMR}...
- 551
1
vote
1
answer
128
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8085 MPU; Stepping through an instruction (Timing diagrams)
Let me write the steps of ADD B, as I've understood it till now.
T0:
ALE goes high
Memory location(say \$2000_h\$) is taken from Program Counter to Memory Address Register(which points to the ...
- 551
3
votes
2
answers
648
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What does it means that a MCU has support for OpenGL?
I am trying to understand the meaning of when someone says that PowerPC 7410 CPU has support for OpenGL based software. Does it mean that there are any specific instruction in its ISA architecture ...
- 1,489
4
votes
1
answer
753
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Microprocessor architecture bits vs bus sizes
I am ready following on this website:
"Another big difference between 32-bit processors and 64-bit processors is the maximum amount of memory (RAM) that is supported. 32-bit computers support a ...
- 1,489
1
vote
1
answer
71
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External bus interfacing
This lab requires us to extend the memory and I/O ports on our µPad using our EBI backpack. What I'm confused about is how the fully address decoded SRAM will differ from the partially addressed i/o ...
-2
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2
answers
147
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What is the best communication mechanism with collision detection/avoidance for my topology?
Here is my sensor topology..
Here, the atmega128 is the main controller and all other atmega8 are connected to the main controller using rs485 cable.
What is the best communication protocol for this ...
8
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4
answers
5k
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Why should I learn a microcontroller architecture? [closed]
I recently started working in a small company that produces automotive diagnose related electronics. My boss, who is in his mid 50's, said that he was using 8051 derivatives, and they were doing the ...
- 952
0
votes
2
answers
13k
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barrel shifter using multiplexer: how to go about it
I am trying to under stand how to build a barrel shifter using multiplexers.
I understand how the barrel shifter works but I don't get how you decide the number of multiplexers to use, and how the ...
- 103
27
votes
6
answers
10k
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Why are relatively simpler devices such as microcontrollers so much slower than CPUs?
Given the same number of pipeline stages and the same manufacturing node (say, 65 nm) and the same voltage, simple devices should run faster than more complicated ones. Also, merging multiple pipeline ...
- 431
4
votes
1
answer
599
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What multi/many-core (micro)processors/controllers should I use for "embarrassingly parallel" computations? [closed]
This is my first question ever on this site, so I hope I don't mess this up. :D
I'll try to be as specific as possible.
What I need:
Something that I can program in C (or a C-like language).
I need ...
1
vote
3
answers
338
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Benefit of (logically/virtually) separate I/O and memory bus
In my course on embedded systems, it is explained that memory inputs can be separated from I/O inputs using a "mode bit" for the address decoder. The most obvious advantage of this is that the amount ...
- 281
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3
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317
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How Can A Coded Firmware Control Hardware [closed]
I really want to know how could a virtual coded program really affect and imitate and animate a piece of hardware.
I Have Always Seen The Diagram Of Processors In the Book Showing ALU and CPU as The ...
- 648
1
vote
1
answer
717
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implementing direct addressing mode for a load instruction on a mips archtitecture
Given a Mips machine with 26 bit addresses and 32 bits data-paths, where the load instruction is as follows
|OPT code|rs|rd|immediate|
|6 bits |5 bits|5 bits|16 bits|
The OPT code is the ...
- 113
4
votes
2
answers
2k
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How does a ps2 mouse send data to a computer? [closed]
I want to read data from a mouse with the help of Arduino.
I want to calculate relative motion between two objects.
My questions are
1) Is it possible?
2) How is mouse interfaced with Arduino?
9
votes
3
answers
1k
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CPUs for retro computer school project
I'm a student in an IT school and we are trying to think of a project we could use to show 1st year students how things work behind the stage and we eventually thought of making a retro computer.
I'...
0
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2
answers
2k
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Programming microcontrollers in ASM or C & how it's done
Just to clarify on these topics:
If I were to program a microcontroller in ASM I would use an assembler, of course. The assembler would compile the code into opcodes (machine code?)(generally 1:1 ...
- 3,461
1
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0
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3k
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SAP-1 (Simple as Possible) W Bus
I'm currently investigating the SAP-1 to build in order to grasp a really good understanding of simple 8 bit computers.
There are a few questions that I would like clearing up.
What exactly is the ...
- 321
2
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2
answers
1k
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Does anyone know the hardware of a Nike+ SportWatch GPS? [closed]
I have one of these devices and I would really love to figure out if it is possible to write and push my own firmware into the device. The software on the watch is pretty limited and I would like to ...
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13
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2
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16k
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Using CCM (Core Coupled Memory) in STM32F4xx
STM32F4xx microcontrollers have 128KB of SRAM + 64KB of CCM SRAM. CMM SRAM is hardwired to data bus so it is impossible to use it with DMA.
What is the reason to add additional SRAM as CCM?
Does it ...
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