All Questions
12 questions
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does data and instruction memory we see in the data path corresponds to the L1 Instruction and Data cache inside of the core?
In CPU data path there are blocks called data memory and instruction memory ? Are these blocks L1 Instruction and L1 data caches ?
For instance check figure 4.10 in this link.
We know that generally ...
0
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1
answer
92
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Is it possible to make the "arithmetic" part of the ALU to be mircoprogrammed?
We know that the Arithmetic and Logic Unit in CPU is a hardware, it is a combinational circuit. Binary addition, for example, is very fast because it doesn't have to be microprogrammed; there is ...
- 453
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2
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306
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How are `call` and `return` usually implemented in microarchitecture? [closed]
This is a follow-on from this question:
Are `call` and `return` usually instructions in a modern ISA?
I'd like to implement call and ...
- 399
3
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1
answer
323
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Are `call` and `return` usually instructions in a modern ISA?
I've been working through the problems in a game based around building a Turing Complete machine.
One of the final problems asks you to implement the call and ...
- 399
2
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5
answers
2k
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How does a microprocessor control its transistors? [closed]
Or in other words, what is the more fundamental building block of an IC below transistors? When I load a code onto my microprocessor, how (fundamentally, sure some people here could write books about ...
- 253
1
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1
answer
507
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8085 μp; Why does Read cycle take 3 T-states and not 2?
In the text I'm following, R.S.Gaonkar it's explained that,
During T1, address in Program Counter(PC) is latched onto the Memory Address Register(MAR),
During the falling edge of T2 \$\overline{MEMR}...
- 551
1
vote
1
answer
128
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8085 MPU; Stepping through an instruction (Timing diagrams)
Let me write the steps of ADD B, as I've understood it till now.
T0:
ALE goes high
Memory location(say \$2000_h\$) is taken from Program Counter to Memory Address Register(which points to the ...
- 551
1
vote
1
answer
71
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External bus interfacing
This lab requires us to extend the memory and I/O ports on our µPad using our EBI backpack. What I'm confused about is how the fully address decoded SRAM will differ from the partially addressed i/o ...
27
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6
answers
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Why are relatively simpler devices such as microcontrollers so much slower than CPUs?
Given the same number of pipeline stages and the same manufacturing node (say, 65 nm) and the same voltage, simple devices should run faster than more complicated ones. Also, merging multiple pipeline ...
- 431
4
votes
1
answer
599
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What multi/many-core (micro)processors/controllers should I use for "embarrassingly parallel" computations? [closed]
This is my first question ever on this site, so I hope I don't mess this up. :D
I'll try to be as specific as possible.
What I need:
Something that I can program in C (or a C-like language).
I need ...
0
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3
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317
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How Can A Coded Firmware Control Hardware [closed]
I really want to know how could a virtual coded program really affect and imitate and animate a piece of hardware.
I Have Always Seen The Diagram Of Processors In the Book Showing ALU and CPU as The ...
- 648
9
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3
answers
1k
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CPUs for retro computer school project
I'm a student in an IT school and we are trying to think of a project we could use to show 1st year students how things work behind the stage and we eventually thought of making a retro computer.
I'...
