All Questions
Tagged with computer-architecture microprocessor
72 questions
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does data and instruction memory we see in the data path corresponds to the L1 Instruction and Data cache inside of the core?
In CPU data path there are blocks called data memory and instruction memory ? Are these blocks L1 Instruction and L1 data caches ?
For instance check figure 4.10 in this link.
We know that generally ...
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1
answer
92
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Is it possible to make the "arithmetic" part of the ALU to be mircoprogrammed?
We know that the Arithmetic and Logic Unit in CPU is a hardware, it is a combinational circuit. Binary addition, for example, is very fast because it doesn't have to be microprogrammed; there is ...
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2
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306
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How are `call` and `return` usually implemented in microarchitecture? [closed]
This is a follow-on from this question:
Are `call` and `return` usually instructions in a modern ISA?
I'd like to implement call and ...
- 399
3
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1
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323
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Are `call` and `return` usually instructions in a modern ISA?
I've been working through the problems in a game based around building a Turing Complete machine.
One of the final problems asks you to implement the call and ...
- 399
3
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2
answers
149
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What is a PCS accumulator?
I'm currently doing my bachelor's thesis in electronics. While reading an article, I stumbled upon the sentence "The FPU is based on a PCS accumulator...".
What does PCS stand for? I can't ...
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2
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1
answer
168
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What is a chip generator?
I've been trying to learn more about the RISC-V environment. I've encountered a chip generator called Rocket Chip.
What is a chip generator, and how does it differ from a core? I'm trying to ...
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1
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1
answer
231
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Mitigating structural hazards in register files in processor pipelines
I am reading about structural hazards in pipelined architecture in processors. In classic RISC pipeline one such hazard is when we write and read simultaneously to same register, which may cause ...
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3
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3
answers
625
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Processor Design: Just how complex is a real CPU datapath?
We're doing a course on Computer Architecture, and the course project involves creating an ARM-based processor.
We're supposed to create the processor in stages, and add significant features in each ...
- 352
3
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4
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3k
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How do processor transistor counts keep increasing, without geometric scaling?
Reading into the history of the semiconductor industry and Moore's Law, and looking at the ITRS/IRDS documents, I understand that scaling down and modern node names (7nm, 5nm etc) are now "...
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0
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41
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Are coarse-grained reconfigurable architectures a subset of dataflow architecture?
By definition, dataflow architectures consist of large modules in the dataflow path, such as adders and multipliers for integer, floating-point, or fixed-point computation.
Hence, are coarse-grained ...
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463
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How does CPU control implement pipeline stall [closed]
The original question was deemed lack of focus. This post is specifically about cpu pipeline stall.
How does synchronous microarchitecture implement pipeline stall when a cache miss occurs during ...
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3
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2k
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What is the difference between stalling and flushing in a microprocessor?
As the title suggests, I want to understand the difference. Attaching the reference.
- 107
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61
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Difficulty in understanding the concept of operand forward in pipeling and when to use split phase
Given below is a question from \$\text{GATE } 2015 \text{ CS}\$ paper,
Consider the sequence of machine instruction given below:
\begin{array}{ll} \text{MUL} & \text{R5, R0, R1} \\ \text{DIV} &...
- 155
4
votes
1
answer
802
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Is it possible to remove the write back stage in 5-stage pipeline?
In this graph, can we simply remove the write back stage since the mux is pushed back into the memory access stage and there is no logic in the write back stage. Is it because of the register file ...
- 113
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2
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393
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Difference between ARM7 and intel i3, i5 & i7 processors
I am just starting out on a journey to understand microcontroller and microprocessor design. Have read briefly on their differences (ARM7 and Intel i3, i5 & i7).
Couldn't find any information on ...
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3
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2
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182
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Soft errors from SEUs/SETs in early 8-bit microprocessors?
Why is it that soft errors due to single-event upsets/transients never seemed to be a problem in early 8-bit microprocessors, like the MOS 6502 or the Zilog Z80? The microprocessors themselves were ...
- 131
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161
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What processor architecture is in a 230GMULps KPU design?
While AI products are becoming popular recently, when looking at the "Seeed Studio Grove AI HAT for Edge Computing Artificial Intelligence Board" it mentions a RISC-V, a 230GMULps 16-bit KPU ...
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5
answers
2k
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How does a microprocessor control its transistors? [closed]
Or in other words, what is the more fundamental building block of an IC below transistors? When I load a code onto my microprocessor, how (fundamentally, sure some people here could write books about ...
- 253
2
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1
answer
3k
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MIPS clock cycle calculation formula
How many clock cycles will take execution of this segment on the simple pipeline without forwarding or bypassing when result of the branch instruction (new PC content) is available after WB stage. ...
- 21
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0
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34
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Does stage Sy of instruction have to wait till all earlier instructions has executed their corresponding stage
I am trying to understand execution of instruction in RISC pipeline.
Can stage Sy of instruction I2 execute before stage Sy of I1? That is, in below example, will it be allowed to run I2's ID in C3 as ...
- 227
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1
answer
2k
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The accurate time latency for 'lw' instruction in a single-cycle datapath
I want to calculate the cycle time of a single-cycle datapath. Then from the course, I know the time should be the execution time of the longest instruction, which is 'lw' in MIPS.
So I try to ...
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3
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617
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how to determine architecture core detail of ARM11 processor
I'm cross-compiling for an embedded Linux board, based in BCM5892 ARM11 processor.
I need to know about architecture detail of this processor(‘armv6’, ‘armv6j’, ‘armv6k’, ‘armv6kz’, ‘armv6t2’, ‘...
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1
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507
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8085 μp; Why does Read cycle take 3 T-states and not 2?
In the text I'm following, R.S.Gaonkar it's explained that,
During T1, address in Program Counter(PC) is latched onto the Memory Address Register(MAR),
During the falling edge of T2 \$\overline{MEMR}...
- 551
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1
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128
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8085 MPU; Stepping through an instruction (Timing diagrams)
Let me write the steps of ADD B, as I've understood it till now.
T0:
ALE goes high
Memory location(say \$2000_h\$) is taken from Program Counter to Memory Address Register(which points to the ...
- 551
5
votes
2
answers
589
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Approaches to storing and addressing microcode for homebrew CPU
I've been teaching myself about CPU architecture for a while now and have successfully designed a couple myself. They were always based around microcode to drive the CPU's control lines.
The microcode ...
- 187
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1
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71
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External bus interfacing
This lab requires us to extend the memory and I/O ports on our µPad using our EBI backpack. What I'm confused about is how the fully address decoded SRAM will differ from the partially addressed i/o ...
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1
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3k
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Understanding branch delay slot and branch prediction prefetch in instruction pipelining
Let me define:
Branch delay slot: Typically assemblers reorder instructions to move some instructions immediately after branch instruction, such that the moved instruction will always be executed, ...
- 227
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0
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53
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Finding percentage memory utilization in pipelining architecture
I was solving problems from the exercise of the book "Computer Organization and Design" by Patterson. The problem reads like this:
Consider stage latencies:
...
- 227
3
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2
answers
5k
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How many stall cycles resulted by incorrectly predicted branch in instruction pipelining
I have been solving following exercise problem from book Computer Organization by Patterson and Hennessy:
The importance of having a good branch predictor depends on how often conditional branches ...
- 227
3
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1
answer
117
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Thermal overload trip in chips
I have read that the thermal design power (TDP) is an important metric while considering energy and power trade off related to microcontrollers. It is said that TDP determines the cooling required and ...
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3
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7k
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What is the role of ISA (Instruction Set Architecture) in the comp arch abstraction stack. [closed]
I have programming background, and I recently started taking computer architecture course. Most of the lectures I see use the some sort of the layering as described in the following diagram explaining ...
- 379
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1
answer
240
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Is it realistic to expect full Spectre fix in branch predictors of future CPUs?
Recently, it has been observed that two branches sharing the same branch predictor state in the same process or even across processes allows certain side channel exploits (Spectre).
Let's consider a ...
- 1,906
-1
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1
answer
398
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Finding percentage accuracy of instruction pipeline branch predictor
I need help in understanding the solution from solution manual. The question is from the exercise 4.24.4 and 4.24.5 of chapter 4 in the book Computer Organization and Design by Patterson and Hannessey ...
- 139
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1
answer
754
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Understanding execution of sequence of pipeline instructions
I need help in understanding the solution from solution manual. The question is from the exercise 4.22.2 of chapter 4 in the book Computer Organization and Design by Patterson and Hannessey (4th ...
- 139
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1
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349
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Understanding instruction branching
I need help in understanding the solution from solution manual. The question is from the exercise 4.22.1 of chapter 4 in the book Computer Organization and Design by Patterson and Hannessey (4th ...
- 139
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0
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746
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Understanding instruction pipelining speedup calculation
I was solving the exercise problem 4.17.6 of chapter 4 in the book Computer Organization and Design by Patterson and Hannessey (4th edition):
Percentage occurrences of the instructions are as ...
- 139
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1
answer
1k
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Understanding processor instruction pipeline problem solution
I need help in understanding the solution from solution manual.
The question is from the exercise 4.13.5 of chapter 4 in the book Computer Organization and Design by Patterson and Hannessey (4th ...
- 139
0
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1
answer
227
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Hows does a processor physically do calculations? [closed]
What should I know to understand how a processor performs computations, at the level of the electron (concerning adders,gates,etc.)?
Suppose I already know the logic side of the issue, i.d. how ...
- 21
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1
answer
55
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Minimal components for arm A9 dev board
If someone wanted to make a barebones dev board, what is needed to get an a9 processor running? Is it reasonable for a school project or will attempting to route the ddr memory and getting it ...
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1
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632
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ARM architecture question [closed]
What is the role of marked area? Where is the address going? Also shouldn't there be an arrow from instruction decoder leading somewhere?
I know basics of comp arch and know am aware of program ...
- 13
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1
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79
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Implementation of multiplier system of processor using sequence system - is it possible?
I am in the course of learning about the processor, sequential systems, etc. I came across this question:
Is multiplier processor may be implemented as a sequence system?
I can not answer that. Can ...
- 111
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1
answer
476
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little endian processor and big endian processor - save number to memory
Processor save 32 bits number(123456780)_8 at address 1000. We would like to know what ...
user119974
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vote
2
answers
390
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considerations about little endian processor and opeartions on registers
Processor is little-endian.
Under followings addresses we have following values (hexdecimal format):
1000: FA
1001: 46
1002: 26
1003: C3
Now, processor is ...
user119974
27
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6
answers
10k
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Why are relatively simpler devices such as microcontrollers so much slower than CPUs?
Given the same number of pipeline stages and the same manufacturing node (say, 65 nm) and the same voltage, simple devices should run faster than more complicated ones. Also, merging multiple pipeline ...
- 431
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2
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164
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Exclusive execution unit in pipeline stage for execution of memory access instructions
I was studying pipeline concept in microarchitecture. My professor told me that memory read and write operations take longer time to execute since DRAM has a maximum frequency of 1333Mhz. Hence, when ...
4
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1
answer
599
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What multi/many-core (micro)processors/controllers should I use for "embarrassingly parallel" computations? [closed]
This is my first question ever on this site, so I hope I don't mess this up. :D
I'll try to be as specific as possible.
What I need:
Something that I can program in C (or a C-like language).
I need ...
1
vote
1
answer
5k
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single cycle vs multicycle datapath execution times
I have a question where I need to calculate the execution time for a program for single cycle and multicycle datapath. I think I may be doing it incorrectly since the multicycle execution time is ...
- 65
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1
answer
1k
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Micro and Nano Memory, Calculate Reducing Bits?
I ran into a question:
in digital system with micro-programmed control circuit, total of 32 distinct pattern operation signal is ...
- 159
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3
answers
317
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How Can A Coded Firmware Control Hardware [closed]
I really want to know how could a virtual coded program really affect and imitate and animate a piece of hardware.
I Have Always Seen The Diagram Of Processors In the Book Showing ALU and CPU as The ...
- 648
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1
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255
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Why does the A8 have twice as many transistors than the Haswell processor yet runs on less power?
There's something I don't get - I am always under the impression that the more transistors we pack in, the more energy it consumes and the hotter it gets (assuming we haven't shrunk the die). However, ...
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