All Questions
Tagged with computer-architecture mips
46 questions
3
votes
1
answer
139
views
Why forward from MEM Stage in a sequence of add instructions that all contain the same register?
I was reading Computer Architecture and Organization 5th edition by Patterson and Hennessy. In Chapter 4, section 4.7 on Data Hazards, I read the following excerpt regarding forwarding from the MEM ...
0
votes
1
answer
91
views
Some questions on this reduced MIPS architecture
Consider the attached discussion of a reduced MIPS microprocessor from Weste and Harris's CMOS VLSI Design. My recollection of my computer organization course is relatively weak, so I'm hoping someone ...
- 1,219
1
vote
3
answers
940
views
Why use bytes instead of words for offsets in 'lw' and 'sw' instructions?
In assembly language, there are instructions like 'lw' (load word) and 'lb' (load byte). Both of these instructions involve adding an offset to a base address. It seems counterintuitive, however, that ...
0
votes
1
answer
325
views
Alu Control output not return 010 for Addi instruction
I'm currently working on a project for a MIPS Datapath Simulation website. The project aims to demonstrate how instructions work. I've implemented the Alu Control Unit using the combinational logic ...
0
votes
1
answer
149
views
Why do we need stalls even if branches can be determined?
I am learning about pipelining and was reading about control hazards from the book Computer Organization and Design: The Hardware/Software Interface (MIPS Edition). There is a paragraph in the book (...
- 103
0
votes
0
answers
1k
views
Help with Register File Implementation on Logisim
I'm currently working on an assignment that involves implementing a register file with 2 read ports and 1 write port on Logisim. I've made some progress but I'm struggling with a few questions and ...
1
vote
0
answers
130
views
How to solve pipeline hazards using stalls?
So, I have the following code, which should run on a five-stage pipeline (Fetch, Decode, Execute, Memory, Write). Now, we need only to consider read-after-write data dependencies and find the total ...
1
vote
2
answers
2k
views
How is sll implemented in MIPS?
I don't understand how MIPS would implement the sll (shift left logical) instruction using the hardware present in its ALU as shown in the diagrams below. Would ...
- 548
3
votes
2
answers
400
views
How can I fix delay between Instruction and Program Counter?
I am designing the MIPS processor, this includes Data Memory and Instruction memory for testing.
I had a problem with IM synthesis covered in this question (How to make a synthesizable Instruction ...
- 33
1
vote
0
answers
164
views
How much faster is the ideal machine without the memory structural hazard versus the machine with the hazard?
I am learning computer architecture and organization. I have the following doubt. Given below is a question along with its solution but I think that the solution is wrong. You can see the question ...
- 375
2
votes
1
answer
164
views
Doubt in pipelining forwarding in MIPS
I am fairly new to computer architecture and having a tough time solving problems based on pipelining. I was trying to solve a problem from this pdf I found on Google
I have a doubt in part ...
- 123
1
vote
1
answer
2k
views
How can I modify single-cycle MIPS processor to implement jal command?
Hello Stack exchange community
I was wondering which modification should I have to make in order to enable single-cycle MIPS processor to run a jal(jump and link) command?
My most pressing confusion ...
- 11
2
votes
1
answer
3k
views
MIPS clock cycle calculation formula
How many clock cycles will take execution of this segment on the simple pipeline without forwarding or bypassing when result of the branch instruction (new PC content) is available after WB stage. ...
- 21
0
votes
0
answers
34
views
Does stage Sy of instruction have to wait till all earlier instructions has executed their corresponding stage
I am trying to understand execution of instruction in RISC pipeline.
Can stage Sy of instruction I2 execute before stage Sy of I1? That is, in below example, will it be allowed to run I2's ID in C3 as ...
- 227
2
votes
1
answer
2k
views
The accurate time latency for 'lw' instruction in a single-cycle datapath
I want to calculate the cycle time of a single-cycle datapath. Then from the course, I know the time should be the execution time of the longest instruction, which is 'lw' in MIPS.
So I try to ...
- 21
1
vote
1
answer
3k
views
Understanding branch delay slot and branch prediction prefetch in instruction pipelining
Let me define:
Branch delay slot: Typically assemblers reorder instructions to move some instructions immediately after branch instruction, such that the moved instruction will always be executed, ...
- 227
1
vote
0
answers
53
views
Finding percentage memory utilization in pipelining architecture
I was solving problems from the exercise of the book "Computer Organization and Design" by Patterson. The problem reads like this:
Consider stage latencies:
...
- 227
3
votes
2
answers
5k
views
How many stall cycles resulted by incorrectly predicted branch in instruction pipelining
I have been solving following exercise problem from book Computer Organization by Patterson and Hennessy:
The importance of having a good branch predictor depends on how often conditional branches ...
- 227
1
vote
2
answers
3k
views
mips single-cycle branch verilog
I'm fairly new to Verilog, hardware design and computer architecture. Nevertheless, I've had a go at designing a simplified MIPS processor. It seems to mostly work fine but whenever I simulate it, it ...
- 13
1
vote
1
answer
221
views
Flushing in pipelined architectures
How is the flushing really implemented? I have an idea that on conditional branches, the prior instructions are flushed. But how are they actually flushed?
- 21
1
vote
2
answers
2k
views
how does program counter stores the instruction memory when program is loaded? [closed]
it is mentioned in the book computer organization and design by Patterson/Hennessy page 252 that:
The instruction memory need only provide read access because the
datapath does not write ...
- 113
3
votes
1
answer
636
views
In which CPUs will write-after-write and write-after-read dependencies cause a hazard?
I've been studying the MIPS single cycle architecture for pipeline. I noticed that read-after-write dependency causes a data hazard but two other write-after-write and write-after-read dependencies ...
- 131
-1
votes
1
answer
398
views
Finding percentage accuracy of instruction pipeline branch predictor
I need help in understanding the solution from solution manual. The question is from the exercise 4.24.4 and 4.24.5 of chapter 4 in the book Computer Organization and Design by Patterson and Hannessey ...
- 139
1
vote
1
answer
754
views
Understanding execution of sequence of pipeline instructions
I need help in understanding the solution from solution manual. The question is from the exercise 4.22.2 of chapter 4 in the book Computer Organization and Design by Patterson and Hannessey (4th ...
- 139
0
votes
1
answer
349
views
Understanding instruction branching
I need help in understanding the solution from solution manual. The question is from the exercise 4.22.1 of chapter 4 in the book Computer Organization and Design by Patterson and Hannessey (4th ...
- 139
0
votes
0
answers
746
views
Understanding instruction pipelining speedup calculation
I was solving the exercise problem 4.17.6 of chapter 4 in the book Computer Organization and Design by Patterson and Hannessey (4th edition):
Percentage occurrences of the instructions are as ...
- 139
1
vote
1
answer
1k
views
Understanding processor instruction pipeline problem solution
I need help in understanding the solution from solution manual.
The question is from the exercise 4.13.5 of chapter 4 in the book Computer Organization and Design by Patterson and Hannessey (4th ...
- 139
1
vote
1
answer
220
views
How instructions get executed in a pipelined architecture?
I saw this HW solution in CMU Comp Arch course website. I am reading ComputerArchitecture on my own. I just have a doubt.
Here is the HW question:
Given the following code (MIPS):
...
- 803
1
vote
1
answer
980
views
Implement BGEZAL instruction-MIPS-32 in verilog
I want to implement MIPS-32 Single cycle microarchitecture using Verilog. I have few doubts regarding the instruction BGEZAL.
It does GPR[31] = PC + 8.
The BGEZAL ...
- 803
2
votes
6
answers
3k
views
what exactly is single cycle instruction architectures?
I got the following text from lab work 2 of CMU's computer architecture course. I am actually trying to do this lab myself out of own interests and I am in no way a student of CMU.
The machine has ...
- 123
-1
votes
2
answers
939
views
Difference between MIPS and ARM datapaths [closed]
I have just learnt simplified five stage pipelined MIPS architecture in the class. I am reading other Instruction Set Architectures (ARM currently) and found some differences between ARM and MIPS. ...
- 113
4
votes
4
answers
3k
views
Are there any cases where single-cycle is better than pipelining?
I've been asked by my professor
When pipelining is better than single-cyle MIPS CPU's?
I actually answered "always", but I'm not sure that's the correct answer. Excluding an increase in design ...
- 167
19
votes
4
answers
8k
views
Why MIPS uses R0 as "zero" when you could just XOR two registers to produce 0?
I think that I am looking for an answer to a trivia question. I am trying to understand why the MIPS architecture uses an explicit "zero" value in a register when you can achieve the same ...
- 3,312
2
votes
0
answers
407
views
Analysis of Branch misprediction in MIPS 32 bit architecture
I am confused about what happens when we use a Bimodal branch predictor in the MIPS architecture shown in the image below.
I am considering the case where there is already a branch delay slot ...
- 121
-3
votes
1
answer
3k
views
Single Cycle Datapath MIPS - Adding swap instruction
Let's say I want to make a new MIPS instruction called: swap $rs $rt , which exchanges the contents of the registers $rs and $rt. Using an auxiliary variable aux, this new instruction is specified as ...
- 99
1
vote
1
answer
698
views
Why is register file latency, during write-back stage, not included in computing for minimum clock cycle time
I was looking at the solution for a homework posted here:
https://cseweb.ucsd.edu/classes/sp13/cse141-a/solutions/assignment4_solutions.pdf
and noticed that for 1.1, it didn't include the Register ...
- 11
0
votes
1
answer
1k
views
Register file write- back for pipelining vs multicycle implementaion for MIPS processors
We know that in multi-cycle implementation of a MIPS processor, the R type instruction takes 4 cycles.
However, in the pipeline implementation of MIPS, for R type instructions, 4th stage (MEM) is ...
- 93
15
votes
4
answers
24k
views
How many clock cycles does a RISC/CISC instruction take to execute?
According to Digital Design and Computer Architecture by Harris and Harris, there are several ways to implement a MIPS processor, including the following:
The single-cycle microarchitecture executes ...
user76520
2
votes
1
answer
2k
views
How the lw (load word) instruction works on the MIPS Unicycle (Implementation)
I'm reading the Computer Organization and Design book from David A. Patterson and John L. Hennessy. Specifically, I have a question about the implementation of a MIPS Unicycle.
So, in the book, they ...
- 475
0
votes
3
answers
4k
views
Finding Instruction Count
Computer A has an overall CPI of 1.3 and can be run at a clock rate of 600MHz.
Computer B has a CPI of 2.5 and can be run at a clock rate of 750 Mhz. We have a particular program we wish to run. When ...
- 139
1
vote
1
answer
717
views
implementing direct addressing mode for a load instruction on a mips archtitecture
Given a Mips machine with 26 bit addresses and 32 bits data-paths, where the load instruction is as follows
|OPT code|rs|rd|immediate|
|6 bits |5 bits|5 bits|16 bits|
The OPT code is the ...
- 113
1
vote
1
answer
17k
views
Use of $at register in MIPS?
Register r1 or $at, is it's sole use in pseudoinstructions? If so, is this the sole solution to enable pseudoinstructions within the architecture?
- 125
1
vote
2
answers
838
views
Classic RISC pipeline question
Consider the following instruction sequence:
Add R3, R4, R5 (R4+R5->R3)
Or R2, R4, R5 (R4 OR R5->R2)
Add R1, R2, R3 (R2+R3->R1)
Assuming no data ...
1
vote
1
answer
31k
views
How does the Store Word(SW) and Load Word(LW) instructions work, MIPS
The SW and LW instructions are defined as:
...
- 1,770
0
votes
1
answer
391
views
Writing a method using MIPS code
I am trying to understand how convert C code to MIPS code and I have having trouble understanding why the stack pointer( $sp ) needs to be manipulated before and after the procedural code.Isn't the ...
- 1,770
2
votes
2
answers
2k
views
MIPS Main Control Logic
In the Patterson & Hennessy book,
This is for these 4 instructions, if I need to implement instructions like andi, addi, ori, j, etc, do I add on to this table? Or do I do something else?
...
- 579