All Questions
5 questions
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Help with Register File Implementation on Logisim
I'm currently working on an assignment that involves implementing a register file with 2 read ports and 1 write port on Logisim. I've made some progress but I'm struggling with a few questions and ...
1
vote
2
answers
2k
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How is sll implemented in MIPS?
I don't understand how MIPS would implement the sll (shift left logical) instruction using the hardware present in its ALU as shown in the diagrams below. Would ...
- 548
3
votes
2
answers
400
views
How can I fix delay between Instruction and Program Counter?
I am designing the MIPS processor, this includes Data Memory and Instruction memory for testing.
I had a problem with IM synthesis covered in this question (How to make a synthesizable Instruction ...
- 33
2
votes
1
answer
164
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Doubt in pipelining forwarding in MIPS
I am fairly new to computer architecture and having a tough time solving problems based on pipelining. I was trying to solve a problem from this pdf I found on Google
I have a doubt in part ...
- 123
3
votes
1
answer
636
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In which CPUs will write-after-write and write-after-read dependencies cause a hazard?
I've been studying the MIPS single cycle architecture for pipeline. I noticed that read-after-write dependency causes a data hazard but two other write-after-write and write-after-read dependencies ...
- 131