All Questions
11 questions
2
votes
1
answer
3k
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MIPS clock cycle calculation formula
How many clock cycles will take execution of this segment on the simple pipeline without forwarding or bypassing when result of the branch instruction (new PC content) is available after WB stage. ...
- 21
0
votes
0
answers
34
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Does stage Sy of instruction have to wait till all earlier instructions has executed their corresponding stage
I am trying to understand execution of instruction in RISC pipeline.
Can stage Sy of instruction I2 execute before stage Sy of I1? That is, in below example, will it be allowed to run I2's ID in C3 as ...
- 227
2
votes
1
answer
2k
views
The accurate time latency for 'lw' instruction in a single-cycle datapath
I want to calculate the cycle time of a single-cycle datapath. Then from the course, I know the time should be the execution time of the longest instruction, which is 'lw' in MIPS.
So I try to ...
- 21
1
vote
1
answer
3k
views
Understanding branch delay slot and branch prediction prefetch in instruction pipelining
Let me define:
Branch delay slot: Typically assemblers reorder instructions to move some instructions immediately after branch instruction, such that the moved instruction will always be executed, ...
- 227
1
vote
0
answers
53
views
Finding percentage memory utilization in pipelining architecture
I was solving problems from the exercise of the book "Computer Organization and Design" by Patterson. The problem reads like this:
Consider stage latencies:
...
- 227
3
votes
2
answers
5k
views
How many stall cycles resulted by incorrectly predicted branch in instruction pipelining
I have been solving following exercise problem from book Computer Organization by Patterson and Hennessy:
The importance of having a good branch predictor depends on how often conditional branches ...
- 227
-1
votes
1
answer
398
views
Finding percentage accuracy of instruction pipeline branch predictor
I need help in understanding the solution from solution manual. The question is from the exercise 4.24.4 and 4.24.5 of chapter 4 in the book Computer Organization and Design by Patterson and Hannessey ...
- 139
1
vote
1
answer
754
views
Understanding execution of sequence of pipeline instructions
I need help in understanding the solution from solution manual. The question is from the exercise 4.22.2 of chapter 4 in the book Computer Organization and Design by Patterson and Hannessey (4th ...
- 139
0
votes
1
answer
349
views
Understanding instruction branching
I need help in understanding the solution from solution manual. The question is from the exercise 4.22.1 of chapter 4 in the book Computer Organization and Design by Patterson and Hannessey (4th ...
- 139
0
votes
0
answers
746
views
Understanding instruction pipelining speedup calculation
I was solving the exercise problem 4.17.6 of chapter 4 in the book Computer Organization and Design by Patterson and Hannessey (4th edition):
Percentage occurrences of the instructions are as ...
- 139
1
vote
1
answer
1k
views
Understanding processor instruction pipeline problem solution
I need help in understanding the solution from solution manual.
The question is from the exercise 4.13.5 of chapter 4 in the book Computer Organization and Design by Patterson and Hannessey (4th ...
- 139