All Questions
Tagged with computer-architecture risc-v
9 questions
0
votes
0
answers
60
views
RISC-V Exercise: why is `MemtoReg = 1`?
Given the instruction sd x12, 20(x13) (ISA RV64I), what are the inputs and outputs of the encircled MUX?
My answer: if x[n] is ...
- 227
3
votes
2
answers
149
views
What is a PCS accumulator?
I'm currently doing my bachelor's thesis in electronics. While reading an article, I stumbled upon the sentence "The FPU is based on a PCS accumulator...".
What does PCS stand for? I can't ...
- 133
2
votes
1
answer
168
views
What is a chip generator?
I've been trying to learn more about the RISC-V environment. I've encountered a chip generator called Rocket Chip.
What is a chip generator, and how does it differ from a core? I'm trying to ...
- 133
0
votes
0
answers
51
views
How different layers of cache connect in hardware?
I had a RISC-V CPU with L1 Instruction Cache and L1 Data Cache, and I want to connect these two L1 Caches to unified L2 Cache. I have the following questions:
Does the unified L2 Cache have dual port ...
0
votes
1
answer
85
views
Generating Control Signals via Case statement vs Boolean function
I'm building a RISC-V processor recently, and I've encountered a question when constructing the control unit. That is, what's the difference between generating control signals through:
Case statement,...
3
votes
0
answers
372
views
How to using JAL in RISCV in this example?
Write a "replace" function that replaces every character in the source string between the first occurrence of character "(" and the first following ")" with character &...
- 31
3
votes
2
answers
5k
views
What is a hardware thread in RISC-V?
RISC-V PMP limits the physical addresses accessible by software running on a hart (hardware thread).
Source: edX course on Introduction to RISC-V, Chapter 4. Developing RISC-V, The Privileged ...
- 2,331
1
vote
1
answer
588
views
Where is the RAM stored on a RISC-V CPU? [closed]
Does RISC-V have any opinion on whether the RAM is stored on the same chip as the CPU (like on ARM devices) or on a separate chip somewhere on the motherboard (like on an x86 desktop)? I assume that ...
- 125
0
votes
2
answers
225
views
What are common ways that modern processors handle data hazards with asynchronous registers
I'm trying to design a processor in VHDL. While the base instruction set is done, I'm having trouble building on top of it.
Specifically, I'm implementing control and status registers (CSRs), which ...
- 687