All Questions
Tagged with computer-architecture vhdl
12 questions
2
votes
2
answers
662
views
VHDL: port declaration design for a feedback signal
I am a Computer Engineering student currently learning computer architecture, and working on modeling a booth's algorithm in VHDL. My design hierarchy contains a datapath and a control unit. The ...
- 83
0
votes
2
answers
500
views
VHDL: on variable declarations to act as register
I am currently a CPE student taking up computer architecture, learning how to model major computer components using VHDL. Currently, I am working on a shift register as a sub component for a top-level ...
- 83
0
votes
1
answer
492
views
Why is carry-out changing for logical shifts in my 32-bit ALU?
My code for logical-right shift is as follows:
...
- 141
2
votes
0
answers
248
views
Ling adder vs classic CLA adder what's the difference?
I'm practicing in designing vhdl unit with some "complex" computer arithmetic algorithm.
I've just implemented the following CLA unit below.
I'm reading through this book, page section 6.3 page 97, I ...
- 618
1
vote
1
answer
456
views
Silly serial adder design with control unit
I have designed a serial adder, with a small control unit which is supposed to synchronize all the ff states. I'm specifically interested in the state machine that does such stuff (you can see a block ...
- 618
2
votes
1
answer
1k
views
Difference between reading data from fifo and the register
I am currently working on a hardware design as a part of my project in verilog.
I am fully aware that we usually use the registers to break the datapath which in turn helps us achieve timing closure. ...
- 23
2
votes
0
answers
275
views
Operator synthesis VHDL, numeric_std.vhd
if i include the library numeric_std.vhd
(the implementation is here https://standards.ieee.org/downloads/1076/1076.2-1996/numeric_std-body.vhdl) you can see that the operator *,+ (as instance are ...
- 618
0
votes
1
answer
796
views
How to reduce an ALU logic with the minimum logic possible? Its very challenging
Our professor wants us to reduce 8-function ALU (8 outputs) to a 4 out ALU that has the capability to implement all the 8 functions. We can use any gates(even AOI's), muxes, and can create our control ...
- 201
2
votes
0
answers
330
views
What CPUs use a skewed associative cache?
What CPUs use a skewed associative cache?
I see several people imply that, with roughly the same hardware, a skewed-associative cache often has better performance than a traditional set-associative ...
- 17.8k
0
votes
2
answers
3k
views
CPU Cache implementation in VHDL
I have been assigned a project of designing a cache memory with some advanced features (using efficient cache algorithms) and implementing it in VHDL.
I know the required theory for carrying out this ...
- 101
5
votes
3
answers
5k
views
How can the number of clock cycles required to complete an instruction in a pipelined processor less than pipeline latency?
I am not new to computer architecture but I have only academic experience with micro-architecture implementation.
I have heard and read this many times but never really bothered to understand the ...
- 907
2
votes
1
answer
2k
views
How to wire a system for Nios 2 in Qsys?
I've managed to reduce the number of errors but I still have some:
...
- 1,724