Questions tagged [computer-architecture]
Computer architecture refers to both the design of a computer's external interfaces (instruction sets) and a computer's internal implementation (microarchitecture). The goal of these design decisions is to optimize speed, power efficiency, size, or cost while satisfying constraints on the rest.
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How does pipelined CPU access both code and data memory in real life?
In the Digital Design and Computer Architecture RISC-V Edition page 442, a pipelined CPU is designed with separate instruction and data memories, as shown in the figure below.
However, this picture ...
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What Determines the Maximum Speed of a Data Interface? [closed]
Coming from the software side of things, every now and then I'll hear about some new USB, PCIe, or other standard and how it's faster than the last.
What is the determining factor behind how fast a ...
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RISC-V Exercise: why is `MemtoReg = 1`?
Given the instruction sd x12, 20(x13) (ISA RV64I), what are the inputs and outputs of the encircled MUX?
My answer: if x[n] is ...
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Are my assumptions on NMOS voltage at drain correct?
If voltage at gate is ground and voltage at source is ground, then voltage at drain is VDD
If voltage at gate is ground and voltage at source is VDD, then voltage at drain is floating
If voltage at ...
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How to understand t and t-1 in DFF mechanism?
I'm following the course From Nand to tetris. In chapter 3, the authors introduce the notion of Data Flip-flop (DFF), which computes the output(t) = input(t-1) where t is the time.
My question is that ...
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Can consumer NPU hardware be repurposed?
Limiting this to the current generation of consumer NPU hardware going into new PCs:
Can the NPU accelerator hardware being put in recent PCs practically be repurposed for non-AI tasks? And what ...
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Understading CPU pipeline stages
I'm working on implementing a CPU that needs a three-stage pipeline. The division of those stages is open for me to determine.
I am struggling to comprehend how the stages are counted. While some ...
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Single port ROM: how does the CPU read constant data?
I am looking at different CPU micro-architectures.
Frequently, it happens that the ROM is supposed to contain only instruction data. See below for an example:
In such design, how is the CPU supposed ...
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1-bit computing with true one-instruction set architecture
Even though MC14500B is considered as 1-bit computing where it accepts 1-bit data to perform operation, the instruction set itself consisted with 4-bit instruction which leads having 16 total ...
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Are iGPUs utilized in any way while using a discrete GPU? Could they? Should they?
Whenever I've seen die shots of CPUs that contain integrated GPUs, it seems that the GPU takes up a not-insignificant portion of the die.
(Source: AMD "Phoenix 2" die shot, purely an ...
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Applying analog computer with passive circuit only
TLDR
You can skip to question section.
Intro
I know the analog computer was actually invented long ago. I don't know how analog computer architecture was, but I guess it was using active components.
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nand2tetris ALU Question
So im working on the ALU for the nand2tetris course online (for fun) and it's "design" is supposed to be as such:
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Why did my CR 2032 CMOS battery with reversed polarity discharge when connected?
I own an Intel NUC which we use as a HTPC. It stays turned off most of the time minus game day/movie nights. It by default uses a JST connector standard polarity CR 2032 3V battery. I ordered a ...
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does data and instruction memory we see in the data path corresponds to the L1 Instruction and Data cache inside of the core?
In CPU data path there are blocks called data memory and instruction memory ? Are these blocks L1 Instruction and L1 data caches ?
For instance check figure 4.10 in this link.
We know that generally ...
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Memory clock and Bus clock
The bus clock rate is how many times per second data is transferred from one component to another. If we consider DRAM DDR4-3200, the clock frequency of the RAM bus today can be 1600 MHz at the same ...
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How to implement the Instruction Set in Logisim
I have an assignment that requires me to build an 7-bit CPU. I’m done with implementing some of the requirements that includes 4 8-bit registers (the requirements say I have to store the parity bit), ...
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What does Vdd and Voh mean?
I truly apologize if this question title is vague I don’t really know entirely what to ask. I’m a programmer interested in computer architecture and I’ve been reading a book about digital design. ...
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Why forward from MEM Stage in a sequence of add instructions that all contain the same register?
I was reading Computer Architecture and Organization 5th edition by Patterson and Hennessy. In Chapter 4, section 4.7 on Data Hazards, I read the following excerpt regarding forwarding from the MEM ...
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What can be done with all of the extra address lines in a ROM? Why were they designed to have so few outputs compared to possible inputs?
I am a student in an introductory Digital Logic and Computer Systems course. We have been learning about ROMS, but often we just use them to basically just map truth tables onto them. We have been ...
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Were vacuum tube computers made of logic gates?
A lot of introductory resources on modern CPU present them as being built from NAND gates (see here and there for instance).
Actually, it is possible to build a modern CPU using almost exclusively ...
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What do we mean when we say something is done "in hardware" versus "in software"?
Describing a specific operation as being done "in hardware" versus "in software" in a given computer system is common. For example, simple computer systems (I am assuming) might ...
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How is the structure of a matrix addressable memory block realized?
Currently studying memory addressing in IC design, my professor mentioned matrix addressing and how it reduces the number of input lines to the memory block. But he didn't make himself clear on the ...
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Why does saving addresses on a stack give us the only way out for both nesting and "recursing" subroutines? [closed]
My text (Computer Organization and Embedded Systems, 6e, by Hamacher et al.) poses the following:
Consider the following possibilities for saving the return address of a subroutine:
(a) In a ...
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How do P-type transistors conduct current?
Going through a Introduction to Computing Systems by Yale N. Patt and Sanjay J. Patel and currently reading a chapter on MOS transistors. From what I understand, N-type transistors "close" a ...
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Is assembly microarchitecture dependent?
Many microarchitectures can implement a given digital system architecture. For example, and as Weste and Harris explain in their CMOS VLSI Design,
Digital VLSI design is often partitioned into five ...
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Some questions on this reduced MIPS architecture
Consider the attached discussion of a reduced MIPS microprocessor from Weste and Harris's CMOS VLSI Design. My recollection of my computer organization course is relatively weak, so I'm hoping someone ...
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On understanding tradeoffs associated with pipeline depth
In Weste and Harris's CMOS VLSI Design, they write the following in the context of a discussion about how different levels of design abstraction interact but, to be clear, my question is about the ...
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Why do AVR microprocessors have two ways (paths) to access I/O ports?
I've an ATmega328P.
Register Summary Page 275 ATmega328P datasheet.
The first address is the I/O address, and the second is the data memory address.
I'm going to set all (D ports) Data Direction ...
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For DDR4 and DDR5, is tCCD_l timing to be obeyed for accesses in a single row as well?
So I have been trying to learn about DDR4 and DDR5 memories, and it seems that the Column-to-Column delay values (in clock cycles) are different depending on whether consecutive accesses are inter-...
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Wrong value in memory because of a branch misprediction
Lets say we have instructions like:
bne r1 $0 loop
sw r2 0(r1)
Let's say we go ahead with the taken path, i.e., execute the sw instruction after bne assuming the ...
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Why use bytes instead of words for offsets in 'lw' and 'sw' instructions?
In assembly language, there are instructions like 'lw' (load word) and 'lb' (load byte). Both of these instructions involve adding an offset to a base address. It seems counterintuitive, however, that ...
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Does the chipset act as a "gateway" to the system bus?
I am trying to understand how exactly the main memory and peripheral devices like NIC, video card, hard disk, USB, etc. are physically or electrically connected to the system bus. Pasting here the ...
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Why is memory addressed using 2 address decoders only and not more? [duplicate]
I am currently taking a university course about computer architecture in which we learned basic DRAM architecture and addressing. As far as I know, each latch is selected using decoder outputs to ...
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Is it possible to make the "arithmetic" part of the ALU to be mircoprogrammed?
We know that the Arithmetic and Logic Unit in CPU is a hardware, it is a combinational circuit. Binary addition, for example, is very fast because it doesn't have to be microprogrammed; there is ...
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Understanding decode stage of x86 fetch-decode-execute pipeline and its (lack of) register requirements
FDE pipeline has register requirements for the F & D stages: For fetching an instruction from memory, the instruction pointer register points to the memory location of the next instruction to be ...
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How are `call` and `return` usually implemented in microarchitecture? [closed]
This is a follow-on from this question:
Are `call` and `return` usually instructions in a modern ISA?
I'd like to implement call and ...
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Are `call` and `return` usually instructions in a modern ISA?
I've been working through the problems in a game based around building a Turing Complete machine.
One of the final problems asks you to implement the call and ...
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Alu Control output not return 010 for Addi instruction
I'm currently working on a project for a MIPS Datapath Simulation website. The project aims to demonstrate how instructions work. I've implemented the Alu Control Unit using the combinational logic ...
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Electrical/physical difference between Primary Memory and Secondary Memory connection to CPU
It is said that the difference between primary memory and secondary memory is that primary memory is "directly accessible by CPU", while secondary memory is "not directly accessible by ...
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Retrieval of information from a sequential circuit
SR-NOR Latch circuit is a sequential circuit in which there exist two, different modes Reset and Set. Electricity flows along ...
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How does CPU's Machine Check Architecture work?
Modern CPUs can alert the OS when itself is malfunctioning, i.e. logically incorrect, and apparently, this is supported by a hardware diagnostic feature called Machine Check Architecture. I can ...
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Mark Horowitz Computing's energy problem - methodology
I have a question about the Mark Horowitz paper: Computing’s Energy Problem
(and what we can do about it). In the paper, the author breaks down the sources of energy loss in modern computing systems.
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Computer Board and Raspberry
I have a question for which I haven't found any source to explain it to me. For personal projects raspberry pi is usually used as computer. How it is substituted in commercial products? Do they make ...
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Is floating point IEEE754 binary digit represented using special unit/circuit for arithmetic operation?
We know that two un/signed integers arithmetic operation using special circuit called full-adder to execute arithmetic operation in Arithmetic Logic Unit (ALU).
The full-adder I mean is classical ...
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Why do we need stalls even if branches can be determined?
I am learning about pipelining and was reading about control hazards from the book Computer Organization and Design: The Hardware/Software Interface (MIPS Edition). There is a paragraph in the book (...
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Can components like EPROM or NE 555 timer be built from scratch?
I was watching some videos on building an 8-bit computer and plan to do so myself, however, I wondered if it was possible to make something like an EPROM or 555 timers from scratch using basic ...
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Can we service another memory request from L1 cache when an L1 miss is being serviced from L2?
Consider the case where L1 cache miss occurred and is being serviced by L2 cache which could take many cycles (may go to main memory in case of L2 cache miss). In the meantime L1 cache is idle, in ...
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What is a PCS accumulator?
I'm currently doing my bachelor's thesis in electronics. While reading an article, I stumbled upon the sentence "The FPU is based on a PCS accumulator...".
What does PCS stand for? I can't ...
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Which devices supply input signals for transistors in a computer?
In a computer, I understand that the transistors are used to make up logic gates. For each transistor, there is a current (voltage) that controls the base terminal with the logic "low/high ...
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What is a chip generator?
I've been trying to learn more about the RISC-V environment. I've encountered a chip generator called Rocket Chip.
What is a chip generator, and how does it differ from a core? I'm trying to ...
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