Questions tagged [computer-architecture]
Computer architecture refers to both the design of a computer's external interfaces (instruction sets) and a computer's internal implementation (microarchitecture). The goal of these design decisions is to optimize speed, power efficiency, size, or cost while satisfying constraints on the rest.
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Which kinds of embedded platforms can be considered well-suited for acquiring a general taste of interrupts? [closed]
I'm an application programmer without much knowledge in low-level programming. I've set up a basic toolchain for assembly programming with the ATMega328P on an Arduino Uno R3 board. One of my aims is ...
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Help with Register File Implementation on Logisim
I'm currently working on an assignment that involves implementing a register file with 2 read ports and 1 write port on Logisim. I've made some progress but I'm struggling with a few questions and ...
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How to estimate how bad the wire delay can be when I am designing a chip?
I am currently working on a program involves designing a Neural Network accelerator architecture. I don't have a very deep background in digital circuit, but I know long wires may incur heavy delay ...
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Need help understanding speedup in parallel computing [closed]
I am currently studying computer architecture and I am having some trouble understanding the concept of speedup in parallel computing. I came across the following statement: "Before the multicore ...
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Designing instruction emulating swap on a MIPS ISA with only 2 registers
In a typical MIPS ISA, you have only 2 working registers. But you have a large number of ALU units.
How to design an instruction to emulate swap?
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What provides the clock signal in CSI2 interface?
What provides the clock signal for the CSI2 interface used for many cameras? Does the camera provide it or is it the processor the camera is interfacing to?
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Are there any fields in EE that overlap with Quantum informatics/computing nowadays? [closed]
As I understand it, research in quantum information and computing has traditionally been confined to physics and applied physics/math departments. It seems to me that many of the practical challenges ...
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A simple question on pipelined MIPS
For branches/jumps the PC is always muxed from the MEM stage. Why don't we mux it from the EX stage itself instead?
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Computer architecture: Count of RAM, ROM and I/O interface addressing
I am trying to work through this question and I appreciate any help or hint. Thank you
Problem:
A computer system uses RAM chips of size 512x8 and ROM chips of size 256x8. The computer system needs 4k ...
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How do you fit so many instructions on a 8-bit processor?
I will preface this that it is highly likely that I have misunderstood how Harvard architecture works, but I cannot understand how an 8-bit instruction set, say the ATmega128 for example, can contain ...
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How different layers of cache connect in hardware?
I had a RISC-V CPU with L1 Instruction Cache and L1 Data Cache, and I want to connect these two L1 Caches to unified L2 Cache. I have the following questions:
Does the unified L2 Cache have dual port ...
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Generating Control Signals via Case statement vs Boolean function
I'm building a RISC-V processor recently, and I've encountered a question when constructing the control unit. That is, what's the difference between generating control signals through:
Case statement,...
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How to solve pipeline hazards using stalls?
So, I have the following code, which should run on a five-stage pipeline (Fetch, Decode, Execute, Memory, Write). Now, we need only to consider read-after-write data dependencies and find the total ...
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How can memories be implemented efficiently with memory blocks of different sizes?
I am unsure if I am framing the question correctly, but here's what I wanted to ask.
Let's say we want to implement a 64 kB memory. We would require a 16-bit address if we have byte-addressable memory....
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SRT division: correcting BSD quotient
I have been reading a lot about the SRT division algorithm lately and I understand that the main idea is that it allows us to skip over addition/subtraction, unlike non-restoring division where we ...
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Mitigating structural hazards in register files in processor pipelines
I am reading about structural hazards in pipelined architecture in processors. In classic RISC pipeline one such hazard is when we write and read simultaneously to same register, which may cause ...
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How to using JAL in RISCV in this example?
Write a "replace" function that replaces every character in the source string between the first occurrence of character "(" and the first following ")" with character &...
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Is there any difference between a CPU core and a CPU itself?
I was reading this article that explains the difference between a thread and a core and it says the following:
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How are BAR registers handled between end points in PCI Express?
I have a question related to the PCI Express protocol.
I managed to understand most of the features of the PCI Express protocol but could not entirely understand the enumeration process.
I know the ...
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Differences in capacitive loads
I'm in school and I am trying to figure out a question for homework. It reads as stated:
Version
Voltage
Clock Rate
i.
Version 1
1.75V
1.5 GHz
Version 2
1.2V
2 GHz
ii.
Version 1
1.1V
3 GHz
...
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How to do signed 16-bit arithmetic on an 8-bit processor?
For example, to add two 16-bit numbers on my 8 bit machine, I add the low bytes together, then the high bytes together, and then add the carry flag to the high byte of the output.
This strategy falls ...
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Program counter updating in a single-cycle ARM processor
This picture is from the book Digital Design and Computer Architecture: ARM Edition. It implements the LDR instruction.
I have one question:
R15 is supposed to be PC+8. In the picture, is R15 ...
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Why do we need nonlinear electronics for computing?
When I read about photonics, I always see that they can be used for linear transformations (just matrix multiplications), and that this is a limitation that makes them unsuitable for building a ...
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Implementing functional design of a computer system into physical hardware [duplicate]
I have recently started studying computer organisation and found that in most of the books the design of computer system is not discussed beyond functional design abstraction level (as shown in the ...
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Functional design implementation of computer system into actual physical hardware
I have recently started studying computer organisation and found that in most of the books the design of computer system is not discussed beyond functional design abstraction level (as shown in the ...
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How is sll implemented in MIPS?
I don't understand how MIPS would implement the sll (shift left logical) instruction using the hardware present in its ALU as shown in the diagrams below. Would ...
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Why do we see one, unified memory address space in ARM Cortex-M core based MCUs even though they have Harvard architecture?
Most of the ARM Cortex-M core based MCUs have Harvard architecture (except for Cortex-M0 and M0+.)
The thing I do not understand is that why we see only one memory address space. For example, in tge ...
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What drives an input from 0 to 1 inside of a digital circuit?
Inside of a digital circuit, like a computer, what is acting as the switch that drives the inputs or internal values from 0 to 1, and how does this work? Like in instructions for a computer, how are ...
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Do PCI Express devices' interrupts always go through a PIC or an APIC?
My Question is PCI/PCIe interrupt path to CPU is through a PIC or an APIC?
https://people.freebsd.org/~jhb/papers/bsdcan/2007/...
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Processor Design: Just how complex is a real CPU datapath?
We're doing a course on Computer Architecture, and the course project involves creating an ARM-based processor.
We're supposed to create the processor in stages, and add significant features in each ...
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How do computer memories interact with each other (registers, cache, RAM, ROM)?
After Googling around for some time, I have managed to get a good understanding what makes these components different, but I've yet to find any clear computer architecture-focused article/thread on ...
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Understanding Forwarding unit
I am new to this subject and am having trouble understanding this topic.
Suppose I have the following circuit to control the forwarding of a MIPS pipeline processor:
So the forwarding control will be ...
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What do the diagonal lines in these circuits mean? [duplicate]
What exactly do these diagonal lines represent in these circuits? (I have them circled in red.)
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Is it usual design that the addition operation in the arithmetic-logic unit is performed by default as other instructions are executed?
The book But How Do It Know? presents an 8-bit computer architecture in which arithmetic-logic instructions (that is, instructions which are executed by the ALU) have 1 as the most significant bit, ...
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How do processor transistor counts keep increasing, without geometric scaling?
Reading into the history of the semiconductor industry and Moore's Law, and looking at the ITRS/IRDS documents, I understand that scaling down and modern node names (7nm, 5nm etc) are now "...
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Confusion about IJVM
I was reading the chapter 4 of the book 'Computer Architecture' by Tanenbaum (since my copy is not in English maybe the title of the English version is not exactly that one), however it is the chapter ...
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Does the memory bus span multiple layers on die?
My question is if you take any model desktop CPU such as the ones manufactured by Intel would the design of the memory bus span multiple layers of a single die or would it be contained on a single ...
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Are coarse-grained reconfigurable architectures a subset of dataflow architecture?
By definition, dataflow architectures consist of large modules in the dataflow path, such as adders and multipliers for integer, floating-point, or fixed-point computation.
Hence, are coarse-grained ...
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What is the cost of increasing the number of register names?
Increasing the number of registers in a CPU, has the upside that more values can be kept in registers instead of having to spill to stack. It has some downsides, one of which is that more instruction ...
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Computers: How signals in the bus can travel in either direction [closed]
I'm reading J. Clark Scott's book But How Do It Know.
When he is describing registers and the bus he illustrates this at one point as five registers sequentially parallel-connected to a bus.
As you ...
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How does CDB mastering work in Tomasulo's algorithm?
I understand that implementations of Tomasulo's algorithm feature a common data bus (CDB) that each functional unit writes its output to. Each reservation station can listen on the CDB for its ...
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How does CPU control implement pipeline stall [closed]
The original question was deemed lack of focus. This post is specifically about cpu pipeline stall.
How does synchronous microarchitecture implement pipeline stall when a cache miss occurs during ...
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How does Asynchronous DRAM perform self-timing
The original question was deemed lack of focus. This post is specifically about dram chip.
When DRAM controller talks to an asynchronous DRAM, how does DRAM itself know when a write is completed and ...
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Are processor instruction sets royalty free? (e.g. ARM v9, x86)
I asked a general question on Law SE with one example (ARM) and for that example, I was directed to What exactly does ARM sell to vendors?.
I've read that QA that ARM sells actual core designs.
I've ...
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Transistors collector input output of other transistor?
I'm new to computer science and trying to learn the basics. Have learnt how to create logical gates using simple components like relays, thanks to nandgame.com. This was easy, boolean functions, have ...
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Can a pin to DDR4 be as thin as household tinfoil? (0.016 mm)
Edit: I think using the term "bus" might be wrong here. A "bus" needs to be large enough to facilitate an entire DDR4 stick's bandwidth to the Northbridge. The connection to each ...
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Which bus protocol(s) does a motherboard use to connect to RAM?
I'm trying to learn about the protocols busses use in computer engineering and so far I've learned about the CAN bus protocol, where you can even watch traffic on the busses with wireshark, but this ...
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Question about computer engineering circuits (noob question) [closed]
I'm currently self learning computer engineering stuff right now and I was wondering how RAM would work in terms of input and output and I stumbled upon this image
I think it's somewhat wrong from ...
