Questions tagged [computer-architecture]
Computer architecture refers to both the design of a computer's external interfaces (instruction sets) and a computer's internal implementation (microarchitecture). The goal of these design decisions is to optimize speed, power efficiency, size, or cost while satisfying constraints on the rest.
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Were vacuum tube computers made of logic gates?
A lot of introductory resources on modern CPU present them as being built from NAND gates (see here and there for instance).
Actually, it is possible to build a modern CPU using almost exclusively ...
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How to implement an 8-bit CPU?
I'm trying to create a CPU, using 8-bit instructions, and there will be 9 or 10 of them.
I have an add, subtract, multiply, load, store, branch if zero, branch if not zero, print (to display), input ...
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What Determines the Maximum Speed of a Data Interface? [closed]
Coming from the software side of things, every now and then I'll hear about some new USB, PCIe, or other standard and how it's faster than the last.
What is the determining factor behind how fast a ...
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How to best understand cache associativity?
AFAIK this definition is the most clear and physical:
Associativity number = Number of comparators.
Is it correct? Could you make a more precise / better definition?
The wikipedia illustration is ...
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Approaches to storing and addressing microcode for homebrew CPU
I've been teaching myself about CPU architecture for a while now and have successfully designed a couple myself. They were always based around microcode to drive the CPU's control lines.
The microcode ...
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How can the number of clock cycles required to complete an instruction in a pipelined processor less than pipeline latency?
I am not new to computer architecture but I have only academic experience with micro-architecture implementation.
I have heard and read this many times but never really bothered to understand the ...
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How does the BSRR register work?
On the GPIOs of some ARM-based microcontrollers, you are given a register BSRR which you can write to to perform atomic changes in a ports output register.
For ...
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"Halt and Catch Fire" BIOS cloning scene unrealistic?
The first episode of the TV series "Halt and Catch Fire" (inspired by the early days of Compaq) has two characters starting to clone the IBM PC BIOS in 1983 by creating a circuit that would display ...
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How Is Context Switching Done In Hardware?
I have a question about how process state would be saved during a context switch.
Given a relatively simple design for a CPU using von Neumann style architecture, how is the process image saved ...
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Thoughts & questions on custom CPU architecture
I'm designing a CPU architecture. I've come up with a preliminary design:
I'd like general thoughts on what I can improve in the design and also I have some specific questions:
Is it overkill to ...
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Are there any cases where single-cycle is better than pipelining?
I've been asked by my professor
When pipelining is better than single-cyle MIPS CPU's?
I actually answered "always", but I'm not sure that's the correct answer. Excluding an increase in design ...
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How to do signed 16-bit arithmetic on an 8-bit processor?
For example, to add two 16-bit numbers on my 8 bit machine, I add the low bytes together, then the high bytes together, and then add the carry flag to the high byte of the output.
This strategy falls ...
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Can you make a CPU out of logic gates
If i solder together enough binary adders, binary subtractors is it possible for it to work like a modern (very very slow) CPU (Such as one found in a graphics calculator).
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Chips vs wafers vs transistors
Sorry to ask such a trivial question but I am a non-engineering student currently writing an essay on Moore's law and I can't seem to find how the items in my title relate. An in-depth description of ...
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2-bit branch prediction accuracy
I am trying to solve this problem, the answer should be 15/20 = 75%.
However, I am not sure how this was calculated and want to understand the underlying concept.
A program core consists of five ...
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Memory (RAM) of computers after shut down
After computer shuts down, is it possible to retrieve data in RAM? I heard that police was able to do that... so I felt that was somehow weird..
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How does a ps2 mouse send data to a computer? [closed]
I want to read data from a mouse with the help of Arduino.
I want to calculate relative motion between two objects.
My questions are
1) Is it possible?
2) How is mouse interfaced with Arduino?
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Microprocessor architecture bits vs bus sizes
I am ready following on this website:
"Another big difference between 32-bit processors and 64-bit processors is the maximum amount of memory (RAM) that is supported. 32-bit computers support a ...
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Homebrew Redundant PC Power Supplies
I'd like to have redundant power supplies to power an array of four hard drives. Each drive uses 5V at .6A (3W) and 12V at .45A (5.4W), for a total of less than 10W each. The four drives will have ...
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Booth multiplication algorithm, why it works?
Just learned about Booth's multiplication algorithm, and from what I understand if the multiplier least significant bit (MLB) is equal to the previous significant bit in that multiplier (MPLB) then we ...
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Why do we need the MOESI/MESIF protocols?
As I understand, those two protocols add an extra state to identify which cache should respond to a miss request from another cache for a particular cache-line.
But, in the MESI protocol, only one ...
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Is it possible to remove the write back stage in 5-stage pipeline?
In this graph, can we simply remove the write back stage since the mux is pushed back into the memory access stage and there is no logic in the write back stage. Is it because of the register file ...
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What multi/many-core (micro)processors/controllers should I use for "embarrassingly parallel" computations? [closed]
This is my first question ever on this site, so I hope I don't mess this up. :D
I'll try to be as specific as possible.
What I need:
Something that I can program in C (or a C-like language).
I need ...
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How does CPU's Machine Check Architecture work?
Modern CPUs can alert the OS when itself is malfunctioning, i.e. logically incorrect, and apparently, this is supported by a hardware diagnostic feature called Machine Check Architecture. I can ...
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When are MIPS control signals generated?
Are the control signals for a given instruction generated within a single cycle
for the pipelined, the multicycle as well as the single-cycle implementations of the MIPS32 datapath?
I think they ...
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Understading CPU pipeline stages
I'm working on implementing a CPU that needs a three-stage pipeline. The division of those stages is open for me to determine.
I am struggling to comprehend how the stages are counted. While some ...
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Are processor instruction sets royalty free? (e.g. ARM v9, x86)
I asked a general question on Law SE with one example (ARM) and for that example, I was directed to What exactly does ARM sell to vendors?.
I've read that QA that ARM sells actual core designs.
I've ...
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Processor - L1 Data cache interface
Sorry if the following looks like a very specialized (or programming) question, but I'm hoping there are people on this forum who have done VHDL/Verilog modeling, and might be able to answer:
I'm ...
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Why can't an Asynchronous CPU use a simple "completion bit" to signal completion?
I've been reading about how asynchronous CPUs work, but they always seem to involve some complicated way of communication. Wikipedia talks about a two-way and four-way handshake. I found a pdf from ...
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Can anyone tell me what other computers used this floating-point format?
I have discovered that the DEC PDP-10 used a floating-point format that differed from IEEE-754 in an interesting way.
IEEE-754 is like sign-magnitude representation. The only difference between a ...
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What is a hardware thread in RISC-V?
RISC-V PMP limits the physical addresses accessible by software running on a hart (hardware thread).
Source: edX course on Introduction to RISC-V, Chapter 4. Developing RISC-V, The Privileged ...
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Is the registry file made from SRAM?
I study computer engineering and I read Hennessy's book about Computer Organization where it's described how the microprocessor does pipelining and that the microproceossor has on-chip cache, as much ...
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How do processor transistor counts keep increasing, without geometric scaling?
Reading into the history of the semiconductor industry and Moore's Law, and looking at the ITRS/IRDS documents, I understand that scaling down and modern node names (7nm, 5nm etc) are now "...
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What's the difference between delayed branch and branch prediction?
I'm studying how delayed branch works and I'm trying to distinguish delayed branch from branch prediction. What is the difference? Is delayed branch a means to facilitate a control hazard?
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Is there any difference between a CPU core and a CPU itself?
I was reading this article that explains the difference between a thread and a core and it says the following:
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How are irrational numbers best represented and processed by computers?
My question is closely related to this one: How do computers understand decimal numbers?
However, that question deals with rational numbers only. I was wondering if irrational numbers can be ...
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Does Registers and RAM are same kind of memory?
Recently, I found out a YT channel of a man who build a 8-bit computer and explain how.
In his video on the registers, he uses a D flip-flop, and in his other video on the ram, I understood that he ...
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How can I fix delay between Instruction and Program Counter?
I am designing the MIPS processor, this includes Data Memory and Instruction memory for testing.
I had a problem with IM synthesis covered in this question (How to make a synthesizable Instruction ...
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Using boolean algebra, simplify $$y = \bar{s} \cdot \bar{u} + s \cdot \bar{u}+s \cdot u$$
I have the following function, that I want to minimise using boolean algebra:
$$y = \bar{s} \cdot \bar{u} + s \cdot \bar{u}+s \cdot u$$
Here's my attempt:
$$\bar{s} \cdot \bar{u} + s \cdot \bar{u}+s \...
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Soft errors from SEUs/SETs in early 8-bit microprocessors?
Why is it that soft errors due to single-event upsets/transients never seemed to be a problem in early 8-bit microprocessors, like the MOS 6502 or the Zilog Z80? The microprocessors themselves were ...
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early accumulator based machines
Wikipedia says that many of the early machines were accumulator-based machines.
My guess is that in those machines the accumulator did not play the role of a speed-up register as do registers in today ...
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Are `call` and `return` usually instructions in a modern ISA?
I've been working through the problems in a game based around building a Turing Complete machine.
One of the final problems asks you to implement the call and ...
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What does it means that a MCU has support for OpenGL?
I am trying to understand the meaning of when someone says that PowerPC 7410 CPU has support for OpenGL based software. Does it mean that there are any specific instruction in its ISA architecture ...
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Logical Design Operation, A Simple Questions?
I'm so sorry if I ask my first question that so simple. My filed is Math and Computer science. I self-study Digital Design.
My challenge is how we can find the operation of the two following ...
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Is primary memory buffering the only way to access I/O devices and secondary storage?
I'm not sure if this is the right stack exchange site to ask this question so sorry if it's not. If anyone can cite a good book which explains computer architecture in general (not for a specific ...
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Is assembly microarchitecture dependent?
Many microarchitectures can implement a given digital system architecture. For example, and as Weste and Harris explain in their CMOS VLSI Design,
Digital VLSI design is often partitioned into five ...
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What is a PCS accumulator?
I'm currently doing my bachelor's thesis in electronics. While reading an article, I stumbled upon the sentence "The FPU is based on a PCS accumulator...".
What does PCS stand for? I can't ...
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What's the relationship between chips, wafers, and dies in a computer?
I have the following question:
If your demand is 50,000 RedDragon chips per month and 25,000
Phoenix chips per month, and your facility can fabricate 70 wafers a month, how
many wafers should you ...
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What is the role of ISA (Instruction Set Architecture) in the comp arch abstraction stack. [closed]
I have programming background, and I recently started taking computer architecture course. Most of the lectures I see use the some sort of the layering as described in the following diagram explaining ...
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what is microcoded architecture in computer architecture
I want to know what is microcoded microarchitecture of an instruction set architecture (ISA) and why is it used? What is the difference between microcoded architecture and single cycle ...
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