Questions tagged [computer-architecture]
Computer architecture refers to both the design of a computer's external interfaces (instruction sets) and a computer's internal implementation (microarchitecture). The goal of these design decisions is to optimize speed, power efficiency, size, or cost while satisfying constraints on the rest.
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Average data transfer rate
I am learning computer architecture and organization I am stuck in the following question.
Consider a hard disk with sector size 1024 bytes, 5000 tracks per surface,
64 sectors per track, and 8 ...
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Getting CPU clock signal out of computer (as to measure externally) [closed]
I've been searching on the internet some clock generator module capable of reaching up to 1GHz, when I just realized that the machine I'm using to search has one CPU with its own 2.5-3.0 GHz clock... ...
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Curious how does ALU addressing work like in Assembly code?
When writing assembly code, say R1 = R2 + R3, it is pretty easy to understand the addressing procedure because all registers are close to the ALU. But I find it hard to see how does the ALU go to the ...
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Can components like EPROM or NE 555 timer be built from scratch?
I was watching some videos on building an 8-bit computer and plan to do so myself, however, I wondered if it was possible to make something like an EPROM or 555 timers from scratch using basic ...
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VHDL: port declaration design for a feedback signal
I am a Computer Engineering student currently learning computer architecture, and working on modeling a booth's algorithm in VHDL. My design hierarchy contains a datapath and a control unit. The ...
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BJT transistor max switching frequency vs FET in high frequency computer architecture
Why arent BJTs used with RISC architectures to produce very high speed relatively sparse CPUs? My understanding is that BJTs don't have the forward bias gate capacitance requirements of FETs which is ...
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Implementation of a 8-to-256 decoder using BJTs
I'm designing an 8-to-256 decoder for an SRAM module I'm building for an home-made 8-bit BJT computer.
This is what I've got, which is the straightforward and trivial way:
However, the design ...
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What is the difference between full and partial address decoding?
Could someone please explain the difference between full address decoding and partial address decoding?
I am reading the chapter on digital logic in "Structured Computer Organization", 6th ed. by ...
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Where can I find common circuitry implementations of different computer system components?
Mostly out of interest, I'm trying to understand common circuit-level implementations of computer components. I understand that implementations may differ widely, but I'd like to see examples. It ...
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What happens if a process needs more pages than number of entries in page table?
I am having a little trouble understanding the concept of paging. Below is a simple example to illustrate my question.
Suppose main memory has 128 bytes, organized into 32 pages of size 4 bytes each, ...
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Making a toy DSP processor
When I was trying to learn computer architecture the thing that helped me the most was making a toy 4-bit processor (through gate level design of every single thing). Now I want to learn about DSP ...
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What provides the clock signal in CSI2 interface?
What provides the clock signal for the CSI2 interface used for many cameras? Does the camera provide it or is it the processor the camera is interfacing to?
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Is it usual design that the addition operation in the arithmetic-logic unit is performed by default as other instructions are executed?
The book But How Do It Know? presents an 8-bit computer architecture in which arithmetic-logic instructions (that is, instructions which are executed by the ALU) have 1 as the most significant bit, ...
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What does "Cycle \$\mu\$s" mean in this context?
I'm reading a paper about the architecture of the IBM system/360. There is a diagram which lays out the machine structure and implementation in the storage and control tables there is a metric which I ...
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Why is a Flush needed in the MSI cache coherency protocol when moving from Modified to Invalid?
While studying the MSI protocol as described in different sources such as:
https://en.wikipedia.org/w/index.php?title=MSI_protocol&oldid=941977299
http://courses.csail.mit.edu/6.888/spring13/...
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How to deal with PS/2 keyboard input and CPU interrupts
First of all, I'm not sure if this is the right place to ask this question or not. It was either here or the Computer Science stack exchange site, but I thought perhaps it would be better posted here ...
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misunderstanding of a Computer Architecture
I have the following architecture , and the timing diagram below . my question is , it's seem that no 'relation' or dependency between control logic and Extender , but at timing diagram , the time of ...
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clarification about amdahl's law
A system is designed as a cascade of of 4 subsystems, each contributing the same amount of time to the average service time of the system. If we wish to increase the speed of the system by a factor ...
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address field and words of memory
"Consider as an example a typical computer of that era which might have had a 16 bit address field in its instructions and 4096 words of memory.A program on this computer could address 65536 words of ...
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Can consumer NPU hardware be repurposed?
Limiting this to the current generation of consumer NPU hardware going into new PCs:
Can the NPU accelerator hardware being put in recent PCs practically be repurposed for non-AI tasks? And what ...
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What is a chip generator?
I've been trying to learn more about the RISC-V environment. I've encountered a chip generator called Rocket Chip.
What is a chip generator, and how does it differ from a core? I'm trying to ...
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Size of a memory cache
Assuming we have a virtual address issued by a model CPU that contains a total of 32 bits and 20 bits of this address are reserved for the tag + the cache comprises a total of 1024 cache lines.
Should ...
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Doubt in pipelining forwarding in MIPS
I am fairly new to computer architecture and having a tough time solving problems based on pipelining. I was trying to solve a problem from this pdf I found on Google
I have a doubt in part ...
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How does cache coherency and DMA work together?
I am currently reading about caches and how they are used in Computer Science. The explanation of how the cache is always up to date with the actual memory is understandable as long writing and ...
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How the lw (load word) instruction works on the MIPS Unicycle (Implementation)
I'm reading the Computer Organization and Design book from David A. Patterson and John L. Hennessy. Specifically, I have a question about the implementation of a MIPS Unicycle.
So, in the book, they ...
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What could this PLA be doing?
The picture below shows a PLA, I have done part (a) and found out that;
$$
F_0 = A_0 \mathbin{\oplus} B_0 \\
F_1 = A_0B_0 + (\overline{A_0} + \overline{B_0})(A_1 \mathbin{\oplus} B_1) \\
F_2 = A_0B_0(...
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Three way set associative cache with LRU replacement
So I am going through a homework exercise, and I am not understanding the solution to the problem. We are given a sequence of memory references and we are to use a three-way set associative cache with ...
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What does "CL" stand for in this processor architecture block diagram?
I'm learning about pipelining but can't understand this abbreviation: "CL". You can see it in processors' schemes.
It is shown with with and without a line above it; what is the line for?
Diagram ...
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How to wire a system for Nios 2 in Qsys?
I've managed to reduce the number of errors but I still have some:
...
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Does anyone know the hardware of a Nike+ SportWatch GPS? [closed]
I have one of these devices and I would really love to figure out if it is possible to write and push my own firmware into the device. The software on the watch is pretty limited and I would like to ...
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Electrical Engineering vs Computer Engineering? [closed]
I am trying to decide whether to major in EE or CE. To my knowledge, computer engineering has the same core focus as electrical engineering but with an emphasis on digital logic and microprocessors. ...
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Calculating range of two's complement
This is a computer architecture question given in our college syllabus and i was finding difficulty in solving it.
Calculate the range of a 16-bit 2's complement number system for representing both ...
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Program counter updating in a single-cycle ARM processor
This picture is from the book Digital Design and Computer Architecture: ARM Edition. It implements the LDR instruction.
I have one question:
R15 is supposed to be PC+8. In the picture, is R15 ...
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Internal differences between CPUs of the same architecture
What is the difference between, for example an Intel i3-4005U (1.7 GHz) and an Intel i3-4025U (1.9 GHz)? These CPUs are from the same generation, have the same amount of cores, cache, iGPU, and ...
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The concept of DDR rank
I have an understanding of DDR rank which I think is incorrect. If someone could join the dots then there would be more clarity.
Here is what I know
A DDR rank is a 64bit interface consisting of x8 ...
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The accurate time latency for 'lw' instruction in a single-cycle datapath
I want to calculate the cycle time of a single-cycle datapath. Then from the course, I know the time should be the execution time of the longest instruction, which is 'lw' in MIPS.
So I try to ...
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68008 Main board Review [closed]
I'm building a retro computer around the 68008 CPU
The main board will be simple, The CPU, 1MB of RAM, and a 32kB ROM (Bios/boot rom)
here is the adress map
$000000 - $07FFFF : RAM0
$080000 - $...
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Why does reading 1 byte from hard disk has the same speed as operation reading 1000 bytes?
Two operations:
read 1 byte from disk
read 1000 bytes from disk
Why exactly will they have approximately the same speed?
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Difference between reading data from fifo and the register
I am currently working on a hardware design as a part of my project in verilog.
I am fully aware that we usually use the registers to break the datapath which in turn helps us achieve timing closure. ...
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Memory architecture and instruction storage - Naimi: AVR Microcontroller
LDI R16, 0x25 --> E 2 0 5 --> 1110 0010 0000 0101
Apparently, in AVR, the code and data are stored separately and each
area (code, data area) is accessed by a unique bus.
Now since the Program ...
user41067
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Are neuromorphic computers considered digital computers?
This might be a pretty simple question, but I am wondering if neuromorphic computers using non Von Neumann architectures such as the IBM TrueNorth chip are still considered digital computers.
I have ...
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Inherent exploitability and power state machines
I'm working on understanding power state machines in regard to mobile computing devices. Most of the information on this subject seems to stem from this article. It's not particularly important to the ...
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Memory Organization in Computer
How is memory stored in a computer? Is it 1 bit per address so in order to get the value of an integer (32 bits) it must go through 32 addresses, get all the bits of 0's and 1's? I am a bit confused ...
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How to calculate index and tag fields lengths for a cpu cache?
I study computer engeering notes for a cache memory and I try to understand what determines the length of the index and the tag fields. The first examples is for 64 bits and the second example is for ...
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Given a shift register- Create a circuit to check whether 4 first bits are equal to the last 4
I hope this is the place to ask such a question.
Given a shift register- within 8 clock pulses 8 bits will enter this register, I need to make a circuit with this register, and other 3 flip-flops ...
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MIPS Main Control Logic
In the Patterson & Hennessy book,
This is for these 4 instructions, if I need to implement instructions like andi, addi, ori, j, etc, do I add on to this table? Or do I do something else?
...
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Differences in capacitive loads
I'm in school and I am trying to figure out a question for homework. It reads as stated:
Version
Voltage
Clock Rate
i.
Version 1
1.75V
1.5 GHz
Version 2
1.2V
2 GHz
ii.
Version 1
1.1V
3 GHz
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MIPS clock cycle calculation formula
How many clock cycles will take execution of this segment on the simple pipeline without forwarding or bypassing when result of the branch instruction (new PC content) is available after WB stage. ...
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Digital Comparator from LSB to MSB using Lookahead
This is homework to be upfront, but I'm really stuck on it and just need some kind of direction. I've been assigned to create a 16-bit lookahead comparator going from LSB to MSB using no more than 4-...
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Ling adder vs classic CLA adder what's the difference?
I'm practicing in designing vhdl unit with some "complex" computer arithmetic algorithm.
I've just implemented the following CLA unit below.
I'm reading through this book, page section 6.3 page 97, I ...
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