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Questions tagged [computer-architecture]

Computer architecture refers to both the design of a computer's external interfaces (instruction sets) and a computer's internal implementation (microarchitecture). The goal of these design decisions is to optimize speed, power efficiency, size, or cost while satisfying constraints on the rest.

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Analysis of Branch misprediction in MIPS 32 bit architecture

I am confused about what happens when we use a Bimodal branch predictor in the MIPS architecture shown in the image below. I am considering the case where there is already a branch delay slot ...
pavikirthi's user avatar
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Operator synthesis VHDL, numeric_std.vhd

if i include the library numeric_std.vhd (the implementation is here https://standards.ieee.org/downloads/1076/1076.2-1996/numeric_std-body.vhdl) you can see that the operator *,+ (as instance are ...
user8469759's user avatar
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What CPUs use a skewed associative cache?

What CPUs use a skewed associative cache? I see several people imply that, with roughly the same hardware, a skewed-associative cache often has better performance than a traditional set-associative ...
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Can a processor do a for loop within 1 clock pulse?

I am in a digital circuits class. In this class we are using verilog to simulate (but not actually physically synthesize) different circuits. We have an assignment where we are supposed to simulate a ...
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clock signals in computers and machines [closed]

Why do computers have clock signals and clock rate, while ordinary machines do not have them? And why is clock so fundamental in CPU and mainboard?
Mark Oswarld's user avatar
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4 answers
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Can an FPGA/ASIC have an operating system?

I know FPGA/ASIC are for a specific task and they are not microprocessors and an OS is needed mainly if multiple processes (tasks) need to be run concurrently. Just wondering if an FPGA/ASIC can have ...
Franc's user avatar
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4 answers
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How can a powersupply have a large input volt range

I see that computer power supplies that can take a voltage input of anything between 90V and 260V at a frequency between 47Hz and 63Hz. Meanwhile it can output power at a very precise voltage. How ...
KaareZ's user avatar
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What does the 8086 CPU do with the data returned from an address in RAM?

I understand how a CPU works fairly well, but there is this one thing which I've never really gotten the hang of. Say we have an Intel 8086 CPU (16 bits wide registers) which is about to fetch its ...
Frævik's user avatar
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Why does Intel produce core i3, core i5 and core i7 processors; but not core i2, core i4 or core i6 processors? [closed]

Why does Intel produce core i3, core i5 and core i7 processors; but not core i2, core i4 or core i6 processors? What is the reason behind this?
Deepak Berwal's user avatar
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5 answers
314 views

Has a CPU with Highlevel language (C/C++) as machine code ever been designed?

I got a question popping directly from reading Tanenbaum's Structured Computer Organization. Stating from Chap. 1 Sec. 1.1 : A machine with C++ or COBOL as its machine language would be complex ...
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How does ROM work? [closed]

ROM is a major part of a computer, and even more so in gaming consoles. How exactly do they work, and how can you make them with logic gates/transistors? I'm currently working on many projects, ...
Trevor Mershon's user avatar
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Which devices supply input signals for transistors in a computer?

In a computer, I understand that the transistors are used to make up logic gates. For each transistor, there is a current (voltage) that controls the base terminal with the logic "low/high ...
InTheSearchForKnowledge's user avatar
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3 answers
279 views

Would a standardized graphics chip socket be sensible? [closed]

I am not an EE, and so I'm running this conjecture on breaking out the GPU from the CPU by folks who have better knowledge than me. Perhaps you can point out something I don't know about modern CPU ...
John Moser's user avatar
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2k views

Is it true that copying is the most CPU intensive operation?

A mech engineer said that copying puts more load on the microprocessor than "other" operations (e.g. moving data or creating the same amount of new data). Is this true? Can you elaborate? I understand ...
Niklas Rosencrantz's user avatar
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Cache write/read times?

I would like to devise certain rules of thumb to help solve certain computer design/architecture challenges. Hence, in memory, which operations typically take longer to execute: loads or stores?? I ...
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Understanding basic computer hardware diagram of address decoding circuit

Hi I'm a computer science student doing a computer hardware course and am having trouble understanding this circuit which is supposed to show how control signals at the memory can be generated using ...
user1058210's user avatar
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1 answer
293 views

Expression calculated at assembly time

I don't understand the explanation. Doesn't the assembler have to calculate 3 * 4 + 5 so it takes longer to execute? Also since 3 * 4 +5 has more characters why does it not take more storage? From ...
Ray's user avatar
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Can I calculate how much time it will take for an electrical signal to propagate through a TTL circuit?

Given a particular circuit of TTL, can I calculate how much time it will take for an electrical signal to propagate through some section, or all of, the circuit? If I wanted to know how long it ...
Christian Westbrook's user avatar
1 vote
1 answer
5k views

Were can I find a simple CPU Design tutorial / book? [closed]

I basically want to know how to make(In hardware and in a simulator) a simple CPU. A book that covers low level stuff like, like logic gates, and more high level stuff like a complete CPU. Ive tried ...
Bruno's user avatar
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2 answers
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Instruction Register? Whats it's purpose/how is it connected? (And what happens after)

So im learning the SAP 1 Computer Architecture. Most things I get pretty well, but from what I understand: (Lets pretend it's an 8bit and address is 4 bits and opcode is 4bit) http://www.instructables....
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8085 μp; Why does Read cycle take 3 T-states and not 2?

In the text I'm following, R.S.Gaonkar it's explained that, During T1, address in Program Counter(PC) is latched onto the Memory Address Register(MAR), During the falling edge of T2 \$\overline{MEMR}...
Aravindh Vasu's user avatar
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2 answers
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Can I use the 12V line of a computer PSU to power my circuits?

Or is there any issues I should be wary of? I need at least 7A on a 12V line, but I've found that a computer PSUs are significantly cheaper.
joaocandre's user avatar
1 vote
2 answers
226 views

D flip flop data extraction

How do you get the data out of a d flip flop? On wikipedia it says that if the clock is non-rising then it ouputs Q. Isn't the clock always non-rising if it's not changing the data? If it is, then ...
David's user avatar
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Electrical/physical difference between Primary Memory and Secondary Memory connection to CPU

It is said that the difference between primary memory and secondary memory is that primary memory is "directly accessible by CPU", while secondary memory is "not directly accessible by ...
Noob_Guy's user avatar
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1 answer
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Where is the RAM stored on a RISC-V CPU? [closed]

Does RISC-V have any opinion on whether the RAM is stored on the same chip as the CPU (like on ARM devices) or on a separate chip somewhere on the motherboard (like on an x86 desktop)? I assume that ...
Aaron Franke's user avatar
1 vote
3 answers
1k views

Why do displays have limited bit-depth?

As far as I am aware, HDMI 2.1 does support 12-bit 4K 60fps, Also it doesn't use TMDS, rather FRL. Sends upto 48Gbps GPUs can do calculation in fp32 and from some reference, I think that it can send ...
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1 vote
2 answers
146 views

Why can't absolute delays be used in ASIC?

Verilog allows the definition of absolute delays when modelling hardware but the ASIC synthesizer will strip these out. Why does it do this?
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1 answer
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Interfacing RAM to a DIY computer

I am a relatively newbie to electronics but hopefully this question is not very non sensical: I am following a guide to build a 8 bit computer. The guide requires a RAM which has a 4 address bit and ...
pokiman's user avatar
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2 answers
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Homebrew Computers - TTL/FPA computer that can run a POSIX OS? [closed]

The internet is filled with inspiring examples of homebrew computers, including ones made from relays and TTL gates. In the first year of Make Magazine - they describe a person who builds a simple ...
hawkeye's user avatar
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Is a digital bit represented by any two discrete signals?

I am trying to understand computers from the building blocks up. I know computers use transistors to amplify voltages, and this is used for arithmetic, such as a MOSFET. However, what really makes ...
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2 answers
589 views

What is the reason of RAM modules conflicts in terms of computer architecture?

What is the reason of such conflicts? I read a book "Computer architecture" by Andrew Tanenbaum, but didn't understand the reasons may cause conflicts with memory with different timings, frequencies.
spyder's user avatar
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2 answers
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Why do AVR microprocessors have two ways (paths) to access I/O ports?

I've an ATmega328P. Register Summary Page 275 ATmega328P datasheet. The first address is the I/O address, and the second is the data memory address. I'm going to set all (D ports) Data Direction ...
Amr Elkamash's user avatar
1 vote
1 answer
716 views

Verilog code execution in gate level modeling

The following is Verilog code an SR latch. ...
PG1995's user avatar
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1 answer
521 views

What is an emulator POD?

Jack Ganssle - The Firmware Handbook States ...
Dustin K's user avatar
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2 answers
2k views

How many ALUs (and threads) are in a Pentium CPU?

I'm reading a book bottom up where it said: The Arithmetic Logic Unit (ALU) is the heart of the CPU operation. It takes values in registers and performs any of the multitude of operations the ...
Marisha's user avatar
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3 answers
728 views

Computer architecture why is MemRead used?

Why is a control signal MemRead needed for the Data Memory element if whenever the output Read Data is not desired it will be multiplexed out via MemtoReg? Wouldn't having MemRead always enabled ...
Wodune's user avatar
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2 answers
121 views

Why unintended capacitances are an issue for the design of chips?

I understand as the clock frequency of a chip is increased, some issues arise. Probably, the most known issues are those related to the so-called "power wall", which alludes to the fact the thermal ...
Humberto Fioravante Ferro's user avatar
1 vote
2 answers
136 views

Is it OK to use the USB 5v pin as power source?

I am doing some stuff in my case and I need a power source for one LED from inside my case. I looked up and there are two +5v pins on a USB header inside my case. Is it OK to use them as power source?...
Atrotors's user avatar
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1 answer
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Use of $at register in MIPS?

Register r1 or $at, is it's sole use in pseudoinstructions? If so, is this the sole solution to enable pseudoinstructions within the architecture?
Entalpi's user avatar
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1 answer
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Calculate Paging System

I have this problem to solve and I have the answers, but I'm trying to understand the concepts behind it. A paging system has the following parameters: 2^32 bytes of physical memory; page size of 2^...
Carlo's user avatar
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1 answer
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5-stage pipelined implementation (RISC) of a microprocessor

I'm trying to solve two questions about a RISC 5-staged pipeline that is not exactly like MIPS found here (everything is included in this post). Consider the non-pipelined implementation of a simple ...
Carlo's user avatar
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2 answers
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8 bit octal full adder help

I have this project listen below and im not sure where to start maybe someone can give me a few pointers or perhaps point me in the right direction of starting this? Thanks!! Input: A, B = octal ...
soniccool's user avatar
1 vote
2 answers
2k views

How is sll implemented in MIPS?

I don't understand how MIPS would implement the sll (shift left logical) instruction using the hardware present in its ALU as shown in the diagrams below. Would ...
kene02's user avatar
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1 answer
119 views

Throughput increase/decrease by how much percent

I am learning computer architecture and organization. I am stuck in the following question. Can someone please help me? The stage delays in a 5-stage pipeline are 300, 200, 100, 400 and 350 ...
Anshul Gupta's user avatar
1 vote
1 answer
941 views

Do 64-bit CPUs consume more power than 32-bit ones?

In this lecture about efficient computing for deep learning, the benchmarks show a 3-fold increase in power usage between 8-bit and 32-bit addition operations. Between 8-bit and 32-bit multiplication, ...
Hey's user avatar
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3 answers
2k views

Effect of doubling clock frequency on computer performance

If we double the clock frequency of a CPU, does that translate to a doubling of the CPU performance? Assuming that the number of instructions and CPI are constant, we have an inverse relationship ...
Ski Mask's user avatar
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1 answer
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8085 MPU; Stepping through an instruction (Timing diagrams)

Let me write the steps of ADD B, as I've understood it till now. T0: ALE goes high Memory location(say \$2000_h\$) is taken from Program Counter to Memory Address Register(which points to the ...
Aravindh Vasu's user avatar
1 vote
1 answer
1k views

Is it posible that two devices plugged in different PCI slots share single PCI bus

Let's assume we have two network cards, Foo and Bar plugged in slots 5 and 4 on motherboard, with some BDF id assigned, for example: Foo => 09:00.0 Bar => 02:00.0 That's the usual scenario. But is ...
Outshined's user avatar
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2 answers
417 views

MAR vs Stack Pointer, Whats the difference?

So I was watching some videos on a guy "Building his own 8-bit computer", and the Memory Address Register (MAR) was attached to the SRAM. The MAR took the next Program Counter value and then looked in ...
msmith1114's user avatar
1 vote
2 answers
3k views

mips single-cycle branch verilog

I'm fairly new to Verilog, hardware design and computer architecture. Nevertheless, I've had a go at designing a simplified MIPS processor. It seems to mostly work fine but whenever I simulate it, it ...
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