Questions tagged [computer-architecture]
Computer architecture refers to both the design of a computer's external interfaces (instruction sets) and a computer's internal implementation (microarchitecture). The goal of these design decisions is to optimize speed, power efficiency, size, or cost while satisfying constraints on the rest.
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how does program counter stores the instruction memory when program is loaded? [closed]
it is mentioned in the book computer organization and design by Patterson/Hennessy page 252 that:
The instruction memory need only provide read access because the
datapath does not write ...
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karnaugh map and don't care states
I'm trying to figure out the boolean expressions I need for drawing a circuit based on a state transition table. I wound up with the k maps below, but I'm not really sure what to do with them. Would I ...
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Connect low-RPM motor to computer PSU
My ongoing (beginner) case-modding efforts have led me to desiring a spinning globe within my computer case. I would like to use a low-RPM motor (something between 4 and 20 rpm) for that and connect ...
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Benefit of (logically/virtually) separate I/O and memory bus
In my course on embedded systems, it is explained that memory inputs can be separated from I/O inputs using a "mode bit" for the address decoder. The most obvious advantage of this is that the amount ...
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Micro and Nano Memory, Calculate Reducing Bits?
I ran into a question:
in digital system with micro-programmed control circuit, total of 32 distinct pattern operation signal is ...
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Average Cycles Per Instruction
We have two different computers with the same instruction set. There are three classes of instructions (A, B, and C) in the instruction set.
Computer M1 has a clock rate of 80 MHz and Computer M2 has ...
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Suggestions for Ternary Computer Parts
I am thinking of creating a ternary computer from scratch, mostly as a hobby project, are there any parts out there that I could use? Or would I have to create them from scratch? If so, what would be ...
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What are the basics of using ROM-based controller in lieu of discrete logic
In Computer Architecture and Organization, how can one use ROM-based controllers instead of discrete logic? My teacher explained a bit, but I can't find any details anywhere online (well, I looked on ...
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unable to understand write policy in Cache memory
I am studying write policies in cache memory ( for first time ). I am able to understand the 'write-through' but i am not able to understand 'write back' and the problems associated with it . Please ...
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How does the Store Word(SW) and Load Word(LW) instructions work, MIPS
The SW and LW instructions are defined as:
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What drives an input from 0 to 1 inside of a digital circuit?
Inside of a digital circuit, like a computer, what is acting as the switch that drives the inputs or internal values from 0 to 1, and how does this work? Like in instructions for a computer, how are ...
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What do the diagonal lines in these circuits mean? [duplicate]
What exactly do these diagonal lines represent in these circuits? (I have them circled in red.)
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Has there been any deliberate implementation of combinational logic soft error correction in any consumer-level product, like a CPU/microcontroller? [closed]
Prologue
It is well known that many error detection, mitigation, and correction methods, such as parity or ECC, have been available in large memory banks, like for RAM, for decades now, and even in ...
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How can I modify single-cycle MIPS processor to implement jal command?
Hello Stack exchange community
I was wondering which modification should I have to make in order to enable single-cycle MIPS processor to run a jal(jump and link) command?
My most pressing confusion ...
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electrification of all transistors
We discussed a topic in the computer organization course. The professor told us that when the computer first turned on, all the transistors on the CPU are instantly electrified. So he said, keeping ...
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Why do magnetic disks not have multiple heads per disk?
So it seems to me that when trying to improve performance of a external memory device (HDD), the thing that is increased is RPM. Why not have multiple read/write heads per substrate instead of just ...
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Designing a Combination Lock FSM: Converting State Diagram to Logic Gates
I am trying to design a Synchronous combination lock for my digital logic class. I have the state diagram, as I understand how to draw out the logic which I want to follow. However, I am struggling to ...
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Cortex-M3, Code region vs SRAM/RAM
In the ARM Cortex-M3 processor core, the memory map contains: a Code region, SRAM and a RAM. What makes the use of the code region different than the other memories? In addition, what is the nature of ...
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Do smaller transistors improve computational efficiency because they decrease the duration of signal transfer?
There has been a massive improvement of computational power of computers per $ over time. As far as I understand, this has been driven almost completely by the massive increase in transistors per ...
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Why is it that true random number generators are not in every computer? [closed]
I understand that one of the fundamental pillars of the programmable computer, is that we should implement features with software rather than hardware, anytime it is possible & more efficient (or ...
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How does the computer's BIOS change the clock speed?
A computer's BIOS can change either the multiplier value or the (FSB) clock frequency to overclock or underclock a CPU. While overclocking by changing the multiplier value is easier and in more often ...
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Simplest display for homemade 8080 based computer-what to use? [closed]
I'm designing a 8080 processor based computer and I want it to be able to at least output something visually.
I have thought about using SMD LED matrix made by myself, but even with the 160 x 120 px ...
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How to Improve my Computer Architecutre and Design skills? [closed]
Though my undergraduation was in Computer Science but I like to believe that I am more of an embedded systems enthusiast and I am comfortable in reading datasheets and timing diagrams. But this was ...
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Bitwise shift operation from NAND?
I'm building an 8-bit computer using the Ben Eater's videos and I would like to improve the ALU, e.g. add nand bitwise operation because every logic gates can be built from this.
But I ask myself if ...
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Atmel SAME70 SDRAM Memory Mapping
In the Atmel SAME70-XPLD board, there is a 2MB (2 bank x 2K row x 256 col x 16 bit) SDRAM (ISSI IS42S16100F-5BL). It is connected as follows:
I don't understand why the A0 pin of the SDRAM is ...
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SMP, NUMA, local memory - limits on numer of processors
I consider what are limits on number of processor in following models of shared memory:
a. each processor has only own local memory.
b. SMP
c. NUMA
I can't see any limits. Am I wrong ?
user119974
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Difference between cordic algorithm and table based methods for elementary functions computation
In this book both Table Based methods and Cordic iterations are explained. computationally speaking i suppose the Table based is usually faster, even though it probably requires more resource, while ...
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Is depth and number of stages the same measure for a CPU pipeline?
Is it true that the depth of a CPU pipeline and the number of stages of a computer pipeline are different measures? There is not much info about it if I google or look in my books. I think that depth ...
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Exclusive execution unit in pipeline stage for execution of memory access instructions
I was studying pipeline concept in microarchitecture. My professor told me that memory read and write operations take longer time to execute since DRAM has a maximum frequency of 1333Mhz. Hence, when ...
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Design an 8x4 memory chip using 2x1 memory chips? [duplicate]
I have been given this task to design a single 8x4 memory chip using only 2x1 memory chips. I have been searching everywhere on google for some decent information or example of how this is done, but ...
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single cycle vs multicycle datapath execution times
I have a question where I need to calculate the execution time for a program for single cycle and multicycle datapath. I think I may be doing it incorrectly since the multicycle execution time is ...
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Why does the A8 have twice as many transistors than the Haswell processor yet runs on less power?
There's something I don't get - I am always under the impression that the more transistors we pack in, the more energy it consumes and the hotter it gets (assuming we haven't shrunk the die). However, ...
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How do you reduce an 8 output ALU to a 4 or 3 output ALU?
I can implement the functions in the picture below, but then if I implement them independently, I would have 8 outputs to the mux. Our professors wants us to reduce the ALU to only 3 or 4 outputs, I ...
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Connect ALU to CPU in Logism Circuit Design and output to 7-segment Display?
I've been playing around in Logisim to get some experience in designing basic electrical circuits. While I'm sure not the best, I was able to put together a functional ALU:
1-Bit:
This ALU is ...
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How is the zero flag set in terms of hardware? [duplicate]
I'm angling this as a general question on the assumption that it doesn't differ significantly with architecture - at least at the level I'm asking.
I'm curious how - in terms of hardware, not the ...
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Classic RISC pipeline question
Consider the following instruction sequence:
Add R3, R4, R5 (R4+R5->R3)
Or R2, R4, R5 (R4 OR R5->R2)
Add R1, R2, R3 (R2+R3->R1)
Assuming no data ...
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Different screw and their material purpose for computers [closed]
At our computer store, I had a luck to get to screw sorting (uh, how I like that) and got to question: is there any guide/rules, where should each of them be used. There are different color/material, ...
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How is the structure of a matrix addressable memory block realized?
Currently studying memory addressing in IC design, my professor mentioned matrix addressing and how it reduces the number of input lines to the memory block. But he didn't make himself clear on the ...
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Why use bytes instead of words for offsets in 'lw' and 'sw' instructions?
In assembly language, there are instructions like 'lw' (load word) and 'lb' (load byte). Both of these instructions involve adding an offset to a base address. It seems counterintuitive, however, that ...
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Mitigating structural hazards in register files in processor pipelines
I am reading about structural hazards in pipelined architecture in processors. In classic RISC pipeline one such hazard is when we write and read simultaneously to same register, which may cause ...
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Linkage pointer in procedure
https://ocw.mit.edu/courses/electrical-engineering-and-computer-science/6-004-computation-structures-spring-2017/c12/c12s3/procedures_answers.pdf
I don't understand how the linkage pointer can be the ...
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DRAM Rank-Level Allocations
I want to do allocations on a specific DRAM rank. The smallest allocation unit in an OS such as Linux is at the page size ...
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In Directed-mapped cache, a problem in exercise!
5.2 Caches are important to providing a high-performance memory hierarchy
to processors. Below is a list of 32-bit memory address references, given as word
addresses.
3, 180, 43, 2, 191, 88, ...
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The number of cycles needed to execute the following loop in pipeline processor?
This question was asked in an objective paper; GATE CSE
Consider a 4 stage pipeline processor. The number of cycles needed by the
four instructions I1, I2, I3, I4 in stages S1, S2, S3, S4 is shown ...
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Flushing in pipelined architectures
How is the flushing really implemented? I have an idea that on conditional branches, the prior instructions are flushed. But how are they actually flushed?
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Understanding execution of sequence of pipeline instructions
I need help in understanding the solution from solution manual. The question is from the exercise 4.22.2 of chapter 4 in the book Computer Organization and Design by Patterson and Hannessey (4th ...
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Understanding processor instruction pipeline problem solution
I need help in understanding the solution from solution manual.
The question is from the exercise 4.13.5 of chapter 4 in the book Computer Organization and Design by Patterson and Hannessey (4th ...
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How instructions get executed in a pipelined architecture?
I saw this HW solution in CMU Comp Arch course website. I am reading ComputerArchitecture on my own. I just have a doubt.
Here is the HW question:
Given the following code (MIPS):
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Implement BGEZAL instruction-MIPS-32 in verilog
I want to implement MIPS-32 Single cycle microarchitecture using Verilog. I have few doubts regarding the instruction BGEZAL.
It does GPR[31] = PC + 8.
The BGEZAL ...
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