Questions tagged [computer-architecture]
Computer architecture refers to both the design of a computer's external interfaces (instruction sets) and a computer's internal implementation (microarchitecture). The goal of these design decisions is to optimize speed, power efficiency, size, or cost while satisfying constraints on the rest.
68 questions with no upvoted or accepted answers
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Can anyone tell me what other computers used this floating-point format?
I have discovered that the DEC PDP-10 used a floating-point format that differed from IEEE-754 in an interesting way.
IEEE-754 is like sign-magnitude representation. The only difference between a ...
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3
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1
answer
115
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On understanding tradeoffs associated with pipeline depth
In Weste and Harris's CMOS VLSI Design, they write the following in the context of a discussion about how different levels of design abstraction interact but, to be clear, my question is about the ...
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How to using JAL in RISCV in this example?
Write a "replace" function that replaces every character in the source string between the first occurrence of character "(" and the first following ")" with character &...
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Intel Compute Stick & USB 4G Device
Id like to create a powerful IoT Edge device that has cellular capability (Wifi is undesirable). Right now the intel compute stick/neural stick almost fits the bill except that it does not have 4G ...
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3
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1
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Thermal overload trip in chips
I have read that the thermal design power (TDP) is an important metric while considering energy and power trade off related to microcontrollers. It is said that TDP determines the cooling required and ...
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2
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1
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Differences in capacitive loads
I'm in school and I am trying to figure out a question for homework. It reads as stated:
Version
Voltage
Clock Rate
i.
Version 1
1.75V
1.5 GHz
Version 2
1.2V
2 GHz
ii.
Version 1
1.1V
3 GHz
...
2
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1
answer
3k
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MIPS clock cycle calculation formula
How many clock cycles will take execution of this segment on the simple pipeline without forwarding or bypassing when result of the branch instruction (new PC content) is available after WB stage. ...
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479
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Digital Comparator from LSB to MSB using Lookahead
This is homework to be upfront, but I'm really stuck on it and just need some kind of direction. I've been assigned to create a 16-bit lookahead comparator going from LSB to MSB using no more than 4-...
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Ling adder vs classic CLA adder what's the difference?
I'm practicing in designing vhdl unit with some "complex" computer arithmetic algorithm.
I've just implemented the following CLA unit below.
I'm reading through this book, page section 6.3 page 97, I ...
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0
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407
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Analysis of Branch misprediction in MIPS 32 bit architecture
I am confused about what happens when we use a Bimodal branch predictor in the MIPS architecture shown in the image below.
I am considering the case where there is already a branch delay slot ...
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Operator synthesis VHDL, numeric_std.vhd
if i include the library numeric_std.vhd
(the implementation is here https://standards.ieee.org/downloads/1076/1076.2-1996/numeric_std-body.vhdl) you can see that the operator *,+ (as instance are ...
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What CPUs use a skewed associative cache?
What CPUs use a skewed associative cache?
I see several people imply that, with roughly the same hardware, a skewed-associative cache often has better performance than a traditional set-associative ...
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How to understand t and t-1 in DFF mechanism?
I'm following the course From Nand to tetris. In chapter 3, the authors introduce the notion of Data Flip-flop (DFF), which computes the output(t) = input(t-1) where t is the time.
My question is that ...
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1
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0
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53
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Wrong value in memory because of a branch misprediction
Lets say we have instructions like:
bne r1 $0 loop
sw r2 0(r1)
Let's say we go ahead with the taken path, i.e., execute the sw instruction after bne assuming the ...
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0
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130
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How to solve pipeline hazards using stalls?
So, I have the following code, which should run on a five-stage pipeline (Fetch, Decode, Execute, Memory, Write). Now, we need only to consider read-after-write data dependencies and find the total ...
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0
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SRT division: correcting BSD quotient
I have been reading a lot about the SRT division algorithm lately and I understand that the main idea is that it allows us to skip over addition/subtraction, unlike non-restoring division where we ...
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337
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Understanding Forwarding unit
I am new to this subject and am having trouble understanding this topic.
Suppose I have the following circuit to control the forwarding of a MIPS pipeline processor:
So the forwarding control will be ...
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1
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0
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Are coarse-grained reconfigurable architectures a subset of dataflow architecture?
By definition, dataflow architectures consist of large modules in the dataflow path, such as adders and multipliers for integer, floating-point, or fixed-point computation.
Hence, are coarse-grained ...
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How much faster is the ideal machine without the memory structural hazard versus the machine with the hazard?
I am learning computer architecture and organization. I have the following doubt. Given below is a question along with its solution but I think that the solution is wrong. You can see the question ...
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Difficulty in understanding the concept of operand forward in pipeling and when to use split phase
Given below is a question from \$\text{GATE } 2015 \text{ CS}\$ paper,
Consider the sequence of machine instruction given below:
\begin{array}{ll} \text{MUL} & \text{R5, R0, R1} \\ \text{DIV} &...
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652
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How to find Base CPU Time and Memory-Stall Time
The program described below runs on a multiple issue processor with a 3-level CPU cache, a 4 GHz clock frequency, and the following performance metrics:
Miss Penalty R/W
Data Miss Rate
Instruction ...
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1
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0
answers
56
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How did the arithmetic organ in ENIAC?
I have been reading the book of Goldstine on computers and I was wondering how ENIAC could activate a computation using numbers (the antecedent of the stored program concept).
Goldstine wrote that ...
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1
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0
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598
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How to cascade IC 74HC161 correctly?
Currently I have this 4 bit CPU as shown in the schematic diagram below.
What I wish to achieve:
Add one more output register to make the CPU output a total of 8 bits
Show alphabet using the 8 bits ...
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1
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0
answers
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DRAM Self-Refresh not the Lowest Power Mode
I have a DDR3L Samsung DRAM on my Laptop. Based on page 23 of its datasheet, IDD6 or the ...
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1
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0
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145
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DMA SPI performance
I am currently writing an SD card driver for a Microcontroller using SPI and DMA. The SPI has a FIFO that can store 4 data values from the data register which has the capable of storing 32 bit. But it ...
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0
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54
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A Problem dealing with Cache memory on a computer
This is Problem 13-3 from the book "Logic and Computer Design Fundamentals" by M. Morris Mano and Charles R. Kime. I believe I have the answer right for part a and part b. That is, they match the ...
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1
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0
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Cache Memory Read and Write Miss/hit policies: details of a real processor
All the references I have checked so far explain the Read Miss,Write Hit/Miss policies at the same level of detail. I understand their concepts but I am looking for more details on their ...
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1
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1
answer
71
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External bus interfacing
This lab requires us to extend the memory and I/O ports on our µPad using our EBI backpack. What I'm confused about is how the fully address decoded SRAM will differ from the partially addressed i/o ...
1
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0
answers
226
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Can a classical Toffoli gate be built from irreversible gates?
The Toffoli gate is a reversible gate with three inputs (A, B, C) and three outputs (S1, S2, S3) generated as
S1 = A
S2 = B
S3 = AB ^ C
It can be implemented in a classic way using the following ...
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0
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53
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Finding percentage memory utilization in pipelining architecture
I was solving problems from the exercise of the book "Computer Organization and Design" by Patterson. The problem reads like this:
Consider stage latencies:
...
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Renaming a special register
I noticed that RISC-V, like some other RISC architectures, by convention treats register 1 specially, using it as the link register, holding the return address for function calls.
If most code ...
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2
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How to calculate the cycle time of pipeline
I have an 8-stage pipeline (IF,ID,OF1,OF2,OF3,Ex1,Ex2,WB) with respective stage delays as 5ns,4ns,10ns,6ns,8ns,11ns,9ns,13ns respectively. The interstage registers have delay of 1ns.
I think here the ...
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943
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multi-cycle risc-v ZERO control line for branch
I have been having trouble to understand how exactly the execute stage in risc-v processor for branch works. what I understood is that the ZERO output from ALU calculations for branch produces zero ...
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How do I draw the truth table of an adder/subtractor that sets flags, and those flags are the inputs of a comparator?
How do I draw a truth table of a circuit that :
starts off with a full adder/subtractor
outputs the result F based on the two inputs (add if opcode is 0, subtract if opcode is 1)
then output three ...
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0
answers
87
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How to drive an HDTV with an 8 bit MPU?
Is it possible/reasonable to generate a 480 x 270 image with an 8 bit MPU, store the image in external memory, upscale the image to 1920 x 1080, and generate an HDMI signal for the upscaled image? ...
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353
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find cache hit rate for direct mapped cache memory
I have this practice exam problem which I am having trouble with. I have gone over many slides but haven't been able to really get it. The question is
I currently have an 8 block main memory with 2 ...
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SAP-1 (Simple as Possible) W Bus
I'm currently investigating the SAP-1 to build in order to grasp a really good understanding of simple 8 bit computers.
There are a few questions that I would like clearing up.
What exactly is the ...
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60
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RISC-V Exercise: why is `MemtoReg = 1`?
Given the instruction sd x12, 20(x13) (ISA RV64I), what are the inputs and outputs of the encircled MUX?
My answer: if x[n] is ...
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Applying analog computer with passive circuit only
TLDR
You can skip to question section.
Intro
I know the analog computer was actually invented long ago. I don't know how analog computer architecture was, but I guess it was using active components.
...
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0
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63
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nand2tetris ALU Question
So im working on the ALU for the nand2tetris course online (for fun) and it's "design" is supposed to be as such:
...
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does data and instruction memory we see in the data path corresponds to the L1 Instruction and Data cache inside of the core?
In CPU data path there are blocks called data memory and instruction memory ? Are these blocks L1 Instruction and L1 data caches ?
For instance check figure 4.10 in this link.
We know that generally ...
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1
answer
292
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How to implement the Instruction Set in Logisim
I have an assignment that requires me to build an 7-bit CPU. I’m done with implementing some of the requirements that includes 4 8-bit registers (the requirements say I have to store the parity bit), ...
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1
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325
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Alu Control output not return 010 for Addi instruction
I'm currently working on a project for a MIPS Datapath Simulation website. The project aims to demonstrate how instructions work. I've implemented the Alu Control Unit using the combinational logic ...
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1
answer
62
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Retrieval of information from a sequential circuit
SR-NOR Latch circuit is a sequential circuit in which there exist two, different modes Reset and Set. Electricity flows along ...
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118
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Mark Horowitz Computing's energy problem - methodology
I have a question about the Mark Horowitz paper: Computing’s Energy Problem
(and what we can do about it). In the paper, the author breaks down the sources of energy loss in modern computing systems.
...
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Can we service another memory request from L1 cache when an L1 miss is being serviced from L2?
Consider the case where L1 cache miss occurred and is being serviced by L2 cache which could take many cycles (may go to main memory in case of L2 cache miss). In the meantime L1 cache is idle, in ...
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Help with Register File Implementation on Logisim
I'm currently working on an assignment that involves implementing a register file with 2 read ports and 1 write port on Logisim. I've made some progress but I'm struggling with a few questions and ...
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0
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How to estimate how bad the wire delay can be when I am designing a chip?
I am currently working on a program involves designing a Neural Network accelerator architecture. I don't have a very deep background in digital circuit, but I know long wires may incur heavy delay ...
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1
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Designing instruction emulating swap on a MIPS ISA with only 2 registers
In a typical MIPS ISA, you have only 2 working registers. But you have a large number of ALU units.
How to design an instruction to emulate swap?
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A simple question on pipelined MIPS
For branches/jumps the PC is always muxed from the MEM stage. Why don't we mux it from the EX stage itself instead?
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