Questions tagged [computer-architecture]
Computer architecture refers to both the design of a computer's external interfaces (instruction sets) and a computer's internal implementation (microarchitecture). The goal of these design decisions is to optimize speed, power efficiency, size, or cost while satisfying constraints on the rest.
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How can we be sure that computers will never accidentally switch a 0 by a 1?
I've read a bit about the construction of a digital computer in Shocken/Nisan's: The Elements of Computing Systems. But this book says nothing about certain electrical aspects in computers, for ...
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Why is digital serial transmission used everywhere? i.e. SATA, PCIe, USB
While looking at SATA, PCIe, USB, SD UHS-II it struck me that they are all the same: digital serial bitstream, transmitted using differential pairs (usually 8b/10b coded), with some differences in ...
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How can a CPU deliver more than one instruction per cycle?
Wikipedia's Instructions per second page says that an i7 3630QM deliver ~110,000 MIPS at a frequency of 3.2 GHz; it would be (110/3.2 instructions) / 4 core = ~8.6 instructions per cycle per core?...
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Why are NAND gates used to make AND gates in computers?
Why is this a standard for AND gates
when it could be made with two FETs and a resistor instead?
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How can cache be that fast?
Here is a screenshot of a cache benchmark:
In the benchmark the L1 cache read speed is about 186 GB/s, with the latency being about 3-4 clock cycles. How is such a speed even achieved?
Consider the ...
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Is analog signal arithmetic faster than digital one?
Would it be theoretically possible to speed up modern processors if one would use analog signal arithmetic (at the cost of accuracy and precision) instead of digital FPUs (CPU -> DAC -> analog FPU -> ...
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Why does Intel's Haswell chip allow floating point multiplication to be twice as fast as addition?
I was reading this very interesting question on Stack Overflow:
Is integer multiplication really done at the same speed as addition on a modern CPU?
One of the comments said:
"It's worth nothing ...
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Why is open hardware so rare? [closed]
I'm trying to understand why open hardware is so much harder to come by than software. I've tried looking around online and I couldn't find as satisfactory explanation.
I understand that hardware is ...
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Why is the Digital 0 not 0V in computer systems?
I'm taking a computer system design course and my professor told us that in digital systems, the conventional voltages used to denote a digital 0 and a digital 1 have changed over the years.
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What exactly does ARM sell to vendors?
Assumptions:
Computer architecture: Describes how the different modules of a processor interact with each other.
A computer architecture is defined using vhdl ...
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Is transistor the only electronic component on a CPU?
I have been reading about CPUs recently and came to know that all logical blocks and memory on CPU can be made out of transistors. So is it the only electronic component on CPU?
Edit (Made after ...
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Why are relatively simpler devices such as microcontrollers so much slower than CPUs?
Given the same number of pipeline stages and the same manufacturing node (say, 65 nm) and the same voltage, simple devices should run faster than more complicated ones. Also, merging multiple pipeline ...
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Why do CPU's typically connect to only one bus?
I found a motherboard architecture here:
This looks to be the typical layout of motherboards. EDIT: Well, apparently it's not so typical anymore.
Why does the CPU connect to only 1 bus? That front-...
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What are the advantages of using FPGAs over TTL in intro computer architecture?
I teach the one and only computer architecture course at a liberal arts college. The course is required for the computer science major and minor. We do not have computer engineering, electrical ...
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What do we mean when we say something is done "in hardware" versus "in software"?
Describing a specific operation as being done "in hardware" versus "in software" in a given computer system is common. For example, simple computer systems (I am assuming) might ...
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Why MIPS uses R0 as "zero" when you could just XOR two registers to produce 0?
I think that I am looking for an answer to a trivia question. I am trying to understand why the MIPS architecture uses an explicit "zero" value in a register when you can achieve the same ...
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How can a CPU dynamically change its clock frequency?
My Intel CPU changes clock speed depending on the usage, but how does it decide what clock speed to run at? Is the clock speed determined by the OS software using an algorithm, or is it hardware based?...
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Why do we need nonlinear electronics for computing?
When I read about photonics, I always see that they can be used for linear transformations (just matrix multiplications), and that this is a limitation that makes them unsuitable for building a ...
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What does banking mean when applied to registers?
This answer to a question on StackOverflow about what banking means in the context of ARM's banked registers indicates that there is some confusion about the meaning of banking when applied to ...
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Why do computers only use 0 and 1?
Why do computers only use 0 and 1? Won't the addition of other numbers such as 2 or 3 speed up computers? Also, 2 and 3 can be used to shorten the bit-length of integers (2 and 3 can be used to end an ...
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How many clock cycles does a RISC/CISC instruction take to execute?
According to Digital Design and Computer Architecture by Harris and Harris, there are several ways to implement a MIPS processor, including the following:
The single-cycle microarchitecture executes ...
user76520
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Do computers speed up at higher temperatures?
At higher temperatures, will computers get faster? Evidently, one always wants cool a computer down as higher temperatures can damage core components.
However, is it an interplay between silicon, ...
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How to efficiently design the opcode for a CPU?
I am building a simple 16-bit CPU in Logisim and have the ALU ready and the opcodes that I want to have.
Now I find it really hard to find the right coding for the commands so that the different ...
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Using CCM (Core Coupled Memory) in STM32F4xx
STM32F4xx microcontrollers have 128KB of SRAM + 64KB of CCM SRAM. CMM SRAM is hardwired to data bus so it is impossible to use it with DMA.
What is the reason to add additional SRAM as CCM?
Does it ...
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How does the Harvard architecture help?
I was reading about arduino and the AVR architecture and got stuck at the point that how does pipeline stall or bubbling is solved by Harvard architecture introduction in the AVR.I mean what Harvard ...
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Why do we see one, unified memory address space in ARM Cortex-M core based MCUs even though they have Harvard architecture?
Most of the ARM Cortex-M core based MCUs have Harvard architecture (except for Cortex-M0 and M0+.)
The thing I do not understand is that why we see only one memory address space. For example, in tge ...
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What does it mean for a CPU to support a stack?
How can a CPU not support a stack? Doesn't any architecture that uses subroutines (I'm pretty sure that's all architectures) have to push the return address onto the stack so it can return to where it ...
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How does an operating system or program detect the CPU model name? [closed]
What kind of binary compatibility is present for 2 processors sharing an Instruction Set?. I had asked a question on Computer Science Stack Exchange, to which I got an answer which said:
As a trivial ...
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Why isn't the BIOS' ROM chip made using CMOS technology?
After reading a computer hardware course on BIOS/CMOS, I'm still unable to determine the reason why the BIOS' ROM chip isn't built using CMOS technology, and why it is connected to a separate chip ...
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Is it correct that in a hard disk both surfaces of each disk are capable of storing data?
I have read that in a hard disk both surfaces of each disk are capable of storing data except the top and bottom disk where only the inner surface is used. Is it correct if yes then why is are there ...
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Estimating current draw for a single instruction
I am a software engineer concerned about current draw.
I am aware that there are ways to reduce the current draw of a program, for example:
using a hlt instruction ...
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CPUs for retro computer school project
I'm a student in an IT school and we are trying to think of a project we could use to show 1st year students how things work behind the stage and we eventually thought of making a retro computer.
I'...
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Clocked edge-triggered timing (contamination delay)
I'm reading a book about computer architecture, and it says that, in clocked edge-triggered devices, the contamination delay is usually nonzero, and that the contamination delay for registers is ...
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Why should I learn a microcontroller architecture? [closed]
I recently started working in a small company that produces automotive diagnose related electronics. My boss, who is in his mid 50's, said that he was using 8051 derivatives, and they were doing the ...
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Are 32-bit ALUs really just 32 1-bit ALUs in parallell?
I'm reading the high esteemed text Computer Organization where this picture is found that is supposed to represent a 32-bit ALU:
Is this technology really how it's done, just a lot of 1-bit ALUs, so ...
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What are ALMs, LEs and ALUTs?
Does ALM mean "Adaptive logic module"?
www.altera.com/literature/ds/ds_nios2_perf.pdf
Jul 1, 2013 -
One ALUT is equivalent to about 1.25 LEs.
Does LE mean logic element and ALUT means adaptive ...
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Is it realistic to expect full Spectre fix in branch predictors of future CPUs?
Recently, it has been observed that two branches sharing the same branch predictor state in the same process or even across processes allows certain side channel exploits (Spectre).
Let's consider a ...
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What is the simplest instruction set that has a C++/C compiler to write an emulator for? [closed]
I'm looking into writing a little software emulator that emulates/runs instructions.
The easiest would be to invent my own instruction set, but I thought it would be more fun if I write an emulator ...
user138530
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Are the instructions fetched from RAM or ROM in an ARM micro-controller?
In many tutorials regarding ARM CPU registers, the instruction register is mentioned in such way: "Register R15 in ARM micro-controller is the program counter and it points to the next instruction to ...
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How does pipelined CPU access both code and data memory in real life?
In the Digital Design and Computer Architecture RISC-V Edition page 442, a pipelined CPU is designed with separate instruction and data memories, as shown in the figure below.
However, this picture ...
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How are BAR registers handled between end points in PCI Express?
I have a question related to the PCI Express protocol.
I managed to understand most of the features of the PCI Express protocol but could not entirely understand the enumeration process.
I know the ...
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Question about an Intel USB Host Controller power supplied per USB port
I had a general question regarding the Intel(R) 82801FB/FBM USB Universal Host Controller (ICH6). The ICH6 has five USB Host controllers in it, with (I'm assuming) two physical USB ports per ...
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What information exactly does an instruction cache store?
Processors use both data and instruction caches in order to reduce the number of slow accesses to main memory. However, while it is clear to me that the data cache's purpose is to store frequently ...
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Why are DIMMs not equipped with a heat sink like a CPU?
I know that a DIMM is composed of a set of chips that contain control logic managing the decode and prefetching memory operations. According to a product specification, I found that newer RAM works at ...
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Why do computer circuits tend to have so many resistors and capacitors? [duplicate]
As someone who has a decent understanding of computer architecture (but not of electrical engineering) I've always wondered why computer circuits tend to have so many resistors, capacitors, and other ...
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Why can computer circuits recognise only two states?
Computers can only understand binary (that is 0s or 1s). I want to know Is there any way that computers can understand more than 2 states. I know that It is much harder to build components that use ...
J.Smith.JJJ
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Processor design: turning blocks on/off dynamically to save power?
I was wondering if this is possible and if it is done in current designs. Seemed like an interesting enough idea to me. Here's a little diagram I made to help try and explain:
So let's say I'm clever ...
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Choice of number of chip select pins in a RAM
I was going through Mano's "Computer architecture " , in chapter memory organization they have used a RAM chip with 2 chip select pins CS1 and CS2' but i can't think of the reason why , all the chip ...
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Should "get new sensor data" be its own task in an RTOS?
I am new to RTOS coding practices/architectures, and am specifically learning on RTX. Should I have a get_new_sensor_data task for each sensor, or is sensor data usually taken care of by some other ...
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4-bit decrementer using four Half Adders
Like the title mentions, is it possible to design a 4-bit decrementer using just four Half Adders? I know it's possible using 3 Full Adders + 1 Half Adder, but I don't seem to find a way to do that ...
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