Questions tagged [constraints]
The constraints tag has no usage guidance.
1
vote
2answers
66 views
Constrain plane clearance from annular ring in Altium
I need to constrain a plane from shorting to the annular rings of a number of vias.
The dialog found at ...
3
votes
1answer
101 views
How to estimate timing contraints for FPGAs?
I try to find out how to specify the timings restrictions in FPGA designs correctly (in .sdc/.xdc files). I know what setup and hold times mean. However: How do I find out, what timing constraints my ...
3
votes
2answers
81 views
SDC constraints for source clock and derived clock
There are two clocks in the system, clk2 is derived from clk1 with a 180-degree phase shift. There is 1-bit data from clk1 to clk2.
I know this is a kind of asynchronous scenario and the traditional ...
2
votes
1answer
216 views
Vivado : constraints setup for SPI interface with common clock
I have been using Vivado 2018 for a system level design and am having trouble with a SPI interface programming. A block diagram of my system is shown below.
The Artix-7 FPGA (on the motherboard) ...
0
votes
0answers
251 views
How to fix 'timing constraints not met' error caused by Xilinx Cordic IP?
I made a window function generator IP in Xilinx Vivado. It works well in the simulation. When I tried to implement for Zedboard, it gives a timing error. The error is caused by Cordic IP used for ...
1
vote
2answers
608 views
Altium Unrouted Net in Fill
I am trying to use vias on a fill to connect copper in Altium, but I keep getting unrouted net constraint errors. I have the following:
The red square and blue rectangle (which extends fully ...
4
votes
2answers
184 views
FPGA automatic pipelining?
I have a synchronous datapath in my design that fails negative slack timing check, and I could most likely fix it by putting extra pipeline registers between datapath blocks by changing RTL sources.
...
0
votes
1answer
1k views
Writing SDC constraints for asynchronous clocks
I am new to SDC constraints, in synchronous clock definition say A and B are synchronous with each other, then we can define create_clock on A port (input) and <...
-2
votes
1answer
120 views
Is it possible to integrate all passive components? [closed]
Looking at a Circuit Board from a recent consumer product, I still see many discrete components (diodes, resistors, capacitors, amplifiers), which occupy space and have to be soldered into the board.
...
2
votes
1answer
185 views
LTSpice constraints on plots
A have a circuit for which I have parameterized some of its resistors with the .STEP command. Consequently, I have many different graphs when I simulate the circuit. I would like to know if it was ...
0
votes
1answer
50 views
Lower Power Inductive Heating Circuit Design Questions
I'm trying to design a very low power (<=10W) inductive heating circuit that will heat the work material to 40-50degC. I've seen plenty of Royer Oscillator circuits online (see here: http://www....
1
vote
2answers
933 views
How to get a default UCF file of Xilinx Virtex-5 XC5VLX110?
How to get a default UCF file of the Xilinx Virtex-5 XC5VLX110?
It doesn't seem to be anyhere. If I have to make it by myself, would you let me know how to ...
3
votes
0answers
600 views
How to specify a minimum clock to output time in output timing constrain?
In design, an external clock pin triggers a flip-flop, where the output goes to an external data pin.
Using Xilinx ISE, how can I specify a timing constraint, so the output should be held for some ...
3
votes
2answers
1k views
SDC constraints for two flop sychronizer
I have doubt, What should be proper SDC constraint for CDC module, i.e., two flop synchronizer.
between "dat driving by aclk to <...
3
votes
0answers
541 views
Timing constraints for DDR output multiplexer
Consider the following circuit, which multiplexes the d0 and d1 inputs to the y output in ...
1
vote
0answers
691 views
How to specify timing constraint for two paths to have a equal delay in Vivado
I am trying to sample an asynchronous signal in multiple clock-domains. I do not care too much about the absolute delay from the source of the async signal to the sampling FF's, but I want to ...
0
votes
1answer
153 views
Constraint relative arrival time for a group of signals
Imagine a situation where the absolut delay of a group of signals doesn't matter, but it must be ensured each signal of the group has roughly the same delay until it reaches a certain point, say a FF. ...
2
votes
1answer
505 views
Multicycle : Is it possible?
I've to constraints an Lattice Semiconductor FPGA and I've some doubts about the multicycle constraint described here. I've the following RTL :
Basically it is a counter that is driven by a rising ...
2
votes
1answer
809 views
Setup and hold time violation constraints for Xilinx Fifo generator
I have a problem concerning the Xilinx Fifo generator and timing contraints described in the fifo manual.
I am using the fifo generator version 9.2 (manual ) to generate a fifo.
I would like to ...
2
votes
1answer
675 views
BlockRAM location constraints (Xilinx)
I have a VHDL module in which several block RAMs are inferred. Now I would like to place these block RAMs into a certain region of my FPGA (close to some IO pins).
How do I do this using Xilinx ...
5
votes
1answer
1k views
Understanding timing constraints
I don't want an introductory text on timing constraints, nor an application note, an user manual, a webinar. I read them all, already, many times. The concept behind timing constraints is very easy. ...
0
votes
2answers
2k views
Setup and hold time
Of the setup and hold timing constraints which are to be met to get a stable output, which one is critical in estimating the maximum clock frequency of a circuit?
3
votes
2answers
2k views
Clock domain crossing timing constraints for Altera
I have a slight problem with my clock domain crossing timing constraints.
I have two clock groups
set_clock_groups -asynchronous -group {clk_A} -group {clk_B}
...
5
votes
1answer
899 views
How do you constrain input delay for a multidimenionsal input vector?
I am defining SDC input constraints for synthesis of a small module that is part of a larger ASIC design. I plan to run the module through synthesis using Synopsys tools. A few of the inputs to this ...
2
votes
1answer
341 views
Rise/fall time constrains for ADC?
Does the sampling clock rise/fall times for ADCs matter, or they can be virtually 0 seconds? Can they be slow? In particular, I could not find anything about rise/fall time constrains for AD9235.
...
0
votes
1answer
1k views
What is the use of OFFSET IN/OUT constraint for FPGA design when using register in IOB?
The following is asked in the context of Xilinx FPGAs (my experience), but may also apply to similar technologies offered by other vendors.
Background: When writing constraints for FPGA I/O, there ...
10
votes
2answers
5k views
ASIC timing constraints via SDC: How to correctly specify a multiplexed clock?
Introduction
Having found multiple, sometimes conflicting or incomplete information on the internet and in some training classes about how to create timing constraints in SDC format correctly, I'd ...
6
votes
1answer
9k views
ASIC timing constraints via SDC: How to correctly specify a ripple-divided clock?
Introduction
Having found multiple, sometimes conflicting or incomplete information on the internet and in some training classes about how to create timing constraints in SDC format correctly, I'd ...
2
votes
3answers
7k views
Fix Conflicting IO Standards
I am using the Basys 2 Spartan-3E FPGA board with Xilinx. I need the pmod i/o to be at 1.8v so I am using LVCMOS18 IOSTANDARD.
You can find all of the IOSTANDARD's available for Spartan-3E in this ...
3
votes
1answer
5k views
Does it always make sense to constrain an I/O port?
I am following an Altera online course on their timing analyzer software called TimeQuest. In it, their recommend that, at the very least, all clock and I/O ports be constrained.
In my FPGA design, I ...
6
votes
1answer
2k views
Discrepancy between post-Place-and-Route static timing analysis and ISIM simulation results
Overview
I'm implementing a simple Harvard-style CPU using Xilinx ISE version 14.1. I'm using settings compatible with a Digilent Nexys3 board, but for the time being the entire project is performed ...
3
votes
1answer
554 views
On the use of “BLOCK INTERCLOCKDOMAIN PATHS”
I based an FPGA design on Lattice reference code that, in the timing constraints .lpf file, specifies:
...
2
votes
1answer
1k views
constraint error and illegal load problem in Virtex-2
I am trying to test a very simple deskew circuit on a virtex-2pro FPGA (xc2vp30-fg676-5). I use xilinx ISE and the deskew IP (two DCMs with a DDR flop) provided by core generator. I also try to ...
9
votes
3answers
3k views
Op amp analysis: when are the “negative feedback rules” applicable?
When we build op amp circuits that use negative feedback, like so:
... we can analyze the circuit very easily, by assuming that $$v^- = v^+$$ due to negative feedback (when also assuming the op amp ...
5
votes
1answer
2k views
Analog Video PCB Layout
What special considerations and/or constraints are typically applied when routing analog video signals on a PCB (e.g. VGA, NTSC, etc). I'm thinking try and keep them routed on a single layer (i.e. at ...
10
votes
2answers
15k views
EAGLE Matched Length Pairs / Groups
What facilities does EAGLE CAD have for helping to do layout with matched length groups and differential pairs? Can you apply such a constraint in the auto-router? As a follow-on to this, what (other) ...
