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How to use FPGA system clock for my design in vivado?

Problem is my device don't use system clock generator (what me need) for synchronization,but use clock signal is generated by TestBench what connected via external I/O ports of FPGA. I have ...
Vladislav Butko's user avatar
1 vote
0 answers
185 views

FPGA DDR timing constraints

I have EMMC master for FPGA. Please tell me how to write constraints on ports in DDR mode? I tried to write constraints but I doubt the correctness Specification: JEDEC Standard No. 84-B51 P.S. Here ...
strontiuman's user avatar
1 vote
2 answers
80 views

Altium: Is it okay to waive this constraint violation between two elements of the same electrical component?

All of my electrical components are listed as having such clearance constraint violations when I open the PCB Rules and Violations window. I have tried lowering the minimum clearance from 0.254 mm to ...
eutectic_codswallop's user avatar
0 votes
1 answer
105 views

FPGA output timing explained

As a hardware designer you have consider the timing constraints of both the input and output device. Input devices specify a setup and hold time reference to the clock (the time in which the data ...
Dukel's user avatar
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1 answer
244 views

Timing parameters of sequential circuit - digital electronic

Problem Determine the timing parameters (\$T_\text{cQ,bb}, T_\text{su,bb}, T_\text{h,bb}\$) for the black box logic circuit seen below: - Attempt \$T_\text{cQ,bb}\$ is the time it takes for the ...
Carl's user avatar
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Calculating timing constraings for interfacing with sdram

I want to set the set_input_delay and set_output_delay constraints for my design but I'm having trouble to find the values to calculate them. My understanding so far: To calculate the set_output_delay ...
TimSch's user avatar
  • 209
3 votes
1 answer
75 views

Best practice to constrain dynamically tuned FPGA->DAC data path

Data is moved from the Zynq 7010 to AD9779A DAC using parallel SDR link at 155.52MHz. This DAC generates DATACLK clock that is used to clock data out of the FPGA (see picture for the relevant FPGA ...
Oleg Skydan's user avatar
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1 answer
808 views

How can I declare individual PMOD pins as input or output in an FPGA?

I have a Xilinx Basys 3 demo' board, which contains the Xilinx Artix-7 XC7A35T-1CPG236C FPGA. I want to use the board's PMOD header as an SPI master interface. Most of the pins are outputs, but MISO ...
Martel's user avatar
  • 1,259
2 votes
1 answer
674 views

How to constrain a source-synchronous FPGA input?

I have a source-synchronous input to my FPGA (an Intel Cyclone 10 GX 10CX085), coming from an external chip whose datasheet gives the following information: fmax = 300 MHz (single data rate) tsetup = ...
Harry's user avatar
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1 vote
1 answer
251 views

Use SDC format for timing constraints on Xilinx CPLDs

Due to the chip shortage, I'm trying to perform timing analysis of an existing CPLD design for a number of alternative chips from different manufacturers. I have existing hardware description source ...
Ben Voigt's user avatar
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SDC constraint inside Xilinx ISE

Inside ISE timing constraint editor window, which following sub-section shall I use set_clock_group to solve the STA setup timing violation path #1 due to cross-clock signal ?
kevin998x's user avatar
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3 votes
1 answer
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How to correctly constrain a clock network with lots of mux branches?

Let me simplify a common clock network structure used in my company: Firstly, there're multiple true clock sources (PLLs, external input, or RC OSCs). Right at the beginning when these sources are &...
Light's user avatar
  • 351
1 vote
1 answer
319 views

Unable to constrain HPS peripheral pins on intel agilex fpga dev kit

I'm having trouble getting the Hard Processor System (HPS, the embedded hard processor of the agilex fpga series) to work properly on the Intel Agilex Dev kit version 3. The issue says that that there ...
Doralitze's user avatar
2 votes
1 answer
639 views

SystemVerilog randomization for a fixed sequence of values

I need to randomize addr such that addr is 'h0 three times followed by addr as 'hf for two times. The values of addr should be in the sequence even if it is used with randomization. I tried using a <...
nick_pick's user avatar
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1 answer
327 views

What is the setup/hold time of the RMII receive interface of the TI DP83630 phy chip?

I'm interfacing the TI DP83630 phy chip to FPGA over RMII interface and need to write the timing constraints. I'm having difficulties interpreting the receive interface setup and hold time from the ...
anchi_anich's user avatar
3 votes
1 answer
392 views

SDC (Synopsys Design Constraints) Timing Exception for Latch Before Launch - FPGA

I am acquiring data from an ADC whose serial output makes the first bit available immediately after completion of a conversion. Then, the FPGA sends clock-pulses to the ADC to shift-out the remaining ...
HypeInst's user avatar
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1 vote
1 answer
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FPGA Timing Constraints

I am fairly new to FPGA design and I am working on a project where the FPGA is the SPI Slave. Are there supposed to be constraints on the Master Clock input signal/ MOSI / Chip select? What is the ...
Apu-JhoNsoN's user avatar
1 vote
1 answer
948 views

Passing input on one pin of FPGA straight out to another output pin for monitoring

I need to monitor a signal as it is going into the FPGA, tracking down a potential noisy input or slow rising signal issue. I want to use an external oscilloscope to see what the FPGA sees (as ...
jrive's user avatar
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1 vote
1 answer
2k views

Clock constraints for SDC file

I found several related answers to my question but none of them seem to clarify my case. I followed this answer and this one, but still getting warnings and when synth/impl. Here's the conceptual ...
Nazar's user avatar
  • 3,192
0 votes
1 answer
238 views

Intel FPGA: applying timing constraints

I have a data signal, select and clock signal which I am sending from the FPGA to another chip and I need to constrain them so I don't violate setup/hold time etc. I have tried to write and SDC file, ...
Tom Berge's user avatar
1 vote
2 answers
1k views

Constrain plane clearance from annular ring in Altium

I need to constrain a plane from shorting to the annular rings of a number of vias. The dialog found at ...
Joel's user avatar
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5 votes
1 answer
698 views

How to estimate timing contraints for FPGAs?

I try to find out how to specify the timings restrictions in FPGA designs correctly (in .sdc/.xdc files). I know what setup and hold times mean. However: How do I find out, what timing constraints my ...
SDwarfs's user avatar
  • 680
2 votes
2 answers
2k views

SDC constraints for source clock and derived clock

There are two clocks in the system, clk2 is derived from clk1 with a 180-degree phase shift. There is 1-bit data from clk1 to clk2. I know this is a kind of asynchronous scenario and the traditional ...
Ross's user avatar
  • 570
3 votes
1 answer
2k views

Vivado : constraints setup for SPI interface with common clock

I have been using Vivado 2018 for a system level design and am having trouble with a SPI interface programming. A block diagram of my system is shown below. The Artix-7 FPGA (on the motherboard) ...
CanisMajoris's user avatar
1 vote
2 answers
2k views

Altium Unrouted Net in Fill

I am trying to use vias on a fill to connect copper in Altium, but I keep getting unrouted net constraint errors. I have the following: The red square and blue rectangle (which extends fully ...
Billy Kalfus's user avatar
  • 1,041
3 votes
2 answers
460 views

FPGA automatic pipelining?

I have a synchronous datapath in my design that fails negative slack timing check, and I could most likely fix it by putting extra pipeline registers between datapath blocks by changing RTL sources. ...
Alexei's user avatar
  • 75
0 votes
1 answer
5k views

Writing SDC constraints for asynchronous clocks

I am new to SDC constraints, in synchronous clock definition say A and B are synchronous with each other, then we can define create_clock on A port (input) and <...
Krishh's user avatar
  • 11
-2 votes
1 answer
144 views

Is it possible to integrate all passive components? [closed]

Looking at a Circuit Board from a recent consumer product, I still see many discrete components (diodes, resistors, capacitors, amplifiers), which occupy space and have to be soldered into the board. ...
Real's user avatar
  • 143
3 votes
1 answer
413 views

LTSpice constraints on plots

A have a circuit for which I have parameterized some of its resistors with the .STEP command. Consequently, I have many different graphs when I simulate the circuit. I would like to know if it was ...
Dory's user avatar
  • 97
0 votes
1 answer
82 views

Lower Power Inductive Heating Circuit Design Questions

I'm trying to design a very low power (<=10W) inductive heating circuit that will heat the work material to 40-50degC. I've seen plenty of Royer Oscillator circuits online (see here: http://www....
athedcha's user avatar
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1 vote
2 answers
1k views

How to get a default UCF file of Xilinx Virtex-5 XC5VLX110?

How to get a default UCF file of the Xilinx Virtex-5 XC5VLX110? It doesn't seem to be anyhere. If I have to make it by myself, would you let me know how to ...
Carter's user avatar
  • 619
3 votes
1 answer
1k views

How to specify a minimum clock to output time in output timing constrain?

In design, an external clock pin triggers a flip-flop, where the output goes to an external data pin. Using Xilinx ISE, how can I specify a timing constraint, so the output should be held for some ...
EquipDev's user avatar
  • 579
2 votes
2 answers
3k views

SDC constraints for two flop sychronizer

I have doubt, What should be proper SDC constraint for CDC module, i.e., two flop synchronizer. between "dat driving by aclk to <...
Prakash Darji's user avatar
4 votes
0 answers
1k views

Timing constraints for DDR output multiplexer

Consider the following circuit, which multiplexes the d0 and d1 inputs to the y output in ...
mkrieger1's user avatar
  • 143
1 vote
0 answers
872 views

How to specify timing constraint for two paths to have a equal delay in Vivado

I am trying to sample an asynchronous signal in multiple clock-domains. I do not care too much about the absolute delay from the source of the async signal to the sampling FF's, but I want to ...
burnpanck's user avatar
  • 133
1 vote
1 answer
218 views

Constraint relative arrival time for a group of signals

Imagine a situation where the absolut delay of a group of signals doesn't matter, but it must be ensured each signal of the group has roughly the same delay until it reaches a certain point, say a FF. ...
andrsmllr's user avatar
  • 883
2 votes
1 answer
724 views

Multicycle : Is it possible?

I've to constraints an Lattice Semiconductor FPGA and I've some doubts about the multicycle constraint described here. I've the following RTL : Basically it is a counter that is driven by a rising ...
haster8558's user avatar
3 votes
1 answer
1k views

Setup and hold time violation constraints for Xilinx Fifo generator

I have a problem concerning the Xilinx Fifo generator and timing contraints described in the fifo manual. I am using the fifo generator version 9.2 (manual ) to generate a fifo. I would like to ...
Simone's user avatar
  • 31
2 votes
1 answer
1k views

BlockRAM location constraints (Xilinx)

I have a VHDL module in which several block RAMs are inferred. Now I would like to place these block RAMs into a certain region of my FPGA (close to some IO pins). How do I do this using Xilinx ...
andrsmllr's user avatar
  • 883
4 votes
1 answer
2k views

Understanding timing constraints

I don't want an introductory text on timing constraints, nor an application note, an user manual, a webinar. I read them all, already, many times. The concept behind timing constraints is very easy. ...
Giancarlo Sportelli's user avatar
1 vote
2 answers
4k views

Setup and hold time

Of the setup and hold timing constraints which are to be met to get a stable output, which one is critical in estimating the maximum clock frequency of a circuit?
titan's user avatar
  • 137
3 votes
2 answers
3k views

Clock domain crossing timing constraints for Altera

I have a slight problem with my clock domain crossing timing constraints. I have two clock groups set_clock_groups -asynchronous -group {clk_A} -group {clk_B} ...
AxelOmega's user avatar
  • 131
4 votes
1 answer
1k views

How do you constrain input delay for a multidimenionsal input vector?

I am defining SDC input constraints for synthesis of a small module that is part of a larger ASIC design. I plan to run the module through synthesis using Synopsys tools. A few of the inputs to this ...
Matt B.'s user avatar
  • 43
2 votes
1 answer
643 views

Rise/fall time constrains for ADC?

Does the sampling clock rise/fall times for ADCs matter, or they can be virtually 0 seconds? Can they be slow? In particular, I could not find anything about rise/fall time constrains for AD9235. ...
Nazar's user avatar
  • 3,192
1 vote
1 answer
2k views

What is the use of OFFSET IN/OUT constraint for FPGA design when using register in IOB?

The following is asked in the context of Xilinx FPGAs (my experience), but may also apply to similar technologies offered by other vendors. Background: When writing constraints for FPGA I/O, there ...
Josh's user avatar
  • 368
10 votes
1 answer
7k views

ASIC timing constraints via SDC: How to correctly specify a multiplexed clock?

Introduction Having found multiple, sometimes conflicting or incomplete information on the internet and in some training classes about how to create timing constraints in SDC format correctly, I'd ...
FriendFX's user avatar
  • 366
6 votes
1 answer
10k views

ASIC timing constraints via SDC: How to correctly specify a ripple-divided clock?

Introduction Having found multiple, sometimes conflicting or incomplete information on the internet and in some training classes about how to create timing constraints in SDC format correctly, I'd ...
FriendFX's user avatar
  • 366
4 votes
3 answers
10k views

Fix Conflicting IO Standards

I am using the Basys 2 Spartan-3E FPGA board with Xilinx. I need the pmod i/o to be at 1.8v so I am using LVCMOS18 IOSTANDARD. You can find all of the IOSTANDARD's available for Spartan-3E in this ...
MLM's user avatar
  • 858
3 votes
1 answer
6k views

Does it always make sense to constrain an I/O port?

I am following an Altera online course on their timing analyzer software called TimeQuest. In it, their recommend that, at the very least, all clock and I/O ports be constrained. In my FPGA design, I ...
Randomblue's user avatar
  • 11.1k
6 votes
1 answer
2k views

Discrepancy between post-Place-and-Route static timing analysis and ISIM simulation results

Overview I'm implementing a simple Harvard-style CPU using Xilinx ISE version 14.1. I'm using settings compatible with a Digilent Nexys3 board, but for the time being the entire project is performed ...
drxzcl's user avatar
  • 3,775