Newest 'constraints' Questions

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SDC constraint inside Xilinx ISE

Inside ISE timing constraint editor window, which following sub-section shall I use set_clock_group to solve the STA setup timing violation path #1 due to cross-clock signal ?

asked Aug 16 at 7:43

kevin998x

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How to correctly constrain a clock network with lots of mux branches?

Let me simplify a common clock network structure used in my company: Firstly, there're multiple true clock sources (PLLs, external input, or RC OSCs). Right at the beginning when these sources are &...

clock vlsi timing-analysis constraints sdc

asked Aug 13 at 2:57

Light

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Unable to constrain HPS peripheral pins on intel agilex fpga dev kit

I'm having trouble getting the Hard Processor System (HPS, the embedded hard processor of the agilex fpga series) to work properly on the Intel Agilex Dev kit version 3. The issue says that that there ...

intel-fpga constraints

asked Jun 3 at 11:34

Doralitze

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SystemVerilog randomization for a fixed sequence of values

I need to randomize addr such that addr is 'h0 three times followed by addr as 'hf for two times. The values of addr should be in the sequence even if it is used with randomization. I tried using a <...

system-verilog constraints

asked May 15 at 19:29

nick_pick

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56 views

What is the setup/hold time of the RMII receive interface of the TI DP83630 phy chip?

I'm interfacing the TI DP83630 phy chip to FPGA over RMII interface and need to write the timing constraints. I'm having difficulties interpreting the receive interface setup and hold time from the ...

fpga timing constraints setup rmii

asked Apr 20 at 14:31

anchi_anich

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Lattice Diamond assign unconnected poin

I used to work with the Lattice IceCube IDE where I just constrained all pins to the corresponding signal not matter whether they were actually used in the design or not. No I have to create a new ...

fpga lattice constraints

asked Apr 13 at 8:21

po.pe

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98 views

SDC (Synopsys Design Constraints) Timing Exception for Latch Before Launch - FPGA

I am acquiring data from an ADC whose serial output makes the first bit available immediately after completion of a conversion. Then, the FPGA sends clock-pulses to the ADC to shift-out the remaining ...

fpga adc timing timing-analysis constraints

asked Mar 12 at 1:45

HypeInst

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160 views

FPGA Timing Constraints

I am fairly new to FPGA design and I am working on a project where the FPGA is the SPI Slave. Are there supposed to be constraints on the Master Clock input signal/ MOSI / Chip select? What is the ...

fpga timing constraints

asked Feb 18 at 22:21

Apu-JhoNsoN

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Passing input on one pin of FPGA straight out to another output pin for monitoring

I need to monitor a signal as it is going into the FPGA, tracking down a potential noisy input or slow rising signal issue. I want to use an external oscilloscope to see what the FPGA sees (as ...

vivado timing-analysis constraints artix-series-fpga

asked Oct 28 '20 at 15:07

jrive

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Clock constraints for SDC file

I found several related answers to my question but none of them seem to clarify my case. I followed this answer and this one, but still getting warnings and when synth/impl. Here's the conceptual ...

timing-analysis constraints sdc microsemi-fpga

asked Sep 27 '19 at 16:32

Nazar

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119 views

Intel FPGA: applying timing constraints

I have a data signal, select and clock signal which I am sending from the FPGA to another chip and I need to constrain them so I don't violate setup/hold time etc. I have tried to write and SDC file, ...

fpga timing intel constraints sdc

asked Jul 16 '19 at 12:15

Tom Berge

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882 views

Constrain plane clearance from annular ring in Altium

I need to constrain a plane from shorting to the annular rings of a number of vias. The dialog found at ...

altium via clearance constraints

asked Apr 25 '19 at 15:32

Joel

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4

votes

1answer

238 views

How to estimate timing contraints for FPGAs?

I try to find out how to specify the timings restrictions in FPGA designs correctly (in .sdc/.xdc files). I know what setup and hold times mean. However: How do I find out, what timing constraints my ...

fpga timing-analysis constraints sdc xdc

asked Jan 16 '19 at 15:17

SDwarfs

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SDC constraints for source clock and derived clock

There are two clocks in the system, clk2 is derived from clk1 with a 180-degree phase shift. There is 1-bit data from clk1 to clk2. I know this is a kind of asynchronous scenario and the traditional ...

synthesis vlsi constraints cdc sdc

asked Dec 18 '18 at 3:00

Ross

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votes

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Vivado : constraints setup for SPI interface with common clock

I have been using Vivado 2018 for a system level design and am having trouble with a SPI interface programming. A block diagram of my system is shown below. The Artix-7 FPGA (on the motherboard) ...

fpga spi vivado constraints artix-series-fpga

asked Nov 4 '18 at 3:26

CanisMajoris

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Altium Unrouted Net in Fill

I am trying to use vias on a fill to connect copper in Altium, but I keep getting unrouted net constraint errors. I have the following: The red square and blue rectangle (which extends fully ...

pcb altium constraints

asked Mar 29 '18 at 22:30

Billy Kalfus

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votes

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258 views

FPGA automatic pipelining?

I have a synchronous datapath in my design that fails negative slack timing check, and I could most likely fix it by putting extra pipeline registers between datapath blocks by changing RTL sources. ...

fpga constraints

asked Nov 26 '17 at 5:12

Alexei

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3k views

Writing SDC constraints for asynchronous clocks

I am new to SDC constraints, in synchronous clock definition say A and B are synchronous with each other, then we can define create_clock on A port (input) and <...

timing constraints sdc

asked Oct 23 '17 at 9:45

Krishh

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133 views

Is it possible to integrate all passive components? [closed]

Looking at a Circuit Board from a recent consumer product, I still see many discrete components (diodes, resistors, capacitors, amplifiers), which occupy space and have to be soldered into the board. ...

pcb constraints psoc fpaa

asked Jul 8 '16 at 16:28

Real

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313 views

LTSpice constraints on plots

A have a circuit for which I have parameterized some of its resistors with the .STEP command. Consequently, I have many different graphs when I simulate the circuit. I would like to know if it was ...

simulation ltspice constraints

asked May 7 '16 at 23:46

Dory

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70 views

Lower Power Inductive Heating Circuit Design Questions

I'm trying to design a very low power (<=10W) inductive heating circuit that will heat the work material to 40-50degC. I've seen plenty of Royer Oscillator circuits online (see here: http://www....

design temperature low-power constraints

asked May 4 '16 at 1:17

athedcha

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How to get a default UCF file of Xilinx Virtex-5 XC5VLX110?

How to get a default UCF file of the Xilinx Virtex-5 XC5VLX110? It doesn't seem to be anyhere. If I have to make it by myself, would you let me know how to ...

fpga xilinx ise constraints

asked Apr 22 '16 at 5:58

Carter

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3

votes

1answer

1k views

How to specify a minimum clock to output time in output timing constrain?

In design, an external clock pin triggers a flip-flop, where the output goes to an external data pin. Using Xilinx ISE, how can I specify a timing constraint, so the output should be held for some ...

fpga xilinx synthesis constraints

asked Mar 30 '16 at 12:49

EquipDev

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SDC constraints for two flop sychronizer

I have doubt, What should be proper SDC constraint for CDC module, i.e., two flop synchronizer. between "dat driving by aclk to <...

synthesis vlsi timing-analysis constraints cdc

asked Mar 18 '16 at 5:01

Prakash Darji

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Timing constraints for DDR output multiplexer

Consider the following circuit, which multiplexes the d0 and d1 inputs to the y output in ...

cadence timing-analysis ddr constraints

asked Mar 3 '16 at 12:31

mkrieger1

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767 views

How to specify timing constraint for two paths to have a equal delay in Vivado

I am trying to sample an asynchronous signal in multiple clock-domains. I do not care too much about the absolute delay from the source of the async signal to the sampling FF's, but I want to ...

xilinx vivado timing-analysis constraints

asked Dec 6 '15 at 15:35

burnpanck

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169 views

Constraint relative arrival time for a group of signals

Imagine a situation where the absolut delay of a group of signals doesn't matter, but it must be ensured each signal of the group has roughly the same delay until it reaches a certain point, say a FF. ...

fpga vhdl xilinx constraints ucf

asked Nov 4 '15 at 13:49

andrsmllr

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votes

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596 views

Multicycle : Is it possible?

I've to constraints an Lattice Semiconductor FPGA and I've some doubts about the multicycle constraint described here. I've the following RTL : Basically it is a counter that is driven by a rising ...

fpga vhdl constraints timing-analysis

asked Jun 4 '15 at 8:20

haster8558

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votes

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Setup and hold time violation constraints for Xilinx Fifo generator

I have a problem concerning the Xilinx Fifo generator and timing contraints described in the fifo manual. I am using the fifo generator version 9.2 (manual ) to generate a fifo. I would like to ...

fpga xilinx constraints fifo

asked Feb 11 '15 at 10:30

Simone

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votes

1answer

820 views

BlockRAM location constraints (Xilinx)

I have a VHDL module in which several block RAMs are inferred. Now I would like to place these block RAMs into a certain region of my FPGA (close to some IO pins). How do I do this using Xilinx ...

fpga xilinx constraints

asked Oct 23 '14 at 15:25

andrsmllr

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4

votes

1answer

1k views

Understanding timing constraints

I don't want an introductory text on timing constraints, nor an application note, an user manual, a webinar. I read them all, already, many times. The concept behind timing constraints is very easy. ...

fpga vhdl serial constraints sdc

asked Sep 4 '14 at 21:32

Giancarlo Sportelli

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Setup and hold time

Of the setup and hold timing constraints which are to be met to get a stable output, which one is critical in estimating the maximum clock frequency of a circuit?

timing constraints setup

asked Aug 5 '14 at 10:02

titan

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votes

2answers

3k views

Clock domain crossing timing constraints for Altera

I have a slight problem with my clock domain crossing timing constraints. I have two clock groups set_clock_groups -asynchronous -group {clk_A} -group {clk_B} ...

fpga intel-fpga timing-analysis constraints cdc

asked Jul 23 '14 at 17:40

AxelOmega

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How do you constrain input delay for a multidimenionsal input vector?

I am defining SDC input constraints for synthesis of a small module that is part of a larger ASIC design. I plan to run the module through synthesis using Synopsys tools. A few of the inputs to this ...

synthesis asic chip-design constraints sdc

asked Jul 2 '14 at 0:33

Matt B.

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votes

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448 views

Rise/fall time constrains for ADC?

Does the sampling clock rise/fall times for ADCs matter, or they can be virtually 0 seconds? Can they be slow? In particular, I could not find anything about rise/fall time constrains for AD9235. ...

adc rise-time constraints

asked Jun 16 '14 at 22:04

Nazar

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What is the use of OFFSET IN/OUT constraint for FPGA design when using register in IOB?

The following is asked in the context of Xilinx FPGAs (my experience), but may also apply to similar technologies offered by other vendors. Background: When writing constraints for FPGA I/O, there ...

fpga xilinx constraints

asked Jan 16 '14 at 17:10

Josh

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ASIC timing constraints via SDC: How to correctly specify a multiplexed clock?

Introduction Having found multiple, sometimes conflicting or incomplete information on the internet and in some training classes about how to create timing constraints in SDC format correctly, I'd ...

clock timing constraints sdc

asked Sep 26 '13 at 4:13

FriendFX

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votes

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ASIC timing constraints via SDC: How to correctly specify a ripple-divided clock?

Introduction Having found multiple, sometimes conflicting or incomplete information on the internet and in some training classes about how to create timing constraints in SDC format correctly, I'd ...

clock timing constraints sdc

asked Sep 26 '13 at 2:49

FriendFX

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3answers

8k views

Fix Conflicting IO Standards

I am using the Basys 2 Spartan-3E FPGA board with Xilinx. I need the pmod i/o to be at 1.8v so I am using LVCMOS18 IOSTANDARD. You can find all of the IOSTANDARD's available for Spartan-3E in this ...

fpga xilinx spartan constraints

asked May 22 '13 at 21:48

MLM

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Does it always make sense to constrain an I/O port?

I am following an Altera online course on their timing analyzer software called TimeQuest. In it, their recommend that, at the very least, all clock and I/O ports be constrained. In my FPGA design, I ...

fpga adc clock intel-fpga constraints

asked Sep 11 '12 at 20:44

Randomblue

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6

votes

1answer

2k views

Discrepancy between post-Place-and-Route static timing analysis and ISIM simulation results

Overview I'm implementing a simple Harvard-style CPU using Xilinx ISE version 14.1. I'm using settings compatible with a Digilent Nexys3 board, but for the time being the entire project is performed ...

fpga simulation timing spartan constraints

asked Jul 19 '12 at 17:26

drxzcl

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votes

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On the use of "BLOCK INTERCLOCKDOMAIN PATHS"

I based an FPGA design on Lattice reference code that, in the timing constraints .lpf file, specifies: ...

fpga verilog constraints

asked Jul 3 '12 at 14:25

shuckc

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votes

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1k views

constraint error and illegal load problem in Virtex-2

I am trying to test a very simple deskew circuit on a virtex-2pro FPGA (xc2vp30-fg676-5). I use xilinx ISE and the deskew IP (two DCMs with a DDR flop) provided by core generator. I also try to ...

fpga constraints

asked Jun 21 '12 at 18:58

drdot

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9

votes

3answers

3k views

Op amp analysis: when are the "negative feedback rules" applicable?

When we build op amp circuits that use negative feedback, like so: ... we can analyze the circuit very easily, by assuming that $$v^- = v^+$$ due to negative feedback (when also assuming the op amp ...

operational-amplifier negative feedback constraints

asked Jun 3 '12 at 14:47

exscape

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votes

1answer

2k views

Analog Video PCB Layout

What special considerations and/or constraints are typically applied when routing analog video signals on a PCB (e.g. VGA, NTSC, etc). I'm thinking try and keep them routed on a single layer (i.e. at ...

pcb analog layout video constraints

asked Feb 22 '12 at 16:01

vicatcu

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11

votes

2answers

17k views

EAGLE Matched Length Pairs / Groups

What facilities does EAGLE CAD have for helping to do layout with matched length groups and differential pairs? Can you apply such a constraint in the auto-router? As a follow-on to this, what (other) ...

layout eagle constraints

asked Feb 17 '12 at 14:54

vicatcu

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