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Questions tagged [constraints]

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6
votes
1answer
9k views

ASIC timing constraints via SDC: How to correctly specify a ripple-divided clock?

Introduction Having found multiple, sometimes conflicting or incomplete information on the internet and in some training classes about how to create timing constraints in SDC format correctly, I'd ...
9
votes
3answers
3k views

Op amp analysis: when are the “negative feedback rules” applicable?

When we build op amp circuits that use negative feedback, like so: ... we can analyze the circuit very easily, by assuming that $$v^- = v^+$$ due to negative feedback (when also assuming the op amp ...
2
votes
1answer
675 views

BlockRAM location constraints (Xilinx)

I have a VHDL module in which several block RAMs are inferred. Now I would like to place these block RAMs into a certain region of my FPGA (close to some IO pins). How do I do this using Xilinx ...
10
votes
2answers
5k views

ASIC timing constraints via SDC: How to correctly specify a multiplexed clock?

Introduction Having found multiple, sometimes conflicting or incomplete information on the internet and in some training classes about how to create timing constraints in SDC format correctly, I'd ...
10
votes
2answers
15k views

EAGLE Matched Length Pairs / Groups

What facilities does EAGLE CAD have for helping to do layout with matched length groups and differential pairs? Can you apply such a constraint in the auto-router? As a follow-on to this, what (other) ...
3
votes
2answers
2k views

Clock domain crossing timing constraints for Altera

I have a slight problem with my clock domain crossing timing constraints. I have two clock groups set_clock_groups -asynchronous -group {clk_A} -group {clk_B} ...