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Questions tagged [constraints]

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Constrain plane clearance from annular ring in Altium

I need to constrain a plane from shorting to the annular rings of a number of vias. The dialog found at ...
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0answers
600 views

How to specify a minimum clock to output time in output timing constrain?

In design, an external clock pin triggers a flip-flop, where the output goes to an external data pin. Using Xilinx ISE, how can I specify a timing constraint, so the output should be held for some ...
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540 views

Timing constraints for DDR output multiplexer

Consider the following circuit, which multiplexes the d0 and d1 inputs to the y output in ...
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0answers
691 views

How to specify timing constraint for two paths to have a equal delay in Vivado

I am trying to sample an asynchronous signal in multiple clock-domains. I do not care too much about the absolute delay from the source of the async signal to the sampling FF's, but I want to ...
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250 views

How to fix 'timing constraints not met' error caused by Xilinx Cordic IP?

I made a window function generator IP in Xilinx Vivado. It works well in the simulation. When I tried to implement for Zedboard, it gives a timing error. The error is caused by Cordic IP used for ...