Questions tagged [copper-pour]

The term "copper pour" refers to an area on a printed circuit board filled with copper

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Should I do a ground copper pour on a 4-layer PCB in order to shorten return current paths?

I'm designing a 4-layer PCB with the SIGNAL/GND/POWER/SIGNAL stackup. Since I have a dedicated ground plane layer, I've decided not to pour ground connected copper on the top and bottom signal layers, ...
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How to make a circular polygon pour in Altium?

I have a circular PCB for an LED circuit and I want to cover the free space with polygon pour to enable larger current to pass thru the circuit. The Polygon pour option only permits polygon (with ...
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General approach to routing with copper fill

I don't have much experience with designing PCBs and when doing so I had to make a surprising number of decisions concerning the copper fill. Assume a simple analog or digital circuit, 2-layer PCB. No ...
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Multiple copper pours in ground plane of a 2 layer board

I am an amateur PCB designer.Trying to design my first PCB. I am using a two-layered power supply board. I am using a 72V battery pack as the input to get +15V,+5V, and -15V as outputs. The pic shows ...
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Should one pour AC-Neutral copper on bottom layer when routing AC

I am designing a PCB where there will be AC mains routing/tracks. What I want to know, is if it is better -for noise reduction- to take one of the AC outputs (Neutral) and pour it on the bottom side ...
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Polygon pour on internal signal layer ALTIUM

I am working on a six layer PCB, the layers are Top layer, layer 1...layer4, Bottom layer. I am trying to create a polygon pour on any internal layers (for example layer 1). However when I try to pour ...
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Removing high impedance ground pours parallel to signal traces in Altium

whenever I route parallel traces on Altium, I get those narrow ground pours between my signal traces when I fill my ground planes. A collegue told me: since these pours are narrow and thus high ...
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Avoiding ground noise in analog circuit pcb design

Below single layer PCB is a constant current sink circuit (electronic load), it's pure analog supplied with ±12 V and consumes very low current (~50 mA) except the transistor control part (which ...
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4 layers PCB mixed signal GND review

I'm a beginner at PCB design. We've subcontracted routing for a PCB; it contains mixed analog and digital signals and it's a 4-layer PCB with an inner split GND plane (Signal - GND - VCC - Signal). ...
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What to do when pouring polygon if you didn't use a GND?

I designed a test board for connectors and it doesn't have any ground net. I am new at designing pcbs and I always used ground polygon pour. I don't know what to do without gnd polygon. What should I ...
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Using a via fence without a top layer ground pour

I'm designing a 4-layer 6GHz RF PCB. The top layer is a signal layer and has the RF microstrip traces and the 2nd layer is an unbroken ground plane. I'm leaning against filling the remainder of the ...
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What is the actual purpose of having a copper foil layer in PCB?

Out of several layers that make up a PCB, one of them is a layer of copper foil (see image below), What purpose does this layer serve to the PCB? Also, some PCBs have just one copper foil layer ...
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Voltage regulator protection diode - connected by pours?

I've got a voltage regulator in a circuit, along with its recommended protection diode: On my PCB, I'm using large copper pours for the Vin (Pin 1) and Vout (Pin 3) connections, as these are used ...
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Is it ok to put GND and VDD pours below IC (AS7265x)

I am designing a PCB to use with the AS7265x sensors. The datasheet states, on page 51: In order to prevent interference, avoid trace routing feedthroughs with exposure directly under the AS7265x ...
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1 answer
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The Thermal relief consideration for TVS diode (for ESD protection)

I am designing a print which has some mircofit connectors, I have placed TVS very close to the connectors on the print and the ground pad connected with a GND polygon directly, this polyon connects ...
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Is this polygon pour, how much current can it carry?

On my attached picture, I draw battery pins, (red square) component that want to current, (blue square, a component want to about 4-6 ampere) and way of current (black line). I have a some questions. ...
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7 answers
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Will copper pour help on my single-layer PCB?

I have a PCB which contains one 20x4 LCD, eighteen 12x12 mm push buttons, and three LEDs. This board is connected to an Arduino Mega through a 30 cm long ribbon cable. Now during testing, I ...
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PCB Copper pour without making Schematic

I have a problem with ground Copper pour for the PCB. I'm using EasyEDA.com to designing my PCBs. But because i usually make my PCB directly without Drawing its schematic so i can't make the ground ...
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7 votes
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PCB layout - ground plane clearance around and under a ceramic resonator

We are using Murata's 4MHz ceramic resonator (CSTCR4M00G53-R0) in one of our designs and request help in PCB layout design around the ceramic resonator. The below Murata's FAQs page suggests not to ...
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VCC on surface or inner layer on 4-layer board?

If I can get away with, I will use 6-layer design where I get two dedicated GND planes, L2 and L5, which creates strong reference plane for traces on L1, L3 and L6. When you're working with 4 layers,...
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What is the proper placement of VCC and GND copper pours in 4-layer PCB?

This is my first PCB design and I'm struggling with proper copper pour usage. I would like to copper pour VCC and GND. From what I understand, a copper pour will net multilayer plated through holes ...
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Problem Placing Polygon Pour on Board Altium 17.1

I'm laying out a two-layer PCB. I've routed all the signals, including power and ground. I like to add a ground plane on both layers by placing polygon pours. I'm having trouble getting Altium to ...
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What are these gaps in PCB polygon pours near vias of the same net?

When adding polygon pours to a power layer on my PCB in Altium Designer (v17), I'm getting weird clearance gaps near vias. The poly and vias are connected to the same net. I'm new to Altium, so I'm ...
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How do I know where to put stitching vias?

I'm working on a PCB that allows me to attach a TSSOP IO expander to a breadboard more easily for experimenting. I asked a question regarding the configuration of decoupling capacitors for an IC with ...
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9 votes
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Why are ground pours isolated from each other on the top layer?

I am reading the application note from TI about the LM3409 evaluation board. In the board layout (Figure 3) the bottom layer is a single GND pour. But top layer has also some copper pours which end ...
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908 views

Are multiple groundplanes a good idea on a 4-layer pcb?

I'm working on a design of a 4-layer PCB. The stackup is like this: Top: signal Inner 1: power distribution traces and copper fill (VCC) in some areas Inner 2: signal Bottom: ground plane There ...
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2 answers
526 views

reason to have entire Cu layer as GND connected through via (KiCad)

This is the first time I am designing a PCB and I was looking at example PCBs drawn in KiCad (the image below is my first PCB, to remove any sources of confusion). I noticed that oftentimes, when ...
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706 views

Altium through-hole type, "slot" vs "rectangle", effect on copper pour

I am drawing a board which will fit in an enclosure with batteries. The battery terminal tabs should come up through slots in the PCB, and solder to a pad around the slot perimeter. I created a new ...
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PCB layer stack up practices [duplicate]

Sorry in advance for the newbie question, but I can't seem to find a good answer. Recently, I've gotten into printed circuit boards and it is all still fairly new. I'm working towards creating a 4 ...
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433 views

2 Layer PCB Copper Pour on the bottom layer

I am an amateur PCB designer. Trying to design my first PCB. It's a two layer board with ESP8266 module. I have read lot about ground plane and copper pour at the bottom layer. I have tried to use all ...
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4 answers
2k views

Is a copper pour redundant on the top layer of a multilayer (>= 4) board with a ground plane?

In a multilayer board with a GND plane directly under the top layer, does adding a copper pour to the top layer give extra value in terms of reducing crosstalk and EMI? If all signal traces already ...
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Altium Polygon Pour Order Issues

I am using Altium Designer 14.1 and I do not know if it is an issue with this version or something else. The problem I am having is I have a solid copper pour covering the whole board. I want to put ...
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2 votes
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338 views

Flex circuit solid or hatch copper pour

I have a flex circuit board with 5 LEDs mounted on it. I have large copper areas attached to the LEDs for improved heat dissipation. I read here that "With a hatched plane, the moisture can exit the ...
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3 answers
957 views

Cannot change to front copper layer in KiCAD

I am learning to design PCB using KiCAD. I followed a tutorial on youtube. I got stuck at changing the layer of the PCB. From the video, the layers can be interchange by pressing page up (front ...
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920 views

Alitum: polygon pour with a fully included round hole

I need to draw a round hole on a polygon pour. I've followed this documentation (see video in "Subtracting Selected Polygon Pours" paragraph). It explains that you must first selected the reference ...
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Altium: Remove Small Sliver Openings in Hatched Pour

One of Altium's polygon pour modes is a hatched version, which allows the user to specify an individual track width and a grid size and it automatically generates a pour in a cross-hatch pattern. It ...
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EAGLE restrict area isolation [duplicate]

Hi, in my circuit I made ground plane and inside of it I need clear area without copper for anthena. So I have created polygon in tRestrict layer and used Ratsnest for reconection. It worked, but not ...
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2 votes
1 answer
577 views

How to separate ground pour from ground traces in Eagle?

I'm designing a board where I have ground pour at the component side. I'm using plenty of decoupling capacitors. The problem is that the ground pour "consumes" the ground traces like this: Is it Ok ...
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721 views

Are copper pours hidden by default in EAGLE?

I'm looking at the EAGLE board file from the Arduino wiki page, and I feel like I must be missing something - none of the ground pins of U1 appear to be connected to anything: As you can see, the GND ...
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Altium Designer PCB project Ground fill polygon cant connect to one of same net component pad

I'm finishing one of my pcb layout, in this case is a multilayer one. the trouble is that design rule checker find me 5 unconnected GND pads but the trouble is that this pads are close to a copper ...
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3 answers
1k views

Can this copper pour be an EMI problem?

I am looking at the following PCB (single layer). The checked red/blue is GND. Can this polygon give EMI problems in the sense that it acts as an antenna because it does not form a closed loop ? ...
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1 vote
1 answer
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Microcontroller and decoupling capacitors on the VDD layer

I have a microcontroller design that is implemented using a two layer PCB. All the components need to be placed on the bottom layer due to the fact that there is a display in the top layer. In short, ...
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4 answers
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Altium Designer, using signal layers as power planes

In cases when a 4-layer board is space limited, and there's a lot signal traces in the whole board, "power plane layers" is not very usefull to distribute power rails. Because it is used only to draw ...
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Coppers Pours for 4-Layer RF (433MHz) Board?

I've got a 4-layer prototype transmitter board built that is using a low-speed MCU (2 MHz). The critical RF sections are 50 ohm impedance matched to the board's characteristics. I eliminated the GND ...
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2 votes
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470 views

Why does copper pour cause impedance discontinuities?

Inspired by this question's accepted answer, I've been studying how PCB trace impedance can be affected by the trace's surroundings. However, something in the accepted answer is confusing me: ...
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Ground pour under ESP8266 12-E

I want to pour ground under a ESP8266 12-E just for thermal reasons but I don't know if this can affect it somehow or if it's safe to do. The PCB is all under 5V, it's only 2 layers and it would have ...
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970 views

Thickness of thermal relief on copper pour

I am working on designing a pcb that will have a copper pour. I have selected to use thermal reliefs to connect the pour to pads, but I am a little confused on the thickness. Should each spoke of the ...
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1 answer
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Will my square pad short if the pour isolation is too small?

How do I get the pour to isolate the pad and not the drill here? I'm assuming the square pad goes all the way through and will short my second layer (in teal). Am I correct? update: Confirmed! I put ...
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1 answer
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Adding multiple thermal relief spokes to a large pad in Mentor-PADS

Regarding Mentor PADS Layout software (v9.5)... I have a large rectangular pad (the tab on a power FET) which is surrounded by a large copper pour (for current and thermal capacity). When I pour the ...
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6 votes
5 answers
3k views

Why were hatched polygons pours used instead of solid pours in the past?

While reading [David L. Jones]'s PCB Design Tutorial, he mentions that hatched polygon pours are a thing of the past. Solid fills are preferred, hatched fills are basically a thing of the past. (...
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