Questions tagged [counter]

A digital circuit that literally "counts" - it progresses through a sequence of states that are representative of some value. It need not count in a natural progression i.e. 1,2,3,4,5 etc. to be considered a counter (i.e. you can have different count sequences) each count value need not be of significance to other circuits (i.e. sometime it's sufficient that the counter counts to some value and then stops). Examples are Gray code, up/down counter.

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492 views

What is a recycling counting sequence?

Is there any difference between the name "recycling count sequence" and "count sequence"? I have a digital system book saying that a MOD-12 counter has a recycling count sequence of 0001 through 1100....
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Propagation delay in asynchronous counter

Are the ripple counters useful in real life? I know, for example, if we set an up counter with 3 FFs, CBA. Followings are the block and the waveform diagram: After the count 001, it will appear 000 (...
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Design Counter With Arbitrary Sequence Using Load

I'm trying to design an asynchronous counter with JK flip- flops, with an arbitrary sequence. The sequence is: 0, 1, 2, 3, 4, 5, 2 ? I know how to solve this kind of problems, but in this case how ...
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Design of a counter that stays in each state for x clocks

Suppose we have an 8-bit counter out[7:0] It needs to stay in each count for specified number of clocks x, where x can be any integer or fractional factor of 512. My Approach: Use 10 bit counter ...
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How propagation delay of synchronous counter is less than asynchronous counter?

My question is very basic one, but thought of asking here to clarify. In asynchronous counter the output of Flip Flop is given as input to other Flip Flop as clock, where as in synchronous counter the ...
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Is there any simulation environment provided with TDC-GP1 counter frimwaire?

hello everybody I want to simulate an electronic circuit, I used TDC-GP1 (Time to Digital Converter) I searched in Proteus and in Pspice Cadness but didn't find this part in library, is there any ...
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FPGA Synchronized Digit Counter goes Asynchronous!

I'm trying to implement one digit counter from 0 to 9 using an FPGA board. The digit is incremented when the signal "pulse" is set. The "pulse" signal is set every fixed number N of clock cycles. The ...
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Character '0' used but not declared for type std_logic_vector??? (Algorithm state machine)

After adding the counter to my VHDL code am getting the following error: Error (10316): VHDL error at ASM.vhd(31): character ''0'' used but not declared for type "std_logic_vector" Thank you Code: <...
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Tick counter digital signal

I want to trigger a laser externally and I want to trigger it when a rotating small wind turbine blade passes a specific angle. I have a digital signal which tells me when the blade passes that angle. ...
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Mod 6 counter that counts 1-6 on a 7 segment display (FIXED) [closed]

I fixed the problem, thank you all for your help, I posted the entire circuit, for anyone in the future who has a similar problem. [![enter image description here][2]][2]
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Prime numbers direct counter [closed]

How can I design a prime numbers counter up to 63?I need to find a rule for the bits? I know how to usually design counters but this one seems kind of difficult since there are so many numbers
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IC for magnetic environments

I am working on a comparator circuit for converting a small AC signal to a digital (square) signal. The circuit is meant to be used in a strong magnetic environment, so the casing should not have ...
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Using a clock to increment a counter which drives a mux?

I am trying to program this functionality onto a Xilinx FPGA; however, when I program it to do this, I get no output. My situation is as follows: I have 12 bits of data (in parallel): the first 6 ...
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Counting number of push button press by external interrupt

It's a requirement that I should count the number of button press by external or any other interrupt. So when I use the external interrupt to increment the counter by 1, it sometimes is crease by 2 ...
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1answer
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truth table for D flip flop with control variables x and y

So I need to build a counter with D Flip-Flop and 2 control variables x and y. XY=00 --> 0-3-2-1-0; XY=01 --> 0-1-2-3-0; XY=10 --> 0-2-3-1-0; XY=11 --> 0-1-3-2-0. How should I make the truth table?...
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CPLD is (sometimes) not incrementing counter

I have this simple program running on the Altera EPM240 that’s sometimes not doing the counter increment. ...
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Building a 7 Segment clock using mains frequency

As the title says, I want to build a clock using the mains frequency (50Hz). I only want to use digital integrated circuits from the CD4xxx series or something similar. (no microcontroller or do-it-...
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Design using only D FF a counter that goes 0->2->1->5->7 [closed]

Have this as an exercise in my logic design textbook. I know how to do this with additional logic, but the challenge comes from only having D flip-flops available. I assume there are at least 3 of ...
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1answer
154 views

RFID (or other) - Proximity Detector

I am trying to detect how often 2 animals 'interact'. Say I have 4 cats, I am trying to work out how often each of the cats interact with each other. I have considered using RFID tags attached to ...
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3answers
615 views

A binary counter problem

How can I create a digital counter that counts from 000 to 111 and automatically starts reverse counting from 111 to 000. I have tried with simulation it works fine, but with actual ICs I am not ...
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1answer
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4 input counter with display

I have 4 switching sensors for all around detection, they output either 24V or 0V. I want a counter that will add 1 everytime one of the sensors detects something (sometimes 3 of them will detect ...
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Clock Frequency for 4 digit 7 segment display in VHDL

I am using basys 3 and VHDL to create a stopwatch and I need to do it for both the 7 segment display of the basys3 itself and for a external 4 digit 7 segment display. I am given the clock divider ...
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How can I see the current state and next state signal? [closed]

I was looking at this code: http://vhdlguru.blogspot.co.uk/2010/04/how-to-implement-state-machines-in-vhdl.html and I wanted to know how you would run the simulation in vivado, but then apart from ...
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The binary up counter works with function generator in simulation but doesnot work when manual switches are used?

ABOVE SIMULATION IS NOT WORKING ABOVE SIMLATION IS WORKING My simulation donot work if I manually turn switch on and off for clock even though I have used pull down resistors but when I use pulse ...
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Simple number counter - PIC16F877A microcontroller problem

I am trying to make a simple counter using pic16f877a. I want to count each time a push button is pressed, that is taking one press as one count, regardless of how long the button is pressed. The ...
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Design a 8 - 6 - 4 - 2 - 0 - 1 - 3 - 5 - 7 - 9… Counter

Design a counter: 12-10-8-6-4-2-0-1-3-5-7-9-11 using D Flip Flop. My first approach is designing a 8 - 6 - 4 - 2 - 0 - 1 - 3 - 5 - 7 - 9 - 8 - 6 ... counter and display them on 7segment LED. ...
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How can I output to one of 4 different outputs without using a demultiplexer?

I do not have a demultiplexer available, so I need a substitute. I have a TTL signal and I need to output the signal to output 1, then output 2, then output 3, then output 4 in sequence, meaning that ...
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Small doubt in asynchronous counter

I was trying to understand the ripple effect in asynchronous counter and I came across this figure:- In all the problems solved in my book, they consider the minimum clock period required for proper ...
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Pulse counting routine with sleep

I'm making a simple battery-powered project that measures water flow with a liquid flow meter and transmits the value with an nRF24L01+. The microcontroller I've chosen is a TI MSP430FR2110 (family ...
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Sit counter or pressure counter?

We have to count how many times a particular chair/seat has been "sat upon" - how would one go about this? Brute force approach suggests put together a pressure sensor to flip a digital counter. ...
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Signal decimator/down-sample with lowest propagation delay

I would like to frequency-divide a 10 MHz digital signal by a factor of 8 or 16, with the lowest possible propagation delay. I need a propagation delay that is at most 5-10 ns. The best solution I ...
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582 views

Propagation delay in asynchronous circuit

Consider the circuit shown below where delay of each flip flop is 10ns and delay of each AND gate is 5ns each. What is the total propagation delay ? My Attempt:- 1) Consider that initial state i.e ...
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Frequency of cascaded counter

Question: Consider one set of \$Mod-14\$ digital-counter having input clock frequncy \$19kHz\$.If another input clock frequency as first one is cascaded then final output clock frequency of the ...
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Counter in verilog

i want to make a counter that increases by the value of its inputs, but i did the testbench and the output is undetermined, xxxx. Can someone tell me if there is something wrong in this code? ...
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8-Bit Binary to BCD Decoding for Three 7-Segment Displays

I've created a circuit that uses both binary and BCD counters to convert an 8-bit binary number into three BCD numbers, which then feed into BCD to 7-segment decoder chips, and finally to common-anode ...
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Is this a ring counter ? What is its definition?

We can know the ring counter like :0000 -> 1000 -> 0100 -> 0010 -> 0001,it shifts the "1" bit. Here is my schematic,the same as the schematic from the internet,and because my d-flip flop is active ...
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1answer
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Propagation delay in case of synchronous counters

Consider 4 bit counter as shown below:- Here suppose we consider propagation delay of each flip flop =2ns and propagation delay of each AND gate is 3ns, then what will be the total propagation delay? ...
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1answer
671 views

Is there a way to change only one of the outputs of a D flip-flop?

I designed a schematic for a ring counter, but the last two flip-flops' simulation signals didn't shift. My D-flip flop is designed as set=1,then Q=0; reset=1,then Q=1; set=1=reset,then Q=1,when D=1 ...
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Output frequency of asynchronous and synchronous counter

I read that output frequency of asynchronous counter will be \$\frac{f_{in}}{2^n}\$ where \$n\$ is number of flip flops and \$f_{in}\$ is input frequency. In synchronous counter will the output ...
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Does the quartz crystal in the standard clock vibrate the same frequency as the sweep motion one? [closed]

In the standard quartz clocks/watches,the quartz crystal vibrates 32768 times per seconds(32768HZ),while this frequency is divided by an electronic counter(15 bit binary digital counter)to derive one ...
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Maximum frequency of the synchronous counter

Find the maximum clock frequency at which the counter in the figure below can be operated. Assume that the propagation delay through each flip flop and each AND gate is 10 ns. Also assume that the ...
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1answer
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Multisim 16 counter to 14 counter

Hello I was wondering if anyone can help me with this 16 counter in multisim. What do I add to limit it at E rather than F? Thank you
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How to connect the counter below to the counter above

I am designing a synchronous DOWN counter that is supposed to count down from 20 to 00. I tried many different ways but the logic combinations I tried are obviously wrong as I am getting very weird ...
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How to convert this into a down counter?

I have been learning counters and am able to design an asynchronous UP counter with JK flip flops in Multisim, however I am unable to convert it to an asynchronous DOWN counter. My UP counter counts ...
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Binary info to Decimal representation using circuitry

I'm tryign to make a counter (and by extension all the other things) using a series of flip-flop circuits, and a seven segment display. As I have it the digit increments through 0xF, which isn't ...
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Ripple counter, reset problem (J-K flip flop counter)

I am trying to simulate a decade counter using a ripple counter 4 bits and a NAND gate to reset the 4 J-K flip-flops when it reaches 10 (1010). The thing is it does not reset but goes to 4 (0100) due ...
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Designing a special counter using logic gates

I need to design a counter circuit that counts in 5-bit binary form between the numbers (0-31) by 5 using only logic gates without any programming. when the counter reaches 30 it must go as 3..8..13.. ...
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How to design a binary up down counter using D flip flop's and the 'up' or 'down' count will be controlled by another flip flop?

I have to design a 4bit Binary Up Down counter using D flip-flops . But here is the catch I cannot directly use a switch to control whether the counter will count up or down, I have to do that using ...

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