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Questions tagged [cpu]

The CPU, known as the Central Processing Unit, is known as the heart of the computer. It is responsible for carrying out the instructions of a computer program by performing the basic arithmetic, logical, control and input/output (I/O) operations specified by the instructions.

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How does a computer know when to “get” the output from the ALU?

Basically what the title says, I guess I've got some sort of misconception or somthing probably. The ALU can have, say, a ripple carry adder which doesn't produce its entire output all at the same ...
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Why is there a PLL in CPU?

I read that PLL are used in CPU to generate the clock, but I can't understand why. I don't really have any guess of why this is.
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What is the purpose of Delayed Branching? [closed]

I study solutions of control hazards in a processor. One method is delayed branching. To my understanding, specific number of instructions (depending on pipeline length) are always executed subsequent ...
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Renaming a special register

I noticed that RISC-V, like some other RISC architectures, by convention treats register 1 specially, using it as the link register, holding the return address for function calls. If most code ...
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1answer
76 views

Word length in a computer system

i am currently reading about memory system in computer architecture. I wanted to know, Is the word length the number of bits input to the ALU?
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1answer
117 views

Home-brew cpu ram

I’m trying to build a cpu out of ttl logic chips. I’ve just about got everything finished, however, I’m still working on the ram. I don’t have any suitable ram chips I can use, however, I do have a ...
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4answers
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What stops an assembly program from crashing the operating system? [closed]

First of all, I am a beginner, so if this question sounds silly, please point out the incorrect assumptions. From what I understand, the job of an operating system is to manage hardware and the ...
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1answer
39 views

Is qNaN easier than trapping on overflow?

According to James Demmel's article, "Faster Numerical Algorithms via Exception Handling", IEEE Trans. on Computers 43 (1994), 983-992, the way a floating-point processor handles overflow can be ...
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What prevents the construction of a CPU with all necessary memory represented in registers? [duplicate]

Modern CPUs employ a hierarchy of memory technologies. Registers, built into the chip have the lowest access times, but are expensive and volatile. Cache is a middle-man between RAM and registers to ...
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1answer
58 views

Cascade shift registers driven by single-cycle microcontroller

I'm trying to make a unit in which 4 digits can be updated in a small amount of time from a single-cycle microcontroller (preferably all digits updated within 5uS) My circuit is setup in the ...
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3answers
150 views

Getting CPU clock signal out of computer (as to measure externally) [closed]

I've been searching on the internet some clock generator module capable of reaching up to 1GHz, when I just realized that the machine I'm using to search has one CPU with its own 2.5-3.0 GHz clock... ...
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Co-Processing Across SBCs

Situation: Was thinking about co-processing as I played with the Adapteva Parallella, which has a quad-core CPU and a 16-core RISC-based co-processor. Question: It got me thinking -- can I achieve ...
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1answer
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How many external devices can be linked to a CPU with n address buses and m data buses?

(Hypothetical) Let's say there is a CPU with 8 address lines and 8 data lines. If each external device has 128 accessible registers, how many external devices can be linked? For 8 address lines, I ...
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3answers
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How big does ground need to be? Step down from 5v10a to 1.2V 50a, do I need a 50 amp ground?

I'm just a layman. I was just thinking about CPUs in computers. They run at about 1, 1.5 volts or there about, sometimes even lower. Desktop cpus can take 90 watts, some 120 watts. That's close to 100 ...
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1answer
39 views

SAP-2 ADD instruction possible in 4 T states?

I'm working through implementation of the SAP-2 CPU from Digital Computer Electronics, 3rd Edition. I'm having difficulty understanding how the arithmetic & logical instructions can be ...
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1answer
57 views

Why disable interrupt is time-consuming in multi-processor computer?

I have a book statement: Disabling interrupt is time-consuming in multi-processor system. I suspect that this is related to the hardware implementation of how interrupt is enabled/disabled. So ...
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1answer
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Pipelining speed calculations? [closed]

I'm having trouble finding a formula to calculate this.. The dynamic flow of our program contains 19% branching instructions. The processor uses delayed branching with one delay slot. Calculate how ...
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1answer
81 views

How to find CPU by needed parameters?

I trying to find a low-power processing unit with lowest price for some practical research. I trying to made a simple device with 1 SATA 3.0, 1 microSD and 1 USB 3.0 interfaces. Can someone advise ...
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2answers
67 views

Treating Multiple CPU Cores as One

I recently took an undergrad computer architecture course and had a question about using multiple cores after seeing how dense the field of research is. I am thinking about a general idea of how many ...
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3answers
2k views

Is it true that on a modern processor, parallelism is possible on a single core?

Final Edit: I just realized that when use the word "parallelism", it's almost parallelism==ILP, I originally thought even a single instruction could be divided into ...
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2answers
491 views

Is the speed of electrical signals always constant within a CPU? [closed]

Microprocessors rely on assumptions about how long it takes for electrical signals to propagate through combinational logic circuits. As far as I understand from reading "Modern processor design", ...
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2answers
122 views

Z80 RD and WR to RD/WR?

This may sound like a very stupid question. However, I am new to the Z80 stuff. I am planning on how to connect the Z80 control signals to a SRAM. But the Z80 has seperate RD and WR, while my SRAM has ...
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1answer
96 views

What is the composition of CPU chip

What are each of those components on the chip?
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1answer
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How does the computer's BIOS change the clock speed?

A computer's BIOS can change either the multiplier value or the (FSB) clock frequency to overclock or underclock a CPU. While overclocking by changing the multiplier value is easier and in more often ...
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3answers
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Micro programming and hard wiring

I have a question about the details of microprogramming and hard wiring in CPU architecture. In hardwiring, we write a code, the compiler translates it to the ISA, then the ISA is run in the hardware....
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2answers
354 views

How many LUTs are needed to implement a CPU? [closed]

I am looking to start my first FPGA based project, but as I am a complete beginner, I have very little idea how big an FPGA I need to implement my idea. My project will be something similar to a CPU, ...
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3answers
178 views

Would a standardized graphics chip socket be sensible? [closed]

I am not an EE, and so I'm running this conjecture on breaking out the GPU from the CPU by folks who have better knowledge than me. Perhaps you can point out something I don't know about modern CPU ...
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What is the tradeoff between number of register files and logical register specified in the ISA?

As the limited number of logical registers are opened to the user and compiler, it incurs the false dependency problems such as WAW and WAR. Therefore, to solve this problem, lots of ...
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1answer
91 views

CPU clock cycles required to execute the following inx?

Consider the following data path of a simple non-pipelined CPU. The registers A,B, A1, A2, MDR, the bus and the ALU are 8-bit wide. SP and MAR are 16-bit registers. The MUX is of size 8×(2:1) and the ...
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1answer
84 views

The number of cycles needed to execute the following loop in pipeline processor?

This question was asked in an objective paper; GATE CSE Consider a 4 stage pipeline processor. The number of cycles needed by the four instructions I1, I2, I3, I4 in stages S1, S2, S3, S4 is shown ...
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1answer
137 views

How does a CPU interface with GPIO pins?

I am trying to implement a simple mips1 clone in Verilog at the moment, works all fine in simulators but I also want to run it on an actual FPGA. Basically I would like to send/receive characters to ...
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2answers
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Are some CPUs implemented in standard cells and are others customized?

Explaining the question more, I see some die pictures which are implementing a Cortex-M0, with Bluetooth LE and so on, depending on the chip functionality, and are appearing like this (nRF51822): ...
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2answers
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How are bits put on a bus, the i2c for example?

I have been to school and through these topics, understand that "bits on a bus" is a behaviour emerging from the very way a CPU works. But still, I suppose this requires some interaction... it doesn't ...
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2answers
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GPU vs CPU on chip memory

There has been a fairly wide ranging discussion as to why it is difficult to combine memory / CPU logic on the same die (yield issue compounding, different processes, different clock-frequency, ...
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4answers
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How firmware [like BIOS] gets added to hardware

I am reading about BIOS, which is a piece of non-volatile Firmware. Wikipedia says of firmware: Common reasons for updating firmware include fixing bugs or adding features to the device. This may ...
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1answer
263 views

Is this microcode control store realistic as a hardware implementation?

In a simple control unit using microcoded sequencing, I use a ROM to store the sequences of control signals. The instruction forms the top 8 bits of the ROM address, and the bottom eight bits are ...
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1answer
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Flushing in pipelined architectures

How is the flushing really implemented? I have an idea that on conditional branches, the prior instructions are flushed. But how are they actually flushed?
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2answers
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The Electronics Involved in Instruction Fetching [closed]

I would like to know how the instruction cycle works at an electronics level. I am new to electronics. In order to limit the scope of this question, I am just focusing on the first step of the cycle, ...
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4answers
876 views

How Specifically the Control Unit (CU) Works

I am a software developer now interested in the electronic implementation of computers. When I think about computers, the thing performing the action is the "processor". But the processor is ...
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3answers
387 views

Analog analog multiplication, part of a hybrid CPU (for fun)

Short version: How do I make an analog multiplier that takes two analog DC inputs? Long version: I made a comment recommending Ben Eaters videos for another question, while doing so I ended up ...
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0answers
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CPU idle mode to deep sleep mode transition overhead

I wanted to know for modern processors, what are the typical amounts of switching energy overhead and switching time overhead, to switch from CPU idle mode to deep sleep and back from deep sleep mode ...
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1answer
233 views

Why is the CPU not able to proceed to the next instruction?

I am using Quartus II 14.0 to perform this activity. I have been trying to interface my CPU with an instruction memory module but I am not getting the correct response. The second instruction is not ...
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0answers
641 views

How to write a program for 4-Bit CPU made in Logisim?

So I finally got my 4-Bit CPU working on Logisim, and am trying to get it to do commands and display them, but am unable to do so. My CPU looks like the following: I am trying to implement the ...
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3answers
128 views

What would be the effect of adding small (~<10mm) lengths of conductor between a CPU's contacts and socket

[I am interested specifically in the case of state of-the-art consumer processors and motherboards] To clarify what the setup might be in practice, imagine wires running vertically between each pair ...
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2answers
315 views

CPU register count and access time [closed]

It has been suggested that one of the reasons typical RISC CPUs stop at 32 architectural integer registers, despite a 32-bit instruction having enough spare bits to specify 64, is that a larger ...
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1answer
495 views

Clarification on R, I, and J type Instruction formats in MIPS

I would like some clarification on some concepts of register types, to know if I understand it correctly. If I had a 32-bit CPU. Would that mean that the max number of operations that can be ...
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3answers
129 views

What determines the maximum size of a cpu cache?

Looking at a list of the very latest CPUs, I see several of them with a cache size of 12MB or 8MB - pretty small, when compared to the ever-increasing size of hard drives and ram. It seems to be taken ...
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2answers
200 views

why they use crystal frequency three times the required CPU clock?

In the data sheets for 8284a, the said The crystal frequency should be selected at three times the required CPU clock. why they use crystal frequency three times the required CPU clock?
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1answer
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Need help understanding the status output generation of an ALU

I'm currently trying to implement a simple processor using Verilog in a FPGA. I'm using Mic - 1 architecture as a reference model. The thing I can't understand is the ALU is generating a "status" ...
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7answers
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Is it cheating if I use an SRAM chip as a register file? [closed]

I'm currently building my very own processor using discrete logic (74LSxx series and that) using my very own instruction set architecture. I am starting to rack up a bit of a bill because all the ...