Questions tagged [cpu]

The CPU, known as the Central Processing Unit, is known as the heart of the computer. It is responsible for carrying out the instructions of a computer program by performing the basic arithmetic, logical, control and input/output (I/O) operations specified by the instructions.

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How come a 4 core intel chip has the same TDP as a 6 core intel chip

This has been puzzling me for a while. Here is the definition of TDP from intel spec sheets: Thermal Design Power (TDP) represents the average power, in watts, the processor dissipates when ...
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Can a bulged capacitor prevent a CPU from booting? [on hold]

I am trying to revive my old CPU. But it won't turn on. The fans don't turn ON, but they are working. PSU is also working. I have changed my CMOS battery. I found that one of the capacitors has ...
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The Current Number of CPU and GPU Cores, Going Forward Time [closed]

I have a thought on why, the number of Cores in CPU in the consumer markets are always the same ? Core pairs like below; Intel: i3 (2C, 4T), i5 (4C, 8T), i7 (6C, 12T, and other variants), i9 (8C, ...
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Data Bus and High Impedance

Let's consider an interface between a simple microprocessor and a certain memory. For instance, let's assume that the microprocessor drives the address bus, a read signal, a write signal, and that the ...
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Why does unaligned memory read require extra clock cycles?

I believe I understand how memory reads work with the 8086 processor. The 8086 has a 20-bit address bus and 16-bit data bus (multiplexed). The memory module consists of two memory banks, and the LSB ...
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Can't understand what multiplexers do in CPU datapath

I'm currently learning about data path in a CPU and having a hard time understanding the functionality of G,L, H parts in the following image. Why have those parts been used there?Thanks in advance.
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What is the minimum size of that a segment can take in 8086? [duplicate]

I know that the minimum distance between any 2 segments is be 16 locations (10H) , but some say its 16 bytes , how is that possible if the the locations are of 2 bytes each. It would total to 32 bytes ...
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If we can access (64*4) 256Kb of memory at a time in 8086 and you can move those segments around, what is the use of the remaining memory

If we can access (64*4) 256Kb of memory at a time in 8086 and you can move those segments around, what is the use of the remaining memory? Some say that we can move around the segments but what is the ...
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What kind of hardware multiplier do modern processors use?

I was wondering what kind of multiplier implementations modern processors use. Is it some derived variant of booth Wallace tree algorithm? Are these kinds of micro-architectural details publicized ...
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Why does Intel's Haswell chip allow FP multiplication to be twice as fast as addition?

I was reading this very interesting question on Stack Overflow: Is integer multiplication really done at the same speed as addition on a modern CPU? One of the comments said: "It's worth nothing ...
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Where to study Cortex R architecture? [closed]

I am interested to study Cortex-R architecture but I cannot find its details online. Is it proprietary detail or should I ask for this information from arm.com? Obviously I am not looking for the ...
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ARM Instruction size vs Instruction encoding

I cannot make sense of the difference between 'Instruction size' and 'Instruction encoding' specially about ARM and Thumb ISA's as explained here: Can we say that Instruction size is 32 bits but its ...
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Weird error pattern on CC2541, the 8051 core

I am playing with the debug interface on the TI CC2541. It seems to be working fine, seeing correct chip ID etc. The interface has a DEBUG_INSTR command that lets you submit and execute an ...
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RISC-V: building a datapath for conditional Branch instructions

I am simulating a multi-cycle 32bit RISC-V CPU in Logisim-Evolution and so far so good, i had implemented almost every instruction from the basic RV32I ISA. But im having trouble to understand how the ...
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Building a byte-addressable memory

I am building a memory module: 32 bits wide, parallel, and, byte-addressable. I did a research and i could not find an memory IC that will suit my needs. It ...
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What is the simplest instruction set that has a C++/C compiler to write an emulator for? [closed]

I'm looking into writing a little software emulator that emulates/runs instructions. The easiest would be to invent my own instruction set, but I thought it would be more fun if I write an emulator ...
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X86_64 Architecture, how does it handle instructions larger than 64 bits?

I have been looking more into how CPU's work, and have a question. If I have a instruction that e.g. takes a 64bit address and a register, and copies the value from that address into the register. And ...
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FPGA CPUs, how to find the max speed?

I'm just getting into FPGAs, and if I understand correctly, you are connecting logic gates together using code. So if I design a CPU in Verilog, it should connect some logic gates together and work, ...
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Why different SOCs have different CPU power voltages for given frequency?

Recently, I studied dvfs tables for 3 SOCs: exynos8890(LITTLE cluster), exynos7880, snapdragon 625. Here is the result: octave source code The point is, that different SOCs with pretty same ...
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What does it means that a MCU has support for OpenGL?

I am trying to understand the meaning of when someone says that PowerPC 7410 CPU has support for OpenGL based software. Does it mean that there are any specific instruction in its ISA architecture ...
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1answer
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8-Bit Program Counter Implementation

I'm trying to construct an 8-Bit Program Counter, in Logisim. It currently has functions LOAD, which makes the 8-Bit input (A0-A7) appear at the output (S0-S7) on the clock pulse: Loading 1 as input: ...
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Why not make one big CPU core? [closed]

I don't understand why CPU manufacturers make multi-core chips. Scaling of multiple cores is horrible, this is highly application specific, and I am sure you can point out certain program or code that ...
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Why does this 555 timer not work correctly when I plug in the Z80 CPU ground?

I am trying to build this circuit here: https://www.youtube.com/watch?v=AZb4NLXx1aM But instead of using the same timer setup I am using this: When I connect the ground pin of the CPU, the LED ...
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CPU architecture

im very new to CPU architecture! I wanted to ask, what is the Data memory component in the image below, is it writing/reading to and from RAM or Cache? And also what is the sign extend used for? I ...
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CPU Utilization Methods

To fulfill customer expentations and fill out customer reports about the device, is there also one section about CPU Utilization. Because I have never done such task before I have overview some "...
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Is it truly impossible to tell what a CPU is doing? [closed]

Computer programmers often recite the mantra that x86 instructions are totally opaque: Intel tells us they are doing something, but there is no hope that anyone can verify what's happening, so if the ...
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Why can the energy of local computing be written as \$f^2\$,not \$v^2\$

I saw this formula in this book: Wireless Information and Power Transfer: Theory and Practice And in the formula 14.8, it said: \$f_{i,n}\$ is the CPU frequency for the nth CPU cycle required for ...
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What information exactly does an instruction cache store?

Processors use both data and instruction caches in order to reduce the number of slow accesses to main memory. However, while it is clear to me that the data cache's purpose is to store frequently ...
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Relationships between instruction execution and clock cycle in modern CPUs

I have some misunderstanding about what clock cycle really is. I generally understand a schema how CPU processes an instruction. Intel manual describes the schema for Intel NetBurst architecture as ...
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DMA and Instruction Pipeline

My university resources say that DMA transfers the bunch of data from IO unit to memory or vice verse when processor is not busy with data and address bus. According to the resources, DMA Controller ...
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How does a computer know when to “get” the output from the ALU?

Basically what the title says, I guess I've got some sort of misconception or somthing probably. The ALU can have, say, a ripple carry adder which doesn't produce its entire output all at the same ...
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Why is there a PLL in CPU?

I read that PLL are used in CPU to generate the clock, but I can't understand why. I don't really have any guess of why this is.
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What is the purpose of Delayed Branching? [closed]

I study solutions of control hazards in a processor. One method is delayed branching. To my understanding, specific number of instructions (depending on pipeline length) are always executed subsequent ...
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Renaming a special register

I noticed that RISC-V, like some other RISC architectures, by convention treats register 1 specially, using it as the link register, holding the return address for function calls. If most code ...
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Word length in a computer system

i am currently reading about memory system in computer architecture. I wanted to know, Is the word length the number of bits input to the ALU?
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Home-brew cpu ram

I’m trying to build a cpu out of ttl logic chips. I’ve just about got everything finished, however, I’m still working on the ram. I don’t have any suitable ram chips I can use, however, I do have a ...
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What stops an assembly program from crashing the operating system? [closed]

First of all, I am a beginner, so if this question sounds silly, please point out the incorrect assumptions. From what I understand, the job of an operating system is to manage hardware and the ...
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Is qNaN easier than trapping on overflow?

According to James Demmel's article, "Faster Numerical Algorithms via Exception Handling", IEEE Trans. on Computers 43 (1994), 983-992, the way a floating-point processor handles overflow can be ...
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What prevents the construction of a CPU with all necessary memory represented in registers? [duplicate]

Modern CPUs employ a hierarchy of memory technologies. Registers, built into the chip have the lowest access times, but are expensive and volatile. Cache is a middle-man between RAM and registers to ...
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Cascade shift registers driven by single-cycle microcontroller

I'm trying to make a unit in which 4 digits can be updated in a small amount of time from a single-cycle microcontroller (preferably all digits updated within 5uS) My circuit is setup in the ...
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3answers
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Getting CPU clock signal out of computer (as to measure externally) [closed]

I've been searching on the internet some clock generator module capable of reaching up to 1GHz, when I just realized that the machine I'm using to search has one CPU with its own 2.5-3.0 GHz clock... ...
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Co-Processing Across SBCs

Situation: Was thinking about co-processing as I played with the Adapteva Parallella, which has a quad-core CPU and a 16-core RISC-based co-processor. Question: It got me thinking -- can I achieve ...
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How many external devices can be linked to a CPU with n address buses and m data buses?

(Hypothetical) Let's say there is a CPU with 8 address lines and 8 data lines. If each external device has 128 accessible registers, how many external devices can be linked? For 8 address lines, I ...
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How big does ground need to be? Step down from 5v10a to 1.2V 50a, do I need a 50 amp ground?

I'm just a layman. I was just thinking about CPUs in computers. They run at about 1, 1.5 volts or there about, sometimes even lower. Desktop cpus can take 90 watts, some 120 watts. That's close to 100 ...
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SAP-2 ADD instruction possible in 4 T states?

I'm working through implementation of the SAP-2 CPU from Digital Computer Electronics, 3rd Edition. I'm having difficulty understanding how the arithmetic & logical instructions can be ...
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Why disable interrupt is time-consuming in multi-processor computer?

I have a book statement: Disabling interrupt is time-consuming in multi-processor system. I suspect that this is related to the hardware implementation of how interrupt is enabled/disabled. So ...
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Pipelining speed calculations? [closed]

I'm having trouble finding a formula to calculate this.. The dynamic flow of our program contains 19% branching instructions. The processor uses delayed branching with one delay slot. Calculate how ...
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How to find CPU by needed parameters?

I trying to find a low-power processing unit with lowest price for some practical research. I trying to made a simple device with 1 SATA 3.0, 1 microSD and 1 USB 3.0 interfaces. Can someone advise ...
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Treating Multiple CPU Cores as One

I recently took an undergrad computer architecture course and had a question about using multiple cores after seeing how dense the field of research is. I am thinking about a general idea of how many ...
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Is it true that on a modern processor, parallelism is possible on a single core?

Final Edit: I just realized that when use the word "parallelism", it's almost parallelism==ILP, I originally thought even a single instruction could be divided into ...