Questions tagged [cpu]
The CPU, the Central Processing Unit, is known as the heart of the computer. It is responsible for carrying out the instructions of a computer program by performing the basic arithmetic, logical, control, and input/output (I/O) operations specified by the instructions.
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Wrong value in memory because of a branch misprediction
Lets say we have instructions like:
bne r1 $0 loop
sw r2 0(r1)
Let's say we go ahead with the taken path, i.e., execute the sw instruction after bne assuming the ...
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Configuring CPU with the reversed power polarity
My question comes from a pure curiosity. I initially wrote that it has no practical value, but in the process of writing I came to the idea that one (e.g. an intruder) can potentially use it to ...
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Is a feedback loop from program counter input to output problematic?
I'm designing a very simple CPU to be built on a custom PCB. I designed the CPU in LogicCircuit, and it seems to work. But I'm wondering it a specific part of the CPU will also work in real life.
I ...
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What is the communication protocol used by non-expansion card USB ports to communicate with CPU?
USB ports can come as expansion cards, like this:
Now obviously, since this is a PCIe USB card, the communication protocol used by this expansion card to communicate with CPU is PCIe.
But what about ...
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Is it possible to make the "arithmetic" part of the ALU to be mircoprogrammed?
We know that the Arithmetic and Logic Unit in CPU is a hardware, it is a combinational circuit. Binary addition, for example, is very fast because it doesn't have to be microprogrammed; there is ...
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Does locking a CPU frequency to a higher state (even OC) have any downsides?
I got into an argument with a friend that thinks generally is not a good idea to manually lock a CPU to a high frequency, or even overclocking by locking the frequency, in a stable scenario. His main ...
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6502 Extra Cycles on Page Cross
On the 6502 processor, when using the Absolute,X, Absolute,Y or (Indirect),Y addressing ...
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Why CPU DDR Memory Controller Has 2 Clock Outputs?
I'm trying to understand the ddr structure for the iMX6 Rex Module .
The cpu used is the MCIMX6Q5EYM10AC model from the NXP i.mx quad series.
MCIMX6Q5EYM10AC Datasheet
iMX6 Rex Module Shematics
A ...
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What stops electricity jumping from one part of a circuit to another part of a circuit in a CPU?
If electricity jumps then what prevents even a small charge of electricity jumping from one conductor to another conductor in a CPU where the distance between the conductors is 1000s of a fraction of ...
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Why does the Fused Multiply Add CSA use the inverted MSB of the addend when one multiply operand is negative?
I found one valuable paper about the "Fused Multiply Add":
Instead of using 161-bit CSA, Only the 106 least-significant bits of the
aligned A are needed as input to the 3:2 CSA, because the ...
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(Tiny, very few, raindrops of) Water got into computer [closed]
my CPU was placed next to a window and due to rain a tiny amount of raindrops entered into it. This happened around 3 hours back.
Water on the top of the case was a tiny bit and inside I could only ...
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What does a thick MOSFET symbol mean?
I have come across a bag of about 5,000 n-type MOSFETs (2n7000), and I figured the best thing to do with them is to build a 6502.
I found a diagram of the nMOS 6502 layout
But I am confused as to ...
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My computer force closes games while I’m playing them [closed]
I have done everything I can think of to solve this problem. My computer sat in my car for months while I was in boot camp and I found a spot on there that might be causing it but I don’t know enough ...
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Entering memory adresses into a direct mapping cache
I have been given the following problem:
A computer CPU generates the following adresses in 8 bit binary form: 91, B3, 70 etc. The computer has direct mapping cache that can store 64 words and 8 words ...
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CPU's ESD Rating
Today I was assembling a PC, and went through all the ESD stuff but at the end was wondering how sensitive are these devices actually are. So my question is
What is the ESD HBM rating of a CPU pins ...
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Estimating Power and Energy Consumption of a Spiking Neural Network
I have a traditional Convolutional Neural Network (CNN), and I've converted that to a Spiking CNN (S-CNN). I wanted to compare them on the basis of power and energy consumption. By using a different ...
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"32 bit memory" meaning
While looking at a datasheet about an NXP ARM CPU, I saw that the DRAM controller could support this
Memory types: LPDDR4
• Two channels of 32-bit memory:
• LPDDR4 up to 1.6 GHz
When it says two ...
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What mechanism does CPU use to know if a write to RAM was completed?
How does CPU know that a write to RAM was successful, like how does a faster CPU know that data was successfully written to a slower RAM?
You're free to mention any system architecture because I'm not ...
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DRAM/DDR energy consumption
I have some questions about the origin of energy consumption in DRAM based memories/systems. In Mark Horowitz paper Computing’s Energy Problem
(and what we can do about it) the author breaks down the ...
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How does CPU's Machine Check Architecture work?
Modern CPUs can alert the OS when itself is malfunctioning, i.e. logically incorrect, and apparently, this is supported by a hardware diagnostic feature called Machine Check Architecture. I can ...
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Mark Horowitz Computing's energy problem - methodology
I have a question about the Mark Horowitz paper: Computing’s Energy Problem
(and what we can do about it). In the paper, the author breaks down the sources of energy loss in modern computing systems.
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How much energy decoder & branch predictor consumes compared to ALU/FPU?
x86-64 CPU core consists of many parts, including instruction decoder, branch predictor and ALU/FPU blocks. Which of these parts consumes the most energy? Are there any rough number for each of these ...
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What is the difference between CPU, GPU, TPU?
I use python code on Google Colab. I would like to ask what is the difference between CPUs, GPUs, TPUs and why the last two have so intense acceleration on python code??? I have seen tutorials on ...
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Can we service another memory request from L1 cache when an L1 miss is being serviced from L2?
Consider the case where L1 cache miss occurred and is being serviced by L2 cache which could take many cycles (may go to main memory in case of L2 cache miss). In the meantime L1 cache is idle, in ...
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How does a flip-flop work in CPU registers?
From what I know, CPU registers work with flip-flops and when the data must pass from one register to another it travels on a bus. This happens only through an appropriate control signal.
What I want ...
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Replacement of RaspberryPi [closed]
I'm working with a learning project where I use an IMU sensor unit connected with Raspberry Pi 4B via UART. I receive data on Raspi's serial port and later I use that data to display it on a self made ...
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Will a pair of identical conductors in the form of identical waves that are 180 degrees out of phase cancel each other out completely? [duplicate]
Since identical waveforms that are 180 degrees out of phase will cancel each other out completely, does that mean a pair of identical conductors in the form of identical waves that are 180 degrees out ...
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Can we say that a CPU is an ASIC that is designed to perform a wide range of instructions?
My question is more terminological than technical.
I have come across different definitions of what an ASIC is. The most common one is that an ASIC is an IC that is designed for a specific application ...
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Is it possible to connect an antenna of the proper length to a CPU and radiate its 4 GHz oscillating current?
Since a 4 GHz CPU has been made to provide that super high frequency, is it possible to connect an antenna of the right length to it and radiate its 4 GHz oscillating current?
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Are there now 64-bit processors that deal with denorms routinely with no exception or interrupt?
Title says it all.
Are there processors with FPUs that deal with denorms arithmetically correctly (don't assume they're zero nor flush them to zero) and don't cause an exception? I would be interested ...
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Can a CPU be notified that it's about to lose power? [closed]
If I have a desktop computer and I pull out the power cord, are there are a few million CPU cycles that still happen before it completely runs out of energy? There could even be a capacitor on the ...
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What happens after Return 0 in C on an embedded microcontroller? [duplicate]
In an embedded microcontroller programmed using C, generally the code body is placed within a continuous loop like while(1) in the main function so execution never ...
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Multicore CPU design dilemma on reading from/writing to hardware devices
I have built a simple 8-bit processor with 16-bit address lines and 8-bit data lines; not the most efficient CPU architecture, but it does the job. As you might have guessed, this CPU is really simple:...
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How much power can a 6 nm transistor handle?
Modern semiconductors are manufactured with feature sizes measured in nanometers. For example, the EPYC 9654 CPU has 78840 million transistors. Each one is in 6 nm and has a TDP of 360 W. What is ...
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How to program the CPU when making a small microcomputer?
I'm trying to make a small microcomputer from individual parts, but I'm having a hard time understanding how to load code onto the processor to be able to run it and do something.
Attached is my ...
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RISC-V Zero Instruction Question
I have seen a table of opcodes for RISC-V instructions (for base I 32 bit ISA). I am working with a RISC-V core on FPGA and had BRAM for instructions set to all zeros.
Does anybody know what happens ...
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Why are there separated power circuits for CPU, GPU, and RAM on a motherboard?
Even though there is a power supply unit in a computer case, why are there separated power circuits for CPU, GPU, and RAM on the motherboard?
I mean, why can not the CPU, RAM and GPU just take their ...
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Performance difference when comparing PCIe DMA vs. MMIO for same data access size
Some PCIe devices can map their own device memory region fully to contiguous host physical memory address space through a feature called PCIe Resizable BAR (base address register), which makes it ...
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What is meaning and significance of locally decrementing SP (Stack Pointer)?
What is meaning of line "SP (Stack Pointer) can be decremented locally"
*I am not asking the answer of the whole question in the image.
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Mitigating structural hazards in register files in processor pipelines
I am reading about structural hazards in pipelined architecture in processors. In classic RISC pipeline one such hazard is when we write and read simultaneously to same register, which may cause ...
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Is there any difference between a CPU core and a CPU itself?
I was reading this article that explains the difference between a thread and a core and it says the following:
...
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Best practice to implement wait state on 6502 CPU
What is the best practice to implement wait states on a 65(C)02?
Are there any schematics to use as reference?
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Why hasn't DRAM speed kept up with CPU speed as technology improves?
In 1976, the Z80 processor ran at 2.5 MHz and a typical DRAM access time was 500 ns. Now, processors run at 4 GHz and DRAM access time is 50 ns. Thus, processors are over three orders of magnitude ...
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What determines the maximum clock rate for a CPU?
What factors determine the maximum CPU clock rate? A 6502, for instance, clocks in the megahertz range, while an Intel x64 chip typically clocks in the gigahertz range.
All things being equal, if the ...
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Why does the CPU usage of a Beaglebone Black peak while running an infinite loop?
I am using a BeagleBone Black to trigger an ultrasonic sensor and expecting the Echo pin-connected GPIO to be sensed as HIGH by my program, but it almost crashes the system.
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CPU test pins (test as a noun)
Looking at the FM2 socket for AMD processors I've noticed that there are some "test pins", i.e V22.
What are they for? Is it possible to manage them, i.e for some led signaling?
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How do modern CPU manufacturers determine the suitable base clock and the associated power?
Modern CPUs have very smart boosting strategies. When idle, they automatically underclock to conserve energy. When busy, they automatically boost or overclock. The adjustments are so dynamic today ...
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What makes a GPU inferior to CPU? [closed]
A computer is supposed to crunch numbers and then output the result data. To make this happen we program the computer to do what we want. This can be done by writing a program in high level language ...
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Single-cycle ARM processor (flags)
This is an ARM processor from my book:
The picture can be enlarged by clicking on it.
I'm wondering about the control unit below, specifically the last picture, the conditional logic. Is the ...
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Can more fan-out be achieved with two inverters, and if so, how to choose which path?
This is a pretty theoretical question. My interest is digital circuits for CPU design.
Let's say I have some digital CMOS circuit composed of 50 transistors that implements some logical function. Let'...
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