Questions tagged [cpu]

The CPU, known as the Central Processing Unit, is known as the heart of the computer. It is responsible for carrying out the instructions of a computer program by performing the basic arithmetic, logical, control and input/output (I/O) operations specified by the instructions.

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0answers
38 views

How do CPU, IOMMU and DMA controller interact with each other?

While drawing an interaction diagram involving CPU, IOMMU and DMA controller, I failed to find any authentic document showing how they interact with each other. Is the DMA controller physically a ...
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Infinite loop on microcontroller vs modern CPU

On a microcontroller (more specifically, on an Arduino Uno board using the ATmega 328P microcontroller) I would normally use an infinite loop to check for inputs etc (in Arduino land, this is normally ...
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What is an emulator POD?

Jack Ganssle - The Firmware Handbook States ...
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IA 32 architecture segmentation

I was reading the 10th edition of "Operating System Concepts" written by Abraham Silberschatz and many others. It says about IA-32 architecture's segmentation: The IA-32 architecture allows a ...
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1answer
96 views

Difference CPU, ASIP, DSP [closed]

During lecture CPU (Central Processing Unit), ASIP (Application-Specific Instruction set Processor) and DSP (Digital Signal Processor) were briefly mentioned. Unfortunately the main differences (and ...
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2answers
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Why are GPU dies so much physically bigger than CPU dies?

I understand that the physical sizes of microchips are generally limited by silicon yields. The larger your chip is, the more waste occurs when you hit a defect in the silicon and have to throw it ...
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For mainstream computing what are the practical advantages of 64-bit register size CPUs given the needs of today and the near future? [closed]

I understand one of the limitations of 32-bit processors is the inability to easily address more than 4GiB of RAM, which is a present day need even for mainstream computing on phones, tablets and ...
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1answer
146 views

Single-cycle MIPS processor in Verilog

I'm very new to Verilog and I've tried to create single-cycle 32bit MIPS processor. Instructions I want to implement are ...
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1answer
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how to copy the value of a register into another (Logisim)

how to design the circuit that copy the value of register into the other? I only know the register can be written or loaded, but how is it possible that after loaded the value of 1 register and still ...
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Buses and the ALU in the 8086

Intel's 8086 manual shows the following diagram for the CPU's architecture (in page 2-5): If I understand correctly, the ALU's two operands and result are retrieved from / sent to the same 16-bit bus....
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1answer
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Thoughts & questions on custom CPU architecture

I'm designing a CPU architecture. I've come up with a preliminary design: I'd like general thoughts on what I can improve in the design and also I have some specific questions: Is it overkill to ...
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CPU no pipeline vs 1 stage pipeline

I was taking the the P.E. practice exam and there is a question that shows a CPU without pipeline stages. There were options for both a 1 stage pipeline or that it was a non-pipelined architecture. ...
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1answer
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The accurate time latency for 'lw' instruction in a single-cycle datapath

I want to calculate the cycle time of a single-cycle datapath. Then from the course, I know the time should be the execution time of the longest instruction, which is 'lw' in MIPS. So I try to ...
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Is a CPU declarative?

I know that this might seem like a stupid question, because declarative is not really an electrical term. I'm having a discussion (argument) with someone who is a functional programming fanatic, and ...
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3answers
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How does a cpu represent bits? [closed]

Maybe my question was asked earlier, but I want info away from logical abstractions, in different contrast. START: A transistor can represent two states - on and off - means 1 and 0 - means 1bit. So ...
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1answer
30 views

CPU cache write policy - evict already dirty? + storage of memory address

I'm reading about cache in wiki https://en.m.wikipedia.org/wiki/CPU_cache and the following phrase seems not clear. Also, a write to a main memory location that is not yet mapped in a write-back ...
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Reverse Feedback protection in a RC circuit

I have been working on a model CPU build from LS TTL ICs for the past couple of weeks. I am going to give a little background here, during the prototyping I stumbled upon several intresting issues ...
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How come a 4 core intel chip has the same TDP as a 6 core intel chip

This has been puzzling me for a while. Here is the definition of TDP from intel spec sheets: Thermal Design Power (TDP) represents the average power, in watts, the processor dissipates when ...
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1answer
128 views

Can a bulged capacitor prevent a CPU from booting? [closed]

I am trying to revive my old CPU. But it won't turn on. The fans don't turn ON, but they are working. PSU is also working. I have changed my CMOS battery. I found that one of the capacitors has ...
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2answers
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Data Bus and High Impedance

Let's consider an interface between a simple microprocessor and a certain memory. For instance, let's assume that the microprocessor drives the address bus, a read signal, a write signal, and that the ...
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4answers
106 views

Why does unaligned memory read require extra clock cycles?

I believe I understand how memory reads work with the 8086 processor. The 8086 has a 20-bit address bus and 16-bit data bus (multiplexed). The memory module consists of two memory banks, and the LSB ...
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1answer
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Can't understand what multiplexers do in CPU datapath

I'm currently learning about data path in a CPU and having a hard time understanding the functionality of G,L, H parts in the following image. Why have those parts been used there?Thanks in advance.
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What is the minimum size of that a segment can take in 8086? [duplicate]

I know that the minimum distance between any 2 segments is be 16 locations (10H) , but some say its 16 bytes , how is that possible if the the locations are of 2 bytes each. It would total to 32 bytes ...
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If we can access (64*4) 256Kb of memory at a time in 8086 and you can move those segments around, what is the use of the remaining memory

If we can access (64*4) 256Kb of memory at a time in 8086 and you can move those segments around, what is the use of the remaining memory? Some say that we can move around the segments but what is the ...
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1answer
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What kind of hardware multiplier do modern processors use?

I was wondering what kind of multiplier implementations modern processors use. Is it some derived variant of booth Wallace tree algorithm? Are these kinds of micro-architectural details publicized ...
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Why does Intel's Haswell chip allow FP multiplication to be twice as fast as addition?

I was reading this very interesting question on Stack Overflow: Is integer multiplication really done at the same speed as addition on a modern CPU? One of the comments said: "It's worth nothing ...
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1answer
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Where to study Cortex R architecture? [closed]

I am interested to study Cortex-R architecture but I cannot find its details online. Is it proprietary detail or should I ask for this information from arm.com? Obviously I am not looking for the ...
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2answers
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ARM Instruction size vs Instruction encoding

I cannot make sense of the difference between 'Instruction size' and 'Instruction encoding' specially about ARM and Thumb ISA's as explained here: Can we say that Instruction size is 32 bits but its ...
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1answer
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Weird error pattern on CC2541, the 8051 core

I am playing with the debug interface on the TI CC2541. It seems to be working fine, seeing correct chip ID etc. The interface has a DEBUG_INSTR command that lets you submit and execute an ...
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1answer
167 views

RISC-V: building a datapath for conditional Branch instructions

I am simulating a multi-cycle 32bit RISC-V CPU in Logisim-Evolution and so far so good, i had implemented almost every instruction from the basic RV32I ISA. But im having trouble to understand how the ...
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1answer
108 views

Building a byte-addressable memory

I am building a memory module: 32 bits wide, parallel, and, byte-addressable. I did a research and i could not find an memory IC that will suit my needs. It ...
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9answers
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What is the simplest instruction set that has a C++/C compiler to write an emulator for? [closed]

I'm looking into writing a little software emulator that emulates/runs instructions. The easiest would be to invent my own instruction set, but I thought it would be more fun if I write an emulator ...
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2answers
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X86_64 Architecture, how does it handle instructions larger than 64 bits?

I have been looking more into how CPU's work, and have a question. If I have a instruction that e.g. takes a 64bit address and a register, and copies the value from that address into the register. And ...
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FPGA CPUs, how to find the max speed?

I'm just getting into FPGAs, and if I understand correctly, you are connecting logic gates together using code. So if I design a CPU in Verilog, it should connect some logic gates together and work, ...
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1answer
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Why different SOCs have different CPU power voltages for given frequency?

Recently, I studied dvfs tables for 3 SOCs: exynos8890(LITTLE cluster), exynos7880, snapdragon 625. Here is the result: octave source code The point is, that different SOCs with pretty same ...
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2answers
135 views

What does it means that a MCU has support for OpenGL?

I am trying to understand the meaning of when someone says that PowerPC 7410 CPU has support for OpenGL based software. Does it mean that there are any specific instruction in its ISA architecture ...
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1answer
148 views

8-Bit Program Counter Implementation

I'm trying to construct an 8-Bit Program Counter, in Logisim. It currently has functions LOAD, which makes the 8-Bit input (A0-A7) appear at the output (S0-S7) on the clock pulse: Loading 1 as input: ...
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11answers
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Why not make one big CPU core? [closed]

I don't understand why CPU manufacturers make multi-core chips. Scaling of multiple cores is horrible, this is highly application specific, and I am sure you can point out certain program or code that ...
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1answer
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Why does this 555 timer not work correctly when I plug in the Z80 CPU ground?

I am trying to build this circuit here: https://www.youtube.com/watch?v=AZb4NLXx1aM But instead of using the same timer setup I am using this: When I connect the ground pin of the CPU, the LED ...
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1answer
98 views

CPU architecture

im very new to CPU architecture! I wanted to ask, what is the Data memory component in the image below, is it writing/reading to and from RAM or Cache? And also what is the sign extend used for? I ...
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1answer
245 views

CPU Utilization Methods

To fulfill customer expentations and fill out customer reports about the device, is there also one section about CPU Utilization. Because I have never done such task before I have overview some "...
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6answers
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Is it truly impossible to tell what a CPU is doing? [closed]

Computer programmers often recite the mantra that x86 instructions are totally opaque: Intel tells us they are doing something, but there is no hope that anyone can verify what's happening, so if the ...
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2answers
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Why can the energy of local computing be written as \$f^2\$,not \$v^2\$

I saw this formula in this book: Wireless Information and Power Transfer: Theory and Practice And in the formula 14.8, it said: \$f_{i,n}\$ is the CPU frequency for the nth CPU cycle required for ...
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3answers
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What information exactly does an instruction cache store?

Processors use both data and instruction caches in order to reduce the number of slow accesses to main memory. However, while it is clear to me that the data cache's purpose is to store frequently ...
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1answer
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Relationships between instruction execution and clock cycle in modern CPUs

I have some misunderstanding about what clock cycle really is. I generally understand a schema how CPU processes an instruction. Intel manual describes the schema for Intel NetBurst architecture as ...
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0answers
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DMA and Instruction Pipeline

My university resources say that DMA transfers the bunch of data from IO unit to memory or vice verse when processor is not busy with data and address bus. According to the resources, DMA Controller ...
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2answers
72 views

How does a computer know when to “get” the output from the ALU?

Basically what the title says, I guess I've got some sort of misconception or somthing probably. The ALU can have, say, a ripple carry adder which doesn't produce its entire output all at the same ...
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5answers
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Why is there a PLL in CPU?

I read that PLL are used in CPU to generate the clock, but I can't understand why. I don't really have any guess of why this is.
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1answer
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What is the purpose of Delayed Branching? [closed]

I study solutions of control hazards in a processor. One method is delayed branching. To my understanding, specific number of instructions (depending on pipeline length) are always executed subsequent ...
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Renaming a special register

I noticed that RISC-V, like some other RISC architectures, by convention treats register 1 specially, using it as the link register, holding the return address for function calls. If most code ...

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