Questions tagged [cpu]
The CPU, the Central Processing Unit, is known as the heart of the computer. It is responsible for carrying out the instructions of a computer program by performing the basic arithmetic, logical, control, and input/output (I/O) operations specified by the instructions.
45
questions with no upvoted or accepted answers
7
votes
0
answers
280
views
x86 Motherboard Bring Up - Intel Tiger Lake UP3 CPU
For those who has experience with Intel x86 motherboard design and bring up.
I'm in the middle of motherboard bring-up that has Intel Tiger Lake UP3 CPU.
Seems like I had a good run so far at power-up ...
- 1,031
2
votes
1
answer
369
views
Program counter updating in a single-cycle ARM processor
This picture is from the book Digital Design and Computer Architecture: ARM Edition. It implements the LDR instruction.
I have one question:
R15 is supposed to be PC+8. In the picture, is R15 ...
- 289
2
votes
0
answers
189
views
FPGA and CPU design: Moving from ideal memory to real RAM blocks
I implemented the single-cycle MIPS design from "Computer Organisation and Design" in Verilog, shown below:
I used my own "ideal" data memory implementation, which asynchronously presents the read ...
- 21
2
votes
0
answers
77
views
How do CPU, IOMMU and DMA controller interact with each other?
While drawing an interaction diagram involving CPU, IOMMU and DMA controller, I failed to find any authentic document showing how they interact with each other. Is the DMA controller physically a ...
- 219
2
votes
3
answers
354
views
CPU no pipeline vs 1 stage pipeline
I was taking the the P.E. practice exam and there is a question that shows a CPU without pipeline stages. There were options for both a 1 stage pipeline or that it was a non-pipelined architecture. ...
- 533
2
votes
1
answer
1k
views
The accurate time latency for 'lw' instruction in a single-cycle datapath
I want to calculate the cycle time of a single-cycle datapath. Then from the course, I know the time should be the execution time of the longest instruction, which is 'lw' in MIPS.
So I try to ...
- 21
1
vote
0
answers
52
views
6502 Extra Cycles on Page Cross
On the 6502 processor, when using the Absolute,X, Absolute,Y or (Indirect),Y addressing ...
- 291
1
vote
0
answers
64
views
Why CPU DDR Memory Controller Has 2 Clock Outputs?
I'm trying to understand the ddr structure for the iMX6 Rex Module .
The cpu used is the MCIMX6Q5EYM10AC model from the NXP i.mx quad series.
MCIMX6Q5EYM10AC Datasheet
iMX6 Rex Module Shematics
A ...
- 553
1
vote
0
answers
49
views
Are there now 64-bit processors that deal with denorms routinely with no exception or interrupt?
Title says it all.
Are there processors with FPUs that deal with denorms arithmetically correctly (don't assume they're zero nor flush them to zero) and don't cause an exception? I would be interested ...
- 1,655
1
vote
0
answers
36
views
Are coarse-grained reconfigurable architectures a subset of dataflow architecture?
By definition, dataflow architectures consist of large modules in the dataflow path, such as adders and multipliers for integer, floating-point, or fixed-point computation.
Hence, are coarse-grained ...
- 51
1
vote
0
answers
247
views
Building a stepper in Logisim - Cannot find the error
I try to build a stepper based on a book. I have been looking for the error for hours now, but still could not find it. Maybe you can help me with this issue?
This is my stepper:
This is a working ...
1
vote
0
answers
57
views
Difficulty in understanding the concept of operand forward in pipeling and when to use split phase
Given below is a question from \$\text{GATE } 2015 \text{ CS}\$ paper,
Consider the sequence of machine instruction given below:
\begin{array}{ll} \text{MUL} & \text{R5, R0, R1} \\ \text{DIV} &...
- 155
1
vote
1
answer
128
views
MOS chip dimensions
I am looking for the physical dimensions to some chips used on the VIC20.
Looking at the datasheet http://www.6502.org/documents/datasheets/ the document is cryptic, not much conclusive because it ...
- 13
1
vote
0
answers
434
views
How to cascade IC 74HC161 correctly?
Currently I have this 4 bit CPU as shown in the schematic diagram below.
What I wish to achieve:
Add one more output register to make the CPU output a total of 8 bits
Show alphabet using the 8 bits ...
- 11
1
vote
0
answers
53
views
Cache Memory Read and Write Miss/hit policies: details of a real processor
All the references I have checked so far explain the Read Miss,Write Hit/Miss policies at the same level of detail. I understand their concepts but I am looking for more details on their ...
- 13
1
vote
0
answers
160
views
iphone 6 plus - Is the resistor R0601 important?
What is the resistor R0601 important for?
Can a iphone 6 plus work without it ?
What is the meaning of the code (ZQ) in the iphone schematic?
Thanks
- 11
1
vote
0
answers
63
views
How come a 4 core intel chip has the same TDP as a 6 core intel chip
This has been puzzling me for a while.
Here is the definition of TDP from intel spec sheets:
Thermal Design Power (TDP) represents the average power, in watts, the
processor dissipates when ...
- 111
1
vote
0
answers
43
views
Renaming a special register
I noticed that RISC-V, like some other RISC architectures, by convention treats register 1 specially, using it as the link register, holding the return address for function calls.
If most code ...
- 559
1
vote
0
answers
923
views
State machines and control signals in a simple CPU
Having built the CPU specified in "The Elements of Computing Systems", I thought I'd try to design a simple 8-bit CPU myself as a fun challenge, with a view to implementing it on an FPGA. However, the ...
- 111
0
votes
0
answers
47
views
Wrong value in memory because of a branch misprediction
Lets say we have instructions like:
bne r1 $0 loop
sw r2 0(r1)
Let's say we go ahead with the taken path, i.e., execute the sw instruction after bne assuming the ...
0
votes
0
answers
28
views
Why does the Fused Multiply Add CSA use the inverted MSB of the addend when one multiply operand is negative?
I found one valuable paper about the "Fused Multiply Add":
Instead of using 161-bit CSA, Only the 106 least-significant bits of the
aligned A are needed as input to the 3:2 CSA, because the ...
- 83
0
votes
0
answers
21
views
Entering memory adresses into a direct mapping cache
I have been given the following problem:
A computer CPU generates the following adresses in 8 bit binary form: 91, B3, 70 etc. The computer has direct mapping cache that can store 64 words and 8 words ...
0
votes
0
answers
52
views
CPU's ESD Rating
Today I was assembling a PC, and went through all the ESD stuff but at the end was wondering how sensitive are these devices actually are. So my question is
What is the ESD HBM rating of a CPU pins ...
- 874
0
votes
0
answers
32
views
Estimating Power and Energy Consumption of a Spiking Neural Network
I have a traditional Convolutional Neural Network (CNN), and I've converted that to a Spiking CNN (S-CNN). I wanted to compare them on the basis of power and energy consumption. By using a different ...
- 189
0
votes
0
answers
49
views
DRAM/DDR energy consumption
I have some questions about the origin of energy consumption in DRAM based memories/systems. In Mark Horowitz paper Computing’s Energy Problem
(and what we can do about it) the author breaks down the ...
- 41
0
votes
0
answers
90
views
Mark Horowitz Computing's energy problem - methodology
I have a question about the Mark Horowitz paper: Computing’s Energy Problem
(and what we can do about it). In the paper, the author breaks down the sources of energy loss in modern computing systems.
...
- 41
0
votes
0
answers
41
views
Can we service another memory request from L1 cache when an L1 miss is being serviced from L2?
Consider the case where L1 cache miss occurred and is being serviced by L2 cache which could take many cycles (may go to main memory in case of L2 cache miss). In the meantime L1 cache is idle, in ...
- 137
0
votes
2
answers
387
views
Undefined(U) values in Vivado sim
I am designing a nanoprocessor and below is my instruction decoder code. As you can see I have used case statements for specific operations based on the input signal.
Because of this, as you can see, ...
- 21
0
votes
0
answers
54
views
CPU(MCU) freezing mechanism due to control voltage dip
I used to develop CPU boards before.
I have been wondering why CPU is stop when there are noise on the DC control power line.
I thought about the mechanism.
when voltage is droped. Internal register ...
- 143
0
votes
0
answers
119
views
What is the cost of increasing the number of register names?
Increasing the number of registers in a CPU, has the upside that more values can be kept in registers instead of having to spill to stack. It has some downsides, one of which is that more instruction ...
- 559
0
votes
0
answers
81
views
Attach heat sink to cpu cooler in order to decrease CPU temperature
The best SMALL FACTOR cpu cooler that I have found so far is this one:
I am building a portable PC; therefore, the smaller the better. I have already checked the specifications and that cpu Noctua ...
- 557
0
votes
0
answers
28
views
How do I read the value of registers in Logism?
I am designing a CPU in logism. One of the components of the CPU is a register circuit (RegFile), which stores the registers data. The register circuit (RegFile) is shown below:
I am able to write ...
- 113
0
votes
0
answers
505
views
Forwarding in RiscV multi cycle Pipeline
Any idea could be helpful
I have been trying for days to understand forwarding mechanism in RiscV but unfountly I keep failing, so I though about asking basic question to make sure I am building on ...
- 41
0
votes
0
answers
91
views
Why we can't do forward in RiscV?
While studying forwarding in RiscV cpu I saw the following claim:
But I can't understand why we can't do forward in this case, why in different conditions we were able to do this and now we can't?
It ...
- 21
0
votes
2
answers
186
views
Why do server mainboards use different capacitors for their VRMs?
Recently I noticed that server mainboards use a different type of capacitor as part of their VRMs (after the inductor). I believe they are ceramic capacitors, whereas consumer boards usually use ...
- 1
0
votes
0
answers
66
views
How temperature difference does not affect transistors in CPUs?
Recently I learned about semi-conductors and some devices.
Today I watched a video on youtube about a guy overclocking a cpu to 7.0 ghz, while cooling it with liquid nitrogen to -192 celsius degrees. ...
0
votes
0
answers
143
views
what were the ENIAC's equivalent to the modern CPU's elements?
If a modern CPU contains these elements:
- 3 or more register units
- ALU
- control unit
and the CPU is connected to a RAM composed of several addresses, what ...
- 113
0
votes
0
answers
284
views
Using interrupts with W65C02 and W65C22
I’m trying to use the interrupts of the 6502 and 6522. I want to read the value of PORTA whenever the “READY” line I have is HIGH.
I think I understood that I have to put the “READY” line on CA1 and ...
- 1
0
votes
0
answers
51
views
Is it possible to speculate on the completion of an adder from the first row?
I've seen speculative adders that take an extra clock cycle something on the order of once in 10^5 additions. Often papers on speculative adders claim to need the information from stage 1 and stage <...
- 123
0
votes
1
answer
2k
views
how to copy the value of a register into another (Logisim)
how to design the circuit that copy the value of register into the other? I only know the register can be written or loaded, but how is it possible that after loaded the value of 1 register and still ...
0
votes
1
answer
65
views
Weird error pattern on CC2541, the 8051 core
I am playing with the debug interface on the TI CC2541. It seems to be working fine, seeing correct chip ID etc.
The interface has a DEBUG_INSTR command that lets you submit and execute an ...
- 405
0
votes
0
answers
416
views
DMA and Instruction Pipeline
My university resources say that DMA transfers the bunch of data from IO unit to memory or vice verse when processor is not busy with data and address bus. According to the resources, DMA Controller ...
- 101
0
votes
0
answers
287
views
Electret condense microphone(ECM), its external circuit design
I got the external circuit about the Electret condense microphone(ECM), shown as in the below. I would like to know that 1). How it can work out on differential signal to input to CPU? 2). It seems ...
- 155
0
votes
0
answers
179
views
How do you initialize the target cpu using the usbWiggler API?
I'm trying to use usbWiggler to communicate with a board that has 4 ICs.
Through the usbWiggler API I have been trying to write and read from the board. However the CPU on the board is not one of the ...
- 419
0
votes
0
answers
198
views
Copper sheet thickness to use between Peltier and CPU
I'm going to use a TEC-12726 (50mm by 50mm, 240W QMax) to cool an FX-8120 (40mm by 40mm, 125W TDP) CPU, and I want to use the full size of the TEC by putting a sheet of copper between the CPU and TEC, ...
- 147