Questions tagged [cyclone]

Cyclone is a family of FPGAs from Altera

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Cyclone III FPGA 3.3V LVTTL output rise and fall time restoration at 25MHz

I am using this signal to drive MD1822 mosfet driver to get high voltage pulses but fpga output rise time and fall time almost 40nS and underdamped I can not get good pulses. How can i improve this? I ...
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123 views

FPGA counter value unstabillity

I have been building a synchronized I2C slave receiver with Verilog. The I2C slave receiver did not encounter any issues when I simulated it with Modelsim. However, it does not function properly ...
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1answer
62 views

How do I get started with my Cyclone IV EP4CE FPGA development board? (Assignment file) [closed]

I have bought a Cyclone IV FPGA development board on AliExpress. I have installed Quartus II 14.01 and I have a sample VHDL file but I do not know how to do the pin assignment without an assignment ...
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1answer
952 views

FPGA starts working after irrelevant changes, why?

I have written a UART module in Verilog. By using that module I get data from PC via UART and then send that data back again via this UART module. I uploaded it to FPGA for testing. It works flawless ...
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2answers
121 views

Why are registers being turned on to 1 before reset/on button is hit on FPGA?

I am writing a really simple program on Verilog for my FPGA to have an LED blink once a button is pushed. Here is the code I have written: ...
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32 views

Quartus Prime Lite: Generate a 25.18 MHz clock and Constrain to clock input in HDL

I am trying to use a generated clock in .sdc to drive my logic in my DE1-SoC Cyclone V chip. When I load the design onto the chip currently, nothing happens. My counter led does not even blink to show ...
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3answers
167 views

Why is my seconds counter in verilog jumping values behaviour?

I am implementing a seconds counter on the Altera DE-1 Educational Board powered by the old Cyclone 2 FPGA. My plan is to make a 'down-clocker' that takes the on-board 50 MHz clock and produces a 1 Hz ...
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97 views

My JTAG connection with Cyclone IV is not working

My FPGA board is not programming. I think I have followed all the guide lines for JTAG connection. Can you see any problems with this connection?
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1answer
151 views

What's wrong with this schematic for powering up Cyclone IV FPGA?

I have followed all the guide lines for powering up the Cyclone IV. However, the 3.3v Regulator is heating too much and also the Cyclone IV FPGA. What's wrong with my schematic? Is there a problem in ...
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48 views

Identify valid FPGA configuration image in serial flash device?

How can I know if there's valid FPGA configuration image in the specific location of the serial configuration device before I perform reconfiguration and experience successful or faulty attempt? ...
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1answer
461 views

Altera Cyclone II Quartus II JTAG Programming Error

I'm trying to program a Cyclone II I bought here using Quartus II 13.0sp1 on Arch Linux. I'm trying to program it with a very simple Verilog program with three inputs and two outputs and a few simple ...
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1answer
164 views

How to implement an ADPLL in Verilog that locks onto an arbitrary sine wave?

I'm unable to figure out how to implement an ADPLL on an FPGA that can take in an arbitrary periodic input and lock onto its frequency (some finite range is okay) and phase. A square wave output will ...
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2answers
266 views

How to open up serial terminal for my USB device converter (or, how to enable VCP in linux)?

I am using a new Cyclone V SoC board by Enclustra (Mercury+ SA2) mounted on their PE-1 BaseBoard. To connect to the board serially on Windows platform, I have to connect the board which is detected ...
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1answer
137 views

What is the minimal schematic (needed capactiors/resistors) to use FPGA Altera Cyclone 4 EP4CE6E22C8N? [closed]

I can't find any information about how wire the Cyclone 4 FPGA. I do not want to use development boards.
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Change memory content of FPGA SoC (DE1-SoC) using software while .sof (EPCQ) is running on FPGA

I am new to FPGA and FPGA-SoC world. I have a DE1-SoC board. I am doing a project. Hardware design of the project contains a memory block which is initialized using .mif file. I know that we can use ...
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1answer
173 views

How can I transfer data to cyclone 4?

I have the fpga below, I managed to implement a couple of simple designs. According to the manual it should be possible to foward data from my laptop to the fpga using the usb-blaster cable, I cannot ...
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1answer
1k views

Altera Cyclone V - Linux & FPGA interrupt handling

I need to propagate an interrupt from my custom FPGA IP core to the HPS system of a DE0_nano_SoC (Cyclone V HPS-FPGA architecture) and handle in Linux. I have googled quite a lot to confidently say ...
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1answer
1k views

Error (209015): Can't configure device. Expected JTAG ID code 0x020B10DD for device 1, but found JTAG ID code 0x000210DD

I bought from ebay Altera Cyclone II EP2C5T144 development board. It came with USB Blaster. I'm using Quartus II 13.0sp1. FPGA is programmed with default settings as it should be (flashing onboard ...
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1answer
2k views

FDCE flip flop primitive on altera quartus?

I would like to know the altera quartus primitive equivalent to the FDCE flip flop on Xilinx ISE. I think that DFFE primitive might work however I am not sure about the CE and CLR pins equivalency. ...
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1answer
160 views

On Cyclone II FPGAs can I apply voltage directly on input pins?

On Cyclone II FPGAs can I apply voltage directly on input pins, maybe taking it from a Vcc pin? Or should I use a resistor? The Altera DE2 board's schematics below looks like some input switches don'...
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169 views

VHDL error: multiple constant drivers for net

I can't find how to deal with the error: "multiple constant drives" which occures when I try to read and set the same net in a single process. I need to set the "output" for some clock cycles on the ...
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2answers
632 views

Why would IO pins be tied to VCC or GND with 0 Ohm resistor on FPGA Dev Board?

I have a cheap Altera Cyclone II EP2C5T144C8 Dev Board and a few (4) of the IO/LVDS pins are shorted to VCC or GND as shown in the schematic segment below. The pins are also brought out to headers on ...
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2answers
3k views

FPGA Memory vs Registers

I'm having an issue on an FPGA project I'm working on. I'm unable to write to defined memories within the FPGA, but writing to registers works fine. I was thinking about working around this problem by ...
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1answer
922 views

Failing to program Cyclone IV GX device via JTAG

I just got the aforementioned device and, upon writing a simple program (it compiles) and going into Programmer, when I try to program the device with the .sof file, I see is ...
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2answers
819 views

Cyclone V external memory group pins DQ/DQS

I'm trying to understand the functions of external memory pins in Cyclone V (5csema5af31c6n) I do understand that colums HMC Pin Assignment for DDR3/DDR2/LPDDR2 shows pin functions for external ...
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1answer
868 views

Output CLOCK signal to GPIO pin of CYCLONE IV E

I am new to FPGA and I am trying to send a CLOCK signal as an output of a GPIO pin of an Altera Cyclone IV E. I first made a program: ...
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2answers
301 views

Adaptative Logic Module : Logic Element equivalence

I have implemented some circuitry with Quartus on a Cyclone 5 FPGA. This has be done for my master thesis. I have to justify wether the number of logic element used by my implementation is "expected" ...
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1answer
2k views

Error (209015): Can't configure device. Expected JTAG ID code 0x02D010DD for device 2, but found JTAG ID code 0x00000000

I'm having a weird problem where i cant upload my design to the DE0-NANO board, gives me the weird error message which is the title of this question. Any other design uploads fine and I have done ...
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1answer
201 views

Implementation of NIOS Softcore alongwith HDL modules on Aletra Cyclone IVGX

My question is not on 'how can' but 'if can'. So I believe people with sufficient experience on any FPGA family might be able to help me out here. Problem Statement: I need to model a very basic ...
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1answer
894 views

Verilog outputting specific bit from register to output; getting constant 1's

I am trying to create an program that bit bangs a value from an FPGA to an arduino. In the module I created, every other clock cycle, the FPGAdata output should be set to the next bit of t. The ...
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2answers
625 views

Synthesizeable D Flip flop for FPGA

Having played around with Verilog for some time now, I decided to graduate to implementing designs on Alltera CycloneIV FPGA using the Quartus suite. Starting with a simple D flip flop, I face the ...
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2answers
2k views

FPGA non-volatile progamming

I recently bought a Cyclone II FPGA here. I have been able to program it with a USB Blaster cable and the Altera Quartus Software. The problem is that when I disconnect power, I lose the program. ...
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1answer
308 views

Cyclone V LVTTL GPIO Termination

On the DE1-SoC (from Terasic) schematic, I found 47 Ohm series resistors connected to GPIOs, they are using 3.3V VCCIO. The cyclone V datasheet show that no external termination is required as shown ...
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1answer
667 views

Possible causes of dead cyclone IV on custom board

i designed and soldered my first fpga board using cyclone IV in the 144 eqfp package. First of all, i made following mistakes: I am using 3.3V VCCIO for all IO banks. I misread the handbook and ...
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1answer
194 views

CycloneIV PCIe hard IP fixedclk_serdes generation

I'm trying to build a minimal design with PCIe on CycloneIV, and have trouble getting the core_clk_out to actually run. In the PCIe user guide, page 13-9, it says ...
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2answers
2k views

For a PLL Clock multiplier, where does the new clock come from?

If I understand it correctly, you use a PLL in an FPGA to get a higher clock from, say, a 50 MHz oscillator by synchronizing the faster clock to the slower reference one. Like if I had a 50MHz crystal ...
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1answer
897 views

Write an I2C code for Cyclone 2 architecture

I really need to I2C interface my FPGA with some slave device. I figured I could use the audio codec in my FPGA as a slave.I have gone through some codes from the internet for I2C. But I do not get ...
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1answer
5k views

Keypad Scanner Verilog code problem with state machine and column input

I am developing a Keypad both in hardware and Verilog using a DE2 Cyclone II board. I made a keypad using buttons (switches) that follows this schematic: The scanner works by setting the Column ...
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1answer
424 views

reuse Cyclone IV fpga Pasive serial configuration pin for SPI

Can i reuse pins DATA0 & DCLK in my application as FPGA SPI interface after configuration (PS) has been completed ? This are the dual purpose pin options: if i set "use as Regular I/O" , i will ...
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1answer
140 views

How to constrain fitter to assign signals to specific LE input in Quartus II?

I have noticed that the time delay through a combinatorial cell in an LE can depend significantly (up to .1 ns on my DE-0 Nano Cyclone IV board) on which input, A thru D, the input is assigned to. To ...
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2answers
1k views

FPGA outputs are always high with basic and/or program

So I am just getting started developing with an Altera Cyclone II EP265 mini board, and I am having some trouble getting a program that outputs the "and" and "or" of three inputs working. The full ...
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1answer
166 views

A simple VHDL circuit won't display initial value

Here is my code and it's pretty simple. I'm to cycle through the first 8 letters of the alphabet on a Altera Cyclone II board. ...
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0answers
982 views

Shematics of the BeMicro CV eval board from Arrow

Where can I find the complete schematics of the board? Arrow sells an ultra low cost FPGA platform with a Cyclone V device on it for around 30$. Ok, for that price it has the bear minimum: 2 buttons, ...
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1answer
1k views

Cyclone V FPGA SocKit - trying to use LCD from FPGA

I'm trying to use the LCD screen on a SocKit board with a Cyclone V FPGA. However, in the documentation I see that the chip is divided into an HPS and the FPGA and the LCD seems to be connected only ...
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1answer
4k views

Generate sine wave in VHDL, with the use of 10-bits DAC [closed]

I want to generate a sine wave with 20Mhz frequency, using a FPGA (Cyclone 3 EP3C10E) and an external 10bit DAC converter (http://www.analog.com/static/imported-files/data_sheets/AD7533.pdf). I have ...
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2answers
3k views

PCIe fails on “polling compliance” state

I am using the PCIe block of Altera Cyclone IV FPGA, and I have an issue whereby about half the PCIe slots I have tried (on three different computers) do not work. Debugging with SignalTap shows that ...
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1answer
1k views

JTAG Design for altera cyclone 3

I am designing the JTAG for a Altera Cyclone 3 (EP3C5E144C8N). I was only aiming at normal JTAG, and do not need Active Serial. I have attached the schematic and board in the *.zip file (http://www....
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2answers
443 views

symbols for ep3c5e144 and ep3c25e144 in Eagle

I am using ep3c5e144 to design a PCB board. Sadly, in Eagle I cant find the exact library and symbol for this device, but only its near relative ep3c25e144. I have some questions: How different is ...
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1answer
3k views

Altera: Change JTAG clock speed

I am having issues with JTAG with my Cyclone IV, specifically the JTAG clock. I am trying to change the JTAG clock frequency somewhere, but can't find where this is done in Quartus II. How can I ...
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1answer
1k views

Quartus II: Pin incompatible with a bank it is not on

I am using the pin planner of Quartus II to place my I/O signals on my Cyclone IV pins. I am stuck on the following fitter error: Error (169029): Pin adc0_in[0] is incompatible with I/O bank 3. ...