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Questions tagged [cyclone]

Cyclone is a family of FPGAs from Altera

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DisplayPort video into a Cyclone V FPGA

I designed a carrier board that has a Type6 COME module that outputs DisplayPort 2.1 to a Altera 5CGXFC7D6F27I7N Cyclone V FPGA. The FPGA firmware contains DisplayPort IP. I am having problems getting ...
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When does the tRAMP timing begin for Cyclone 5 Power Supplies?

I am currently designing a power supply setup for a Cyclone 5 FPGA. In the datasheet, it is stated that if power supplies do not reach operating conditions within the maximum tRAMP time allowed (100ms ...
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Issue with Running Two Separate Codes on Intel Cyclone V SoC ARM Cortex A9 Dual Core via QSPI

I am working on an Intel Cyclone V SoC ARM Cortex A9 Dual Core setup and aiming to execute two distinct codes on Core 0 and Core 1 in bare-metal mode. While I've successfully executed this setup using ...
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Assistance Needed: Trouble Running Bare-Metal Code on second core in Cyclone V SoC

I am working on intel cyclone 5 hps I have two cores in a processor Core 0 core 1, I want two code to run on two different cores core 0 and core 1 in bare metal. When I run in jtag mode it works, for ...
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Cyclone III FPGA 16x2 LCD repeat one character instead of displaying complete word

So I am trying to use the LCD on the cyclone III FPGA. I have written this verilog code that should display numbers 0 to 9 then letters A to G Compiling the code has no errors at all However, when ...
Mahmoud Khodier's user avatar
4 votes
1 answer
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Debuging verilog SDRAM controller

I've been working on a project that involves the creation of a SDRAM Controller in verilog for an Altera DE2 prototyping board. Despite reading the documentation for the memory chip on the board, ...
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Change clock frequency from 50MHz to 40MHz using Altera Cyclone IV and Quartus Lite 20.1

I'm using the FPGA board EasyFPGAv2.2 which have Altera Cyclone IV with chip EP4CE6E22C6 and I made a verilog program to generate VGA 640x480 60Hz signal. It works great dividing 50MHz by 2 generating ...
Yury Euceda's user avatar
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Syntax Help: VHDL Syntax Error at *.vhd near text ["process", "behave"] expecting "if"

Problem I'm developing a simple LED blinking system in Quartus Prime Lite 18.1 to be instantiated on a DE0-Nano development board that makes use of the Cyclone IV E generation of Intel FPGAs. To do so ...
Mark Musil's user avatar
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1 answer
141 views

Intel FPGA input voltage between Vil and Vih : what's happening?

Considering these settings: Cyclone 10 LP (or Cyclone II / Cyclone III / Cyclone IV) IO configured as Input LVTTL 3.3V (Vilmax=0.8V Vihmin=1.7V) Voltage between 0.8V and 1.7V on this input No CLK ...
zian's user avatar
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FPGA counter value unstabillity

I have been building a synchronized I2C slave receiver with Verilog. The I2C slave receiver did not encounter any issues when I simulated it with Modelsim. However, it does not function properly ...
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1 answer
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FPGA starts working after irrelevant changes, why?

I have written a UART module in Verilog. By using that module I get data from PC via UART and then send that data back again via this UART module. I uploaded it to FPGA for testing. It works flawless ...
Rehin's user avatar
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2 answers
279 views

Why are registers being turned on to 1 before reset/on button is hit on FPGA?

I am writing a really simple program on Verilog for my FPGA to have an LED blink once a button is pushed. Here is the code I have written: ...
Lokwill's user avatar
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Why is my seconds counter in verilog jumping values behaviour?

I am implementing a seconds counter on the Altera DE-1 Educational Board powered by the old Cyclone 2 FPGA. My plan is to make a 'down-clocker' that takes the on-board 50 MHz clock and produces a 1 Hz ...
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My JTAG connection with Cyclone IV is not working

My FPGA board is not programming. I think I have followed all the guide lines for JTAG connection. Can you see any problems with this connection?
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What's wrong with this schematic for powering up Cyclone IV FPGA?

I have followed all the guide lines for powering up the Cyclone IV. However, the 3.3v Regulator is heating too much and also the Cyclone IV FPGA. What's wrong with my schematic? Is there a problem in ...
Alpha0's user avatar
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Identify valid FPGA configuration image in serial flash device?

How can I know if there's valid FPGA configuration image in the specific location of the serial configuration device before I perform reconfiguration and experience successful or faulty attempt? ...
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Altera Cyclone II Quartus II JTAG Programming Error

I'm trying to program a Cyclone II I bought here using Quartus II 13.0sp1 on Arch Linux. I'm trying to program it with a very simple Verilog program with three inputs and two outputs and a few simple ...
Chris Loonam's user avatar
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How to implement an ADPLL in Verilog that locks onto an arbitrary sine wave? [duplicate]

I'm unable to figure out how to implement an ADPLL on an FPGA that can take in an arbitrary periodic input and lock onto its frequency (some finite range is okay) and phase. A square wave output will ...
thebionicandroid's user avatar
2 votes
2 answers
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How to open up serial terminal for my USB device converter (or, how to enable VCP in linux)?

I am using a new Cyclone V SoC board by Enclustra (Mercury+ SA2) mounted on their PE-1 BaseBoard. To connect to the board serially on Windows platform, I have to connect the board which is detected ...
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What is the minimal schematic (needed capactiors/resistors) to use FPGA Altera Cyclone 4 EP4CE6E22C8N? [closed]

I can't find any information about how wire the Cyclone 4 FPGA. I do not want to use development boards.
Alpha0's user avatar
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Change memory content of FPGA SoC (DE1-SoC) using software while .sof (EPCQ) is running on FPGA

I am new to FPGA and FPGA-SoC world. I have a DE1-SoC board. I am doing a project. Hardware design of the project contains a memory block which is initialized using .mif file. I know that we can use ...
Adhamzhon Shukurov's user avatar
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How can I transfer data to cyclone 4?

I have the fpga below, I managed to implement a couple of simple designs. According to the manual it should be possible to foward data from my laptop to the fpga using the usb-blaster cable, I cannot ...
user8469759's user avatar
5 votes
2 answers
2k views

Altera Cyclone V - Linux & FPGA interrupt handling

I need to propagate an interrupt from my custom FPGA IP core to the HPS system of a DE0_nano_SoC (Cyclone V HPS-FPGA architecture) and handle in Linux. I have googled quite a lot to confidently say ...
new_stacker's user avatar
2 votes
1 answer
4k views

Error (209015): Can't configure device. Expected JTAG ID code 0x020B10DD for device 1, but found JTAG ID code 0x000210DD

I bought from ebay Altera Cyclone II EP2C5T144 development board. It came with USB Blaster. I'm using Quartus II 13.0sp1. FPGA is programmed with default settings as it should be (flashing onboard ...
Boo1eu9's user avatar
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2 votes
1 answer
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FDCE flip-flop primitive in Altera Quartus?

I would like to know the Altera Quartus primitive equivalent to the FDCE flip-flop on Xilinx ISE. I think that the DFFE primitive might work, however, I am not sure about the CE and CLR pins ...
artificer's user avatar
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On Cyclone II FPGAs can I apply voltage directly on input pins?

On Cyclone II FPGAs can I apply voltage directly on input pins, maybe taking it from a Vcc pin? Or should I use a resistor? The Altera DE2 board's schematics below looks like some input switches don'...
artificer's user avatar
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VHDL error: multiple constant drivers for net

I can't find how to deal with the error: "multiple constant drives" which occures when I try to read and set the same net in a single process. I need to set the "output" for some clock cycles on the ...
dwEprew's user avatar
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Why would IO pins be tied to VCC or GND with 0 Ohm resistor on FPGA Dev Board?

I have a cheap Altera Cyclone II EP2C5T144C8 Dev Board and a few (4) of the IO/LVDS pins are shorted to VCC or GND as shown in the schematic segment below. The pins are also brought out to headers on ...
ks0ze's user avatar
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3 votes
2 answers
7k views

FPGA Memory vs Registers

I'm having an issue on an FPGA project I'm working on. I'm unable to write to defined memories within the FPGA, but writing to registers works fine. I was thinking about working around this problem by ...
Peyton B's user avatar
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Failing to program Cyclone IV GX device via JTAG

I just got the aforementioned device and, upon writing a simple program (it compiles) and going into Programmer, when I try to program the device with the .sof file, I see is ...
Dmitri Nesteruk's user avatar
2 votes
2 answers
1k views

Cyclone V external memory group pins DQ/DQS

I'm trying to understand the functions of external memory pins in Cyclone V (5csema5af31c6n) I do understand that colums HMC Pin Assignment for DDR3/DDR2/LPDDR2 shows pin functions for external ...
Vlad Timofeev's user avatar
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1 answer
2k views

Output CLOCK signal to GPIO pin of CYCLONE IV E

I am new to FPGA and I am trying to send a CLOCK signal as an output of a GPIO pin of an Altera Cyclone IV E. I first made a program: ...
Adaptive's user avatar
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619 views

Adaptative Logic Module : Logic Element equivalence

I have implemented some circuitry with Quartus on a Cyclone 5 FPGA. This has be done for my master thesis. I have to justify wether the number of logic element used by my implementation is "expected" ...
user1382272's user avatar
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Error (209015): Can't configure device. Expected JTAG ID code 0x02D010DD for device 2, but found JTAG ID code 0x00000000

I'm having a weird problem where i cant upload my design to the DE0-NANO board, gives me the weird error message which is the title of this question. Any other design uploads fine and I have done ...
Serge's user avatar
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2 votes
1 answer
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Implementation of NIOS Softcore alongwith HDL modules on Aletra Cyclone IVGX

My question is not on 'how can' but 'if can'. So I believe people with sufficient experience on any FPGA family might be able to help me out here. Problem Statement: I need to model a very basic ...
sherinkapotein's user avatar
1 vote
1 answer
2k views

Verilog outputting specific bit from register to output; getting constant 1's

I am trying to create an program that bit bangs a value from an FPGA to an arduino. In the module I created, every other clock cycle, the FPGAdata output should be set to the next bit of t. The ...
Eric Johnson's user avatar
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2 answers
876 views

Synthesizeable D Flip flop for FPGA

Having played around with Verilog for some time now, I decided to graduate to implementing designs on Alltera CycloneIV FPGA using the Quartus suite. Starting with a simple D flip flop, I face the ...
sherinkapotein's user avatar
3 votes
2 answers
3k views

FPGA non-volatile progamming

I recently bought a Cyclone II FPGA here. I have been able to program it with a USB Blaster cable and the Altera Quartus Software. The problem is that when I disconnect power, I lose the program. ...
Eric Johnson's user avatar
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1 answer
519 views

Cyclone V LVTTL GPIO Termination

On the DE1-SoC (from Terasic) schematic, I found 47 Ohm series resistors connected to GPIOs, they are using 3.3V VCCIO. The cyclone V datasheet show that no external termination is required as shown ...
HochKonik's user avatar
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4 votes
1 answer
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Possible causes of dead cyclone IV on custom board

i designed and soldered my first fpga board using cyclone IV in the 144 eqfp package. First of all, i made following mistakes: I am using 3.3V VCCIO for all IO banks. I misread the handbook and ...
Arnost's user avatar
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2 votes
1 answer
221 views

CycloneIV PCIe hard IP fixedclk_serdes generation

I'm trying to build a minimal design with PCIe on CycloneIV, and have trouble getting the core_clk_out to actually run. In the PCIe user guide, page 13-9, it says ...
Simon Richter's user avatar
3 votes
2 answers
3k views

For a PLL Clock multiplier, where does the new clock come from?

If I understand it correctly, you use a PLL in an FPGA to get a higher clock from, say, a 50 MHz oscillator by synchronizing the faster clock to the slower reference one. Like if I had a 50MHz crystal ...
Zephyr's user avatar
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-2 votes
1 answer
1k views

Write an I2C code for Cyclone 2 architecture

I really need to I2C interface my FPGA with some slave device. I figured I could use the audio codec in my FPGA as a slave.I have gone through some codes from the internet for I2C. But I do not get ...
Muthu Subramanian's user avatar
1 vote
1 answer
7k views

Keypad Scanner Verilog code problem with state machine and column input

I am developing a Keypad both in hardware and Verilog using a DE2 Cyclone II board. I made a keypad using buttons (switches) that follows this schematic: The scanner works by setting the Column ...
roro172's user avatar
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1 answer
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reuse Cyclone IV fpga Pasive serial configuration pin for SPI

Can i reuse pins DATA0 & DCLK in my application as FPGA SPI interface after configuration (PS) has been completed ? This are the dual purpose pin options: if i set "use as Regular I/O" , i will ...
Cristian Mardones's user avatar
-1 votes
1 answer
163 views

How to constrain fitter to assign signals to specific LE input in Quartus II?

I have noticed that the time delay through a combinatorial cell in an LE can depend significantly (up to .1 ns on my DE-0 Nano Cyclone IV board) on which input, A thru D, the input is assigned to. To ...
Andrew's user avatar
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1 vote
2 answers
1k views

FPGA outputs are always high with basic and/or program

So I am just getting started developing with an Altera Cyclone II EP265 mini board, and I am having some trouble getting a program that outputs the "and" and "or" of three inputs working. The full ...
aftrumpet's user avatar
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1 vote
1 answer
182 views

A simple VHDL circuit won't display initial value

Here is my code and it's pretty simple. I'm to cycle through the first 8 letters of the alphabet on a Altera Cyclone II board. ...
aeolus's user avatar
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1 vote
0 answers
1k views

Shematics of the BeMicro CV eval board from Arrow

Where can I find the complete schematics of the board? Arrow sells an ultra low cost FPGA platform with a Cyclone V device on it for around 30$. Ok, for that price it has the bear minimum: 2 buttons, ...
Blup1980's user avatar
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2 votes
1 answer
1k views

Cyclone V FPGA SocKit - trying to use LCD from FPGA

I'm trying to use the LCD screen on a SocKit board with a Cyclone V FPGA. However, in the documentation I see that the chip is divided into an HPS and the FPGA and the LCD seems to be connected only ...
MA81's user avatar
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