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Questions tagged [ddr]

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22
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3answers
5k views

Why does RAM (any type) access time decrease so slowly?

This article shows that DDR4 SDRAM has approximately 8x more bandwidth DDR1 SDRAM. But the time from setting the column address to when the data is available has only decreased by 10% (13.5ns). A ...
1
vote
1answer
308 views

Data Strobe in DDR memory

In DDR3 memory there is a signal called DQS that I have several question about. What is DQS abbreviated for? specially Q What is the purpose of data strobe in DRAM and why not use simple clock. Is ...
0
votes
1answer
34 views

Using narrower DDR RAM than controller

I have some ARM processor that have 72-bit width (8 for ECC) RAM controller. Can I buy eg. two 32bit chips and combine them? If yes then how? Can I buy just one 32bit and pull down rest of data pins ...
0
votes
1answer
51 views

DDRx timing analysis

I have a question regarding timing analysis for DDR3 and DDR4 signals. How do we do timing analysis to see if all setup and hold requirements are fulfilled correctly, considering they have write ...
16
votes
2answers
4k views

Why use DDR instead of increasing clock speed?

Why would you want to use DDR ram and read/write on every rising and falling edge of the clock instead of just doubling your clock speed and read/write on just one of either the rising or falling edge?...
1
vote
1answer
62 views

DRAM memory organisation

I've been trying to understand the working of DRAM chips but apparently in a lot of confusion. Suppose there are 8 banks in a single chip on a module. Is it only one bit that comes out of a single ...
0
votes
1answer
52 views

how is ddr4 controlled on the laptop

I am a student of electrical engineering and my previous term's project was implementing ddr2 SDRAM with Xilinx FPGA, but I am interested to know which device on the laptop control ddr4 on it? and ...
2
votes
0answers
161 views

DDR2 and DDR3 ODT and ZQ calibration

Can anyone please explain what is the difference in ODT and ZQ technique used in DDR2 and DDR3?? Which method is very useful for DDR2 termination? whether ODT or External parallel termination?? ...
0
votes
1answer
50 views

what is the difference between D and D/L flip-flops?

I'm trying to understand how a DDR receive circuit works. I'm reading the MachXO2 Family Data Sheet, page 22: http://www.latticesemi.com/view_document?document_id=38834 What I don't get is this: ...
0
votes
2answers
209 views

Inserting an FPGA on a MIPI camera lane [closed]

I have a processor which accepts MIPI data. However, the problem is I want to perform some processing on this data and the IMX6 is not fast enough to do this in real time. I was wondering what is the ...
2
votes
1answer
97 views

DDR Trace Length Inside Package from Simulation Model

The DDR4 in question is a Micron MT40A512M16JY. From the vendor site, you can get the datasheets, specs, sim models. I assume from the sim models you should be able to see the trace length of each ...
2
votes
1answer
337 views

DDR4 pull-up resistors and decoupling clock lines

I am trying to understand the layout of a DDR4 chip connected to a FPGA. The schematic follows: I tried to look for datasheets from the memory manufacturer explaining how to properly pull-up or pull-...
1
vote
1answer
157 views

Is there a rule for DDR4 CA signals reference plane?

I'd like to know if there is any rule for the reference plane of DDR4 CA signals in PCB layout. I saw some design guide which specify the reference plane to be VDDQ power plane for CA signals, but I'm ...
2
votes
1answer
77 views

MachXO2 DDR and PCLK routing issue

I'm doing a project in which I use DDR interfaces to transmit and receive data between different FPGAs. The FPGA transmitter will send data at 125 MHz and the receiver will use 250 MHz to sample the ...
4
votes
3answers
376 views

Parallel access to memory with multiple DDR4 chips

Some development boards have multiple DDR4 chips. Does it imply that such boards have multiple DDR controllers and memory can be accessed in parallel. For example this boards: https://www.xilinx.com/...
0
votes
1answer
269 views

DDR3 memory transfer rate

I am trying to understand memory transfer rate while working with DDR3. I am getting different numbers. For example, in Wikipedia https://en.wikipedia.org/wiki/DDR3_SDRAM DRAM has peak transfer rate ...
1
vote
1answer
348 views

Theoretical calculation of DDR3L transfer speed

I am not sure if this questions belongs to this stack exchange site but I didn't find other better one. In case it doesn't, let me know and I will move it to some other place. I am working with a ...
2
votes
1answer
398 views

DDR4 differential pair routing guideline

I have a question about the DDR4 trace routing on the server main board. For clock and DQS signals, are they both considered differential signals? I checked the Intel PDG; it shows that two specs ...
0
votes
1answer
150 views

PIC32MZ DA Separate DDR grounding

I am puzzling over the purpose of ferrite beads and grounding on the PIC32MZ DA starter kit. On page 34 of the User Guide it shows L2 and L3, and a separate Ground and power net. It would appear ...
3
votes
1answer
125 views

How might an LPDDR2 PHY be designed?

I was reading the LPDDR2 spec today out of curiosity. While browsing the spec I became curious about "how might one hypothetically design a minimal working LPDDR2 PHY on paper/for simulation, perhaps ...
1
vote
2answers
2k views

What's the standard procedure of DDR4 training?

I have a question about DDR4 training sequence, and hope someone can give me some information. As I know, there will be training sequence at system boot. (In my system, it's called 1D/2D training, ...
3
votes
1answer
69 views

Electrical principle of row hammer glitch

There is a fairly new and exploitable bug happening in some DDR3 DRAMs called the "row hammer" in which it's possible to bit flip memory cells. I understand how the exploit works, but not the ...
2
votes
2answers
240 views

Understanding DDRn SDRAM

So I am basically trying to grasp/confirm my grasp of SDRAM and DDR. So basically I understand that there is going to be some chips each with up to 8 banks (so kinda like 8 chips internally?). For ...
3
votes
2answers
123 views

LPDDR2 clock long term jitter issue

I have a problem with LPDDR2 clock period cumulative error measurement tERR(11-50per) but shorter length measurement are OK with some margin. I'm looking at some cause or tips to understand or fix ...
0
votes
1answer
64 views

Choose “safe” section of DDR memory in ZC702 board

I can not fully understand what section of the available external memory is safe to assign for a VDMA on the ZC702 board. I need to dedicate 4MB of memory for the three frames (640*480* 4bytes * 3 ...
1
vote
1answer
687 views

LPDDR2 reference design?

I've been trying to interface LPDDR2 ram with my SOC but got confused as to how to connect the CA lines. Does anyone have any reference designs of LPDDR2 for me to go off of?
1
vote
1answer
356 views

lpddr2 interface differences between different memory controllers?

The way LPDDR2 connections are done with CA bus is different between these two processors. I thought since LPDDR2 is a JEDEC standard, these schematics should be interfacing with the same lines from ...
0
votes
2answers
97 views

Combining decoupling capacitors for sensitive power requirements in LPDDR

I've been looking through a bunch of designs I found online on LPDDR2 interfacing. What's always confused me is the parallel decoupling capacitors. Why have so many vs just combining that to what you ...
6
votes
2answers
800 views

Weird 240 ohm resistor on zq line to DDR

I've been looking at schematics that interface ddr ram and noticed a weird notation for their zq pull down resistor. What is with the dot at the top as well as the 1%? Haven't seen this before.
5
votes
1answer
483 views

What is the difference between LPDDR2-S2 vs S4?

Looking at page 18 of the JEDEC spec on LPDDR2 LPDDR2-S2 also uses a double data rate architecture on the DQ pins to achieve high speed operation. The double data rate architecture is essentially a ...
2
votes
1answer
293 views

What is the more frequent error in DDR Memory?

this is about DDR memory data corruption and not about STUCK address or data lines. If we have a good DDR with no memory stuck issues and we perform lots of writes and reads which type of error is ...
-2
votes
1answer
89 views

Does a DDR RAM device exist which would allow RAM to be removed and preserved? [closed]

Hello I would like to know if there any device which could preserve content of RAM once removed from a host system and this special device could be connected perhaps by way of USB to another machine ...
-4
votes
1answer
797 views

Moving a large dataset from the PS to PL on a zynq device?

I am at the moment trying to interface with DRAM on my Xilinx Zynq device such that I am capable of moving a large amount of data from the processing system (PS) side to the programmable logic (PL). ...
2
votes
1answer
624 views

What is traffic generator (while using Xilinx Memory Interface Generator)

I am trying to use the Memory controller Block in my Xilinx Spartan 6 FPGA to set up an interface with LPDDR memory. I read the MCB User guide, and I am quite clear about how it works, and how I would ...
3
votes
0answers
515 views

Timing constraints for DDR output multiplexer

Consider the following circuit, which multiplexes the d0 and d1 inputs to the y output in ...
1
vote
0answers
152 views

GDDR Power Calculation

I'm wondering if there is any publicly available documents or research papers that cover GDDR power estimation? Micron provides very nice documentation and calculators for DDR up to DDR4, however I ...
3
votes
1answer
681 views

DDR4 frequency decrease if populated with more than one module per channel

I'm curious how one particular company Gigabyte ensures its server motherboards to run at the maximum supported memory frequency even when there're two or three DIMMs per channel (of coure we're ...
5
votes
1answer
297 views

how does this differential ddr receiver work?

I'm looking at this simple schematic trying to understand how a DDR SSTL receiver works (the one on the left). I get that the input voltage will be compared to Vref and the output will be a ...
2
votes
0answers
766 views

Why DDR3 RAS timing have to be greater than RCD + CAS timing?

By definition, tRAS is the minimum delay from when a particular row in a bank is activated, to when it can be closed with a PRE command. I have seen claims numerous times that tRAS should be > tRCD + ...
0
votes
1answer
557 views

DDR interface - SSTL termination

I have a question regarding the DDR SSTL termination. The JEDEC Standard (JESD8-9B) about the SSTL Interface for DDRs shows two possible termination methods, class I with single parallel termination ...
3
votes
1answer
337 views

What references cover DDR3 layout considerations?

I'm looking for succinct yet correct guidelines for evaluating a DDR3 memory PCB layout. I know that trace length matching, via style and back-drilling, and signal grouping all matter. I know that ...
5
votes
2answers
772 views

waveforms showing effect of trace-length matching for SHORT ddr/ddr2/ddr3 traces?

I've seen lots of waveform plots that illustrate the beneficial effect of things like on-die termination, and the effect is unmistakable. For example, see page 6 of this Micron technical note. I'm ...
2
votes
1answer
430 views

Zedboard 512x512 matrices, % utilization problem

My objective is to read seven 512X512 float matrices from the SD card to the DDR memory (step accomplished already with each matrix occupying around 1Mb), then pass them from DDR to my custom IP block ...
1
vote
1answer
3k views

MM2S simple transfer gone wrong

I followed some examples and I already managed to make a big S2MM (stream to memory-mapped) transfer via an AXI DMA. However, now I'm trying the reverse, i.e. to make a simple MM2S transfer to a very ...
0
votes
1answer
376 views

Understanding Address Map

Please refer to this image of page 113 of this manual I'm not understanding this table. From what I can tell, I have from 0010_0000 to 3FFF_FFF of DDR memory, which is 1 072 693 247 bytes and ...
0
votes
1answer
121 views

Memory address 32-bit

I'm working with a Zedboard and I'm printing to the screen memory addresses of consecutive 32-bit float numbers. So the print generates this: ...
-1
votes
1answer
2k views

how to calculate capacity of the ddr address line

i see the micron data sheet 8-GB,4-GB and 1-GB the address lines are 16,15,13 my question is how to calculate the capacity of the (double data rate type three synchronous dynamic random-access memory ...
-1
votes
1answer
644 views

How does Xilinx MIG AXI interface map to DDR PHY pinout?

At the bottom of page 156 of UG586 I can understand how the User Address maps to the PHY pinout. However, I can't understand page 155 of the same manual. How does the 32-bit Microblaze address space ...
1
vote
2answers
5k views

In an SDRAM how do address rows/columns and rank width and bank width relate to the total memory size?

I have a Micron SDRAM (MT16KTF1G64HZ-8GB). The size of the memory is 8GB. I did some calucaltions and 8GB of data means 2^36 bits capacity. Now when I look in the Micron data sheet, the row address is ...
1
vote
2answers
864 views

Series Termination DDR

I was Going through some application notes for the placement of Series termination of DDR and found it should be placed near to the processor. But if I am not wrong termination resistor are placed to ...