Questions tagged [ddr]

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C code for DDR Access in Xilinx SoC devices

In my design, I want to write to DDR and then I want to fetch the data from DDR memory and then pass them to FPGA to be processed, after that, the data will be written back to DDR memory.I am using ...
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67 views

Calculating RAM memory capacity from schematic symbol

Is it possible to calculate the memory capacity of a RAM given its schematic symbol? I made a first guess from an example but seems to be incorrect: If the address bus is 15-bit width, there are a ...
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Fast DDR4 on a slow bus [closed]

A PC manufacturer's manual reads: MEMORY SPECIFICATIONS Speed: 3200 MHz operates at 2667 MHz for Intel 10th Generation. Configurations supported: 8 GB DDR4 at 2667 MHz (1 x 8 GB); 32 GB DDR4 at 2667 ...
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1answer
37 views

SystemVerilog usage of always_ff and fork join

The module is data central to setup the addr/data/command for set_cmd_pins() method, which is to translate these commands to pin-level signals which are a pair of methods to setup the DQS and DQ pin ...
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1k views

Is ECC feature in DDR realized with using Hamming code technique?

The fundamental formula for a Hamming coding is as below: 2^k≥n+k+1 Where k = # of parity bits and n = data bits In a DDR system with ECC feature, every data byte will generate an additional ECC bit ...
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1answer
51 views

Why do DDR RAMs have both xDQ and xDM signals?

DDR2 RAMs have these control signals RAS, CAS - address strobes UDQ, LDQ - byte strobes WE - write enable UDM, LDM - write mask Why do we need UDM and LDM? Can't you write a byte by asserting WE and ...
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3answers
148 views

what is the most difficult part of creating a DDR2 or DDR3 memory controller inside an FPGA?

In this day and age we can just use the memory IP provided to us by the FPGA vendor be it a soft IP or hard IP. This makes it almost trivial to communicate with high speed memory devices like DDR2 and ...
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3answers
91 views

DDR: Is the real maximum speed half of what is advertised in datasheets?

Let's take a single 8-bit 200MHz DDR chip. All datasheets state that bandwidth is "up to" 400MB/s. Because it's dual, data is read/written on both edges so yes, theoretical, it's 400MB/s. ...
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1answer
32 views

ddr: Is there any significant delta between the different strobes?

In a DDR memory, during a read, output data from the DDR is aligned on the strobe. There is one strobe per 8-bit: UDQS/LDQS for a 16-bit-wide DDR DQS[0-3] for a 32-bit-wide DDR Is there any ...
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1answer
80 views

No terminations on point to point DDR3?

Are terminations required for DDR3 in point to point designs? I saw a reference design that doesn't include any termination to VTT for a controller/single DRAM design (pt to pt). DQS, DM and DQ use ...
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32 views

DDR3 AC characteristics

What is the meaning behind different AC input levels such as AC120, AC135, AC175 etc? I understand that AC_X means the level is Vref + X mV. And I also understand that the setup time is defined with ...
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DDR4 Refresh VPP Power Consumption

My question may seem stupid but for a REFRESH operation on a single-rank DDR4 with multiple DRAM devices, how to properly estimate the DRAM power consumption ? I tried to use Micron Power Calculator ...
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1answer
219 views

DDR3 pcb design routing

I am trying to layout DDR3 128MB chip and a Spartan-6 FPGA. DDR signal pins located on specific memory controller pins and could not be swapped. I've never done DDR routing and went with SP605 Xilinx ...
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1answer
76 views

There is a way to write into FIFO on both clock edges?

Im using Lattice ECP3 FPGA, didnt found any information about it on the internet. I have ADC which providing me 12bits data on both clock edges, so I used Lattice High Speed I/O Interface: This ...
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1answer
163 views

Why cant clock be directly used instead of DQS in DDR during read and write

I have been reading about DDR lately and I am not able to understand the exact use of the DQS signal. The timing diagrams show dqs in phase with clock so why cant the clock only be used for the write ...
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1answer
114 views

Lattice FPGA problems with built-in DELAY module

I'm trying to delay an input data coming from ADC component in DDR to my FPGA, afterwards output it in the clock rising edge. The ADC Im using: ADS5463: Im using Lattice ECP3 FPGA, based on the fpga ...
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2answers
80 views

How to Output DDR data to 1 register

I have an Input which provides DDR data, I need to capture it and output it from the FPGA in one register (12bit). How can I do it? What I did for now is to capture the input data with always block ...
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1answer
51 views

What if ddr4 Termination is done at last word component

Memory Component : MT40A256M16 Controller : Xilinx MPSOC - PS Side Question : I have mistakenly provided the DDR4 termination resistances at the first data lane and the layout engineer has completed ...
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1answer
120 views

DDR4 board bringup issue

I am struggling with a DDR4 related board bringup issue. Can anyone out there recognise what the problem is by studying the attached memory dumps? The memory dump is from Preboot loader PB31 area of ...
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8 WCK toggles for Write Leveling in LPDDDR5

What is purpose of having 8 toggles on WCK for Write Leveling in LPDDR5? First toggle of WCK may be ignored due to instability by DRAM. And the DRAM feed-backs phase relationship of last WCK-CK on DQ. ...
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1answer
136 views

ADC with parallel DDR LVDS interface and also a parallel CMOS interface

The ADS4126 is a 12-Bit, 160-MSPS Analog-to-Digital Converter (ADC). Its data rate is too high for it to be read out using something like SPI or I2C. It does use SPI for control purpose though. The ...
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2answers
182 views

DDR Interface Protocol

I have seen and worked with interfaces like SPI and I2C. However, when I started to learn about DDR interface/communication protocol, I want to understand like how many lines, what are the important ...
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DRAM Memory Lines

I have been trying to understand DDR and DRAM memories and stumbled upon this video In this video, from 20:00 to 23:00 he tells that the 8kb row buffer lines, actually come out as 64b and this 64b ...
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1answer
62 views

What is voltage level in DDR5 defined by JEDEC?

Voltage level in DDR4 is 1.2 volt, will it be same in DRR5 also? Also how much maximum voltage fluctuation will be allowed?
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1answer
88 views

Why DDRx I/O bus frequency is half effective frequency?

I've already known that I/O buffer transfers data on both the rising and falling edges of the clock signal. But it really confused me why I/O bus frequency is half of effective frequency. For ...
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2answers
1k views

What is the difference between DRAM channel and DRAM Rank?

Can someone explain me the terms : DRAM Rank and a DRAM Channel is simple terms. I went through this PDF and I was not able to understand the DRAM Organisation/architecture on page 3 and page 11. Can ...
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1answer
58 views

What is the theoretical throughput limit of DDR SDRAM read only

I wonder how fast I can read from a DDR SDRAM (known as DDR1) clocked at 200MHz. The controller will be implemeted on an FPGA. I have 8 bit data interface to the DDR. Each data pin reached 400Mbps. ...
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102 views

DDR3 RAM - possible Row Hammer

Tl; Dr; I make a lot of reads to a RAM, physically incrementing the address and get more errors every time i restart the read process on address 0x0. Is this the Row-Hammer ? I made a question ...
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1answer
113 views

Can I run a DDR4 module at 50 MHz?

I haven't seen any restrictions about minimum clock, but I may have overlooked them. EDIT: The module is a Crucial CT4G4SFS824A, based (this is an informed guess) on 4Gb Micron 512 Meg x 8
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1answer
83 views

Why do we have single ended DQ and differential DQS in DDRIO?

if differential can reduce cross talks, why do we use single ended DQ? And we know DQS is differential from DDR2
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1answer
399 views

why pre-post amble is required?

why do we need pre-post amble for READ or WRITE DQS ? 1 ) one reason could be --> Because transitions of voltages from logic level 0 to 1 or 1 to 0 take time to complete: so the strobe is asserted a ...
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2answers
174 views

DDR UDQS and LDQS into one DQS controller

I have one x16 memory chip () that has two Data Strobe pairs (UDQS and LDQS), on the other hand, I have arm chip (i.MX6 ULZ) that has one Data Strobe pair (DQS). Is there any way of connecting them, I'...
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2answers
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High speed interfaces and FPGAs [closed]

Please excuse me if my question is very naive or broad. I just wanted to get some direction. I didn't know how else to ask for help. I am working on Analog electronics and MCUs. It seems to be ...
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0answers
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Altera/Intel FPGA Interfacing External Memory

I am in the process of making a prototype PCB with an Altera Cyclone IV or V FPGA and 2 channels of external memory, one channel for a softcore CPU and one channel for a 2d graphics accelerator. I ...
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3answers
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Why does RAM (any type) access time decrease so slowly?

This article shows that DDR4 SDRAM has approximately 8x more bandwidth DDR1 SDRAM. But the time from setting the column address to when the data is available has only decreased by 10% (13.5ns). A ...
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Data Strobe in DDR memory

In DDR3 memory there is a signal called DQS that I have several question about. What is DQS abbreviated for? specially Q What is the purpose of data strobe in DRAM and why not use simple clock. Is ...
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1answer
50 views

Using narrower DDR RAM than controller

I have some ARM processor that have 72-bit width (8 for ECC) RAM controller. Can I buy eg. two 32bit chips and combine them? If yes then how? Can I buy just one 32bit and pull down rest of data pins ...
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1answer
150 views

DDRx timing analysis

I have a question regarding timing analysis for DDR3 and DDR4 signals. How do we do timing analysis to see if all setup and hold requirements are fulfilled correctly, considering they have write ...
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2answers
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Why use DDR instead of increasing clock speed?

Why would you want to use DDR ram and read/write on every rising and falling edge of the clock instead of just doubling your clock speed and read/write on just one of either the rising or falling edge?...
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1answer
123 views

DRAM memory organisation

I've been trying to understand the working of DRAM chips but apparently in a lot of confusion. Suppose there are 8 banks in a single chip on a module. Is it only one bit that comes out of a single ...
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1answer
72 views

how is ddr4 controlled on the laptop

I am a student of electrical engineering and my previous term's project was implementing ddr2 SDRAM with Xilinx FPGA, but I am interested to know which device on the laptop control ddr4 on it? and ...
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248 views

DDR2 and DDR3 ODT and ZQ calibration

Can anyone please explain what is the difference in ODT and ZQ technique used in DDR2 and DDR3?? Which method is very useful for DDR2 termination? whether ODT or External parallel termination?? ...
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1answer
117 views

what is the difference between D and D/L flip-flops?

I'm trying to understand how a DDR receive circuit works. I'm reading the MachXO2 Family Data Sheet, page 22: http://www.latticesemi.com/view_document?document_id=38834 What I don't get is this: ...
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2answers
302 views

Inserting an FPGA on a MIPI camera lane [closed]

I have a processor which accepts MIPI data. However, the problem is I want to perform some processing on this data and the IMX6 is not fast enough to do this in real time. I was wondering what is the ...
2
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1answer
129 views

DDR Trace Length Inside Package from Simulation Model

The DDR4 in question is a Micron MT40A512M16JY. From the vendor site, you can get the datasheets, specs, sim models. I assume from the sim models you should be able to see the trace length of each ...
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1answer
1k views

DDR4 pull-up resistors and decoupling clock lines

I am trying to understand the layout of a DDR4 chip connected to a FPGA. The schematic follows: I tried to look for datasheets from the memory manufacturer explaining how to properly pull-up or pull-...
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1answer
276 views

Is there a rule for DDR4 CA signals reference plane?

I'd like to know if there is any rule for the reference plane of DDR4 CA signals in PCB layout. I saw some design guide which specify the reference plane to be VDDQ power plane for CA signals, but I'm ...
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1answer
129 views

MachXO2 DDR and PCLK routing issue

I'm doing a project in which I use DDR interfaces to transmit and receive data between different FPGAs. The FPGA transmitter will send data at 125 MHz and the receiver will use 250 MHz to sample the ...
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3answers
609 views

Parallel access to memory with multiple DDR4 chips

Some development boards have multiple DDR4 chips. Does it imply that such boards have multiple DDR controllers and memory can be accessed in parallel. For example this boards: https://www.xilinx.com/...
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1answer
617 views

DDR3 memory transfer rate

I am trying to understand memory transfer rate while working with DDR3. I am getting different numbers. For example, in Wikipedia https://en.wikipedia.org/wiki/DDR3_SDRAM DRAM has peak transfer rate ...