Questions tagged [ddr]

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75 views

LPDDR: is pluggable (socketed, not soldered) connection possible for low voltage?

I've already asked the question about plausibility of socketed LPDDR here and got an answer LPDDR on separate replaceable modules / boards - possible? drawbacks? You could probably extend LPDDR onto ...
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DDR3 vs DDR4: design differences

Based on the anandtech article about DDR3, DDR3 has Ranks and each rank consists of 8 ICs and these ICs is a stack of banks (terms from the article). So, these 8 ICs are used to implement 8n-prefetch, ...
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How many DDR memory chips can be connected to Zynq UltraScale+ MPSoC ZCU104

I have a question regarding Zynq UltraScale+ MPSoC: how many DDR RAMs can be connected to the ZU7EV device, including both PS and PL banks ? Here is the link for TRM.
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1answer
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Additive latency for DRAM READ and WRITE commands [closed]

In TN-47-10 – DDR2 Posted CAS# Additive Latency Technical Note , what does it exactly mean by Additive latency (AL = 1) is only used for READ commands and will not affect WRITE command timing ?
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LPDDR on separate replaceable modules / boards - possible? drawbacks?

I've read that LPDDR is more efficient in active states and times more energy efficient than DDR in inactive states, e.g. in Performance vs power in off-chip DDR SDRAM, there is a mentioning of ...
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2answers
429 views

maximum memory supported by processor - why often stated less than 1TB?

I want to understand technical details of limitations of maximum memory size a system / processor can support. Below what I was able to find via web search to date Wiki: Modern 64-bit processors such ...
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0answers
45 views

DDR4 Routing Consideration

I'm designing a new PC based on Intel Tiger Lake UP3. In Intel Design Guide, I saw that there recommendation for DDR4 signals is to have two BO segments (BO1 and BO2). each BO has different impedance ...
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1answer
63 views

DDR3 logic levels - AC or DC?

In a DDR3 datasheet, I found different voltage levels (AC and DC.) I already know about DC logic levels but I don't know about AC logic levels. What is the difference between the two? Do the AC values ...
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33 views

Timing Diagram - HyperBus - HyperFlash - HyperRAM - RWDS - CLK - DQ

I'm trying to design an interface between an application processor and a HyperFlash memory from Cypress. Therefore, I'm trying to understand the timing diagram for RWDS and DQs relative to the CLK ...
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1answer
35 views

Is data width of an external DDR memory the same as the pins used to transfer data?

I'm trying to configure a Memory Interface Generator IP in Vivado. Somehow, the Block Automation doesn't work and I've to do it myself. The board I'm using is the Arty A7 development board. It has a ...
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1answer
117 views

How long can a DDR memory row be activated?

I need to test buffers output DC current of DDR-3 memory. I want to write to the memory only hFF's (or h00's) and then fetch it into output buffer. Then I whant to run an infinity burst. Is there any ...
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1answer
58 views

Mismatch of requirements from JEDEC with recommendations Intel(Altera)

I am studying the workings of DDR memory, in particular the recommendations for PCB layout. One of the intel documents (Table 1–24; Page 70) has the following wording: "Propagation delay of clock ...
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33 views

Xilinx primitives for DDR3 memory controller

I have finished simulating a Micron DDR3 controller, the DDR3 schematics and verilog code are located at https://github.com/promach/DDR However, I have concern on implementing it on the Spartan-...
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The concept of DDR rank

I have an understanding of DDR rank which I think is incorrect. If someone could join the dots then there would be more clarity. Here is what I know A DDR rank is a 64bit interface consisting of x8 ...
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1answer
50 views

DDR5 Standard: Changelog

I would like to upgrade a software simulator from DDR4 to DDR5. I was looking for a document that describes in detail the changes of the DDR5 standard but I couldn't. Is there any source that explains ...
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2answers
135 views

Highspeed Signals on outer layers of pcb

in many application notes for processors in a BGA package I see a declaration that you could fully fanout the bga using only 4-6 layers and almost no HDI technology like microvias, burried vias even ...
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43 views

DDR memory READ preamble and postamble

For Preamble detection and postamble closure for a memory interface controller , could anyone explain how the following Figure 4 , Figure 5 and Figure 6 work together to sample (or capture) the ...
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1answer
195 views

tRAS definition for DDR memory

In Figure 3 of https://www.systemverilog.io/understanding-ddr4-timing-parameters#refresh , why tRAS is defined as the max timing between two REFRESH commands ? This ...
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1answer
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My understanding of computer hardware architecture

Forgive my above crude diagram. Assume the above is the hardware architecture for a computer/mobile phone or any device which hold a microprocessor. Please let me know whether my understanding is ...
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2answers
414 views

What components of a DRAM (specifically LPDDR) memory do the power rails VDD1, VDD2 and VDDQ supply the power to?

I'm working on a project that tries to understand the power consumption of LPDDR memory under different operating modes such as active, idle, self-refresh, deep-power-down mode. With my experimental ...
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108 views

C code for DDR Access in Xilinx SoC devices

In my design, I want to write to DDR and then I want to fetch the data from DDR memory and then pass them to FPGA to be processed, after that, the data will be written back to DDR memory.I am using ...
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3answers
121 views

Calculating RAM memory capacity from schematic symbol

Is it possible to calculate the memory capacity of a RAM given its schematic symbol? I made a first guess from an example but seems to be incorrect: If the address bus is 15-bit width, there are a ...
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1answer
79 views

SystemVerilog usage of always_ff and fork join

The module is data central to setup the addr/data/command for set_cmd_pins() method, which is to translate these commands to pin-level signals which are a pair of methods to setup the DQS and DQ pin ...
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3answers
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Is ECC feature in DDR realized with using Hamming code technique?

The fundamental formula for a Hamming coding is as below: 2^k≥n+k+1 Where k = # of parity bits and n = data bits In a DDR system with ECC feature, every data byte will generate an additional ECC bit ...
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1answer
88 views

Why do DDR RAMs have both xDQ and xDM signals?

DDR2 RAMs have these control signals RAS, CAS - address strobes UDQ, LDQ - byte strobes WE - write enable UDM, LDM - write mask Why do we need UDM and LDM? Can't you write a byte by asserting WE and ...
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3answers
225 views

what is the most difficult part of creating a DDR2 or DDR3 memory controller inside an FPGA?

In this day and age we can just use the memory IP provided to us by the FPGA vendor be it a soft IP or hard IP. This makes it almost trivial to communicate with high speed memory devices like DDR2 and ...
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3answers
169 views

DDR: Is the real maximum speed half of what is advertised in datasheets?

Let's take a single 8-bit 200MHz DDR chip. All datasheets state that bandwidth is "up to" 400MB/s. Because it's dual, data is read/written on both edges so yes, theoretical, it's 400MB/s. ...
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1answer
50 views

ddr: Is there any significant delta between the different strobes?

In a DDR memory, during a read, output data from the DDR is aligned on the strobe. There is one strobe per 8-bit: UDQS/LDQS for a 16-bit-wide DDR DQS[0-3] for a 32-bit-wide DDR Is there any ...
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1answer
249 views

No terminations on point to point DDR3?

Are terminations required for DDR3 in point to point designs? I saw a reference design that doesn't include any termination to VTT for a controller/single DRAM design (pt to pt). DQS, DM and DQ use ...
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0answers
95 views

DDR4 Refresh VPP Power Consumption

My question may seem stupid but for a REFRESH operation on a single-rank DDR4 with multiple DRAM devices, how to properly estimate the DRAM power consumption ? I tried to use Micron Power Calculator ...
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2answers
907 views

DDR3 pcb design routing

I am trying to layout DDR3 128MB chip and a Spartan-6 FPGA. DDR signal pins located on specific memory controller pins and could not be swapped. I've never done DDR routing and went with SP605 Xilinx ...
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1answer
225 views

There is a way to write into FIFO on both clock edges?

Im using Lattice ECP3 FPGA, didnt found any information about it on the internet. I have ADC which providing me 12bits data on both clock edges, so I used Lattice High Speed I/O Interface: This ...
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1answer
661 views

Why cant clock be directly used instead of DQS in DDR during read and write

I have been reading about DDR lately and I am not able to understand the exact use of the DQS signal. The timing diagrams show dqs in phase with clock so why cant the clock only be used for the write ...
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1answer
309 views

Lattice FPGA problems with built-in DELAY module

I'm trying to delay an input data coming from ADC component in DDR to my FPGA, afterwards output it in the clock rising edge. The ADC Im using: ADS5463: Im using Lattice ECP3 FPGA, based on the fpga ...
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2answers
202 views

How to Output DDR data to 1 register

I have an Input which provides DDR data, I need to capture it and output it from the FPGA in one register (12bit). How can I do it? What I did for now is to capture the input data with always block ...
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1answer
108 views

What if ddr4 Termination is done at last word component

Memory Component : MT40A256M16 Controller : Xilinx MPSOC - PS Side Question : I have mistakenly provided the DDR4 termination resistances at the first data lane and the layout engineer has completed ...
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1answer
167 views

DDR4 board bringup issue

I am struggling with a DDR4 related board bringup issue. Can anyone out there recognise what the problem is by studying the attached memory dumps? The memory dump is from Preboot loader PB31 area of ...
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1answer
332 views

ADC with parallel DDR LVDS interface and also a parallel CMOS interface

The ADS4126 is a 12-Bit, 160-MSPS Analog-to-Digital Converter (ADC). Its data rate is too high for it to be read out using something like SPI or I2C. It does use SPI for control purpose though. The ...
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2answers
398 views

DDR Interface Protocol

I have seen and worked with interfaces like SPI and I2C. However, when I started to learn about DDR interface/communication protocol, I want to understand like how many lines, what are the important ...
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58 views

DRAM Memory Lines

I have been trying to understand DDR and DRAM memories and stumbled upon this video In this video, from 20:00 to 23:00 he tells that the 8kb row buffer lines, actually come out as 64b and this 64b ...
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1answer
138 views

What is voltage level in DDR5 defined by JEDEC?

Voltage level in DDR4 is 1.2 volt, will it be same in DRR5 also? Also how much maximum voltage fluctuation will be allowed?
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1answer
150 views

Why DDRx I/O bus frequency is half effective frequency?

I've already known that I/O buffer transfers data on both the rising and falling edges of the clock signal. But it really confused me why I/O bus frequency is half of effective frequency. For ...
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2answers
4k views

What is the difference between DRAM channel and DRAM Rank?

Can someone explain me the terms : DRAM Rank and a DRAM Channel is simple terms. I went through this PDF and I was not able to understand the DRAM Organisation/architecture on page 3 and page 11. Can ...
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1answer
115 views

What is the theoretical throughput limit of DDR SDRAM read only

I wonder how fast I can read from a DDR SDRAM (known as DDR1) clocked at 200MHz. The controller will be implemeted on an FPGA. I have 8 bit data interface to the DDR. Each data pin reached 400Mbps. ...
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109 views

DDR3 RAM - possible Row Hammer

Tl; Dr; I make a lot of reads to a RAM, physically incrementing the address and get more errors every time i restart the read process on address 0x0. Is this the Row-Hammer ? I made a question ...
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1answer
138 views

Can I run a DDR4 module at 50 MHz?

I haven't seen any restrictions about minimum clock, but I may have overlooked them. EDIT: The module is a Crucial CT4G4SFS824A, based (this is an informed guess) on 4Gb Micron 512 Meg x 8
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1answer
300 views

Why do we have single ended DQ and differential DQS in DDRIO?

if differential can reduce cross talks, why do we use single ended DQ? And we know DQS is differential from DDR2
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1answer
1k views

why pre-post amble is required?

why do we need pre-post amble for READ or WRITE DQS ? 1 ) one reason could be --> Because transitions of voltages from logic level 0 to 1 or 1 to 0 take time to complete: so the strobe is asserted a ...
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354 views

DDR UDQS and LDQS into one DQS controller

I have one x16 memory chip () that has two Data Strobe pairs (UDQS and LDQS), on the other hand, I have arm chip (i.MX6 ULZ) that has one Data Strobe pair (DQS). Is there any way of connecting them, I'...
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High speed interfaces and FPGAs [closed]

Please excuse me if my question is very naive or broad. I just wanted to get some direction. I didn't know how else to ask for help. I am working on Analog electronics and MCUs. It seems to be ...