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Questions tagged [ddr]

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84 views

DDR4 board bringup issue

I am struggling with a DDR4 related board bringup issue. Can anyone out there recognise what the problem is by studying the attached memory dumps? The memory dump is from Preboot loader PB31 area of ...
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13 views

8 WCK toggles for Write Leveling in LPDDDR5

What is purpose of having 8 toggles on WCK for Write Leveling in LPDDR5? First toggle of WCK may be ignored due to instability by DRAM. And the DRAM feed-backs phase relationship of last WCK-CK on DQ. ...
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1answer
34 views

ADC with parallel DDR LVDS interface and also a parallel CMOS interface

The ADS4126 is a 12-Bit, 160-MSPS Analog-to-Digital Converter (ADC). Its data rate is too high for it to be read out using something like SPI or I2C. It does use SPI for control purpose though. The ...
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2answers
84 views

DDR Interface Protocol

I have seen and worked with interfaces like SPI and I2C. However, when I started to learn about DDR interface/communication protocol, I want to understand like how many lines, what are the important ...
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49 views

DRAM Memory Lines

I have been trying to understand DDR and DRAM memories and stumbled upon this video In this video, from 20:00 to 23:00 he tells that the 8kb row buffer lines, actually come out as 64b and this 64b ...
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1answer
40 views

What is voltage level in DDR5 defined by JEDEC?

Voltage level in DDR4 is 1.2 volt, will it be same in DRR5 also? Also how much maximum voltage fluctuation will be allowed?
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1answer
55 views

Why DDRx I/O bus frequency is half effective frequency?

I've already known that I/O buffer transfers data on both the rising and falling edges of the clock signal. But it really confused me why I/O bus frequency is half of effective frequency. For ...
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2answers
109 views

What is the difference between DRAM channel and DRAM Rank?

Can someone explain me the terms : DRAM Rank and a DRAM Channel is simple terms. I went through this PDF and I was not able to understand the DRAM Organisation/architecture on page 3 and page 11. Can ...
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1answer
41 views

What is the theoretical throughput limit of DDR SDRAM read only

I wonder how fast I can read from a DDR SDRAM (known as DDR1) clocked at 200MHz. The controller will be implemeted on an FPGA. I have 8 bit data interface to the DDR. Each data pin reached 400Mbps. ...
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0answers
98 views

DDR3 RAM - possible Row Hammer

Tl; Dr; I make a lot of reads to a RAM, physically incrementing the address and get more errors every time i restart the read process on address 0x0. Is this the Row-Hammer ? I made a question ...
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1answer
89 views

Can I run a DDR4 module at 50 MHz?

I haven't seen any restrictions about minimum clock, but I may have overlooked them. EDIT: The module is a Crucial CT4G4SFS824A, based (this is an informed guess) on 4Gb Micron 512 Meg x 8
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1answer
44 views

Why do we have single ended DQ and differential DQS in DDRIO?

if differential can reduce cross talks, why do we use single ended DQ? And we know DQS is differential from DDR2
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1answer
122 views

why pre-post amble is required?

why do we need pre-post amble for READ or WRITE DQS ? 1 ) one reason could be --> Because transitions of voltages from logic level 0 to 1 or 1 to 0 take time to complete: so the strobe is asserted a ...
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2answers
80 views

DDR UDQS and LDQS into one DQS controller

I have one x16 memory chip () that has two Data Strobe pairs (UDQS and LDQS), on the other hand, I have arm chip (i.MX6 ULZ) that has one Data Strobe pair (DQS). Is there any way of connecting them, I'...
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2answers
86 views

High speed interfaces and FPGAs [closed]

Please excuse me if my question is very naive or broad. I just wanted to get some direction. I didn't know how else to ask for help. I am working on Analog electronics and MCUs. It seems to be ...
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0answers
61 views

Altera/Intel FPGA Interfacing External Memory

I am in the process of making a prototype PCB with an Altera Cyclone IV or V FPGA and 2 channels of external memory, one channel for a softcore CPU and one channel for a 2d graphics accelerator. I ...
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3answers
6k views

Why does RAM (any type) access time decrease so slowly?

This article shows that DDR4 SDRAM has approximately 8x more bandwidth DDR1 SDRAM. But the time from setting the column address to when the data is available has only decreased by 10% (13.5ns). A ...
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1answer
2k views

Data Strobe in DDR memory

In DDR3 memory there is a signal called DQS that I have several question about. What is DQS abbreviated for? specially Q What is the purpose of data strobe in DRAM and why not use simple clock. Is ...
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1answer
46 views

Using narrower DDR RAM than controller

I have some ARM processor that have 72-bit width (8 for ECC) RAM controller. Can I buy eg. two 32bit chips and combine them? If yes then how? Can I buy just one 32bit and pull down rest of data pins ...
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1answer
109 views

DDRx timing analysis

I have a question regarding timing analysis for DDR3 and DDR4 signals. How do we do timing analysis to see if all setup and hold requirements are fulfilled correctly, considering they have write ...
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2answers
4k views

Why use DDR instead of increasing clock speed?

Why would you want to use DDR ram and read/write on every rising and falling edge of the clock instead of just doubling your clock speed and read/write on just one of either the rising or falling edge?...
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1answer
88 views

DRAM memory organisation

I've been trying to understand the working of DRAM chips but apparently in a lot of confusion. Suppose there are 8 banks in a single chip on a module. Is it only one bit that comes out of a single ...
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1answer
69 views

how is ddr4 controlled on the laptop

I am a student of electrical engineering and my previous term's project was implementing ddr2 SDRAM with Xilinx FPGA, but I am interested to know which device on the laptop control ddr4 on it? and ...
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0answers
229 views

DDR2 and DDR3 ODT and ZQ calibration

Can anyone please explain what is the difference in ODT and ZQ technique used in DDR2 and DDR3?? Which method is very useful for DDR2 termination? whether ODT or External parallel termination?? ...
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1answer
81 views

what is the difference between D and D/L flip-flops?

I'm trying to understand how a DDR receive circuit works. I'm reading the MachXO2 Family Data Sheet, page 22: http://www.latticesemi.com/view_document?document_id=38834 What I don't get is this: ...
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2answers
264 views

Inserting an FPGA on a MIPI camera lane [closed]

I have a processor which accepts MIPI data. However, the problem is I want to perform some processing on this data and the IMX6 is not fast enough to do this in real time. I was wondering what is the ...
2
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1answer
117 views

DDR Trace Length Inside Package from Simulation Model

The DDR4 in question is a Micron MT40A512M16JY. From the vendor site, you can get the datasheets, specs, sim models. I assume from the sim models you should be able to see the trace length of each ...
2
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1answer
662 views

DDR4 pull-up resistors and decoupling clock lines

I am trying to understand the layout of a DDR4 chip connected to a FPGA. The schematic follows: I tried to look for datasheets from the memory manufacturer explaining how to properly pull-up or pull-...
1
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1answer
228 views

Is there a rule for DDR4 CA signals reference plane?

I'd like to know if there is any rule for the reference plane of DDR4 CA signals in PCB layout. I saw some design guide which specify the reference plane to be VDDQ power plane for CA signals, but I'm ...
2
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1answer
104 views

MachXO2 DDR and PCLK routing issue

I'm doing a project in which I use DDR interfaces to transmit and receive data between different FPGAs. The FPGA transmitter will send data at 125 MHz and the receiver will use 250 MHz to sample the ...
3
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3answers
503 views

Parallel access to memory with multiple DDR4 chips

Some development boards have multiple DDR4 chips. Does it imply that such boards have multiple DDR controllers and memory can be accessed in parallel. For example this boards: https://www.xilinx.com/...
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1answer
424 views

DDR3 memory transfer rate

I am trying to understand memory transfer rate while working with DDR3. I am getting different numbers. For example, in Wikipedia https://en.wikipedia.org/wiki/DDR3_SDRAM DRAM has peak transfer rate ...
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1answer
407 views

Theoretical calculation of DDR3L transfer speed

I am not sure if this questions belongs to this stack exchange site but I didn't find other better one. In case it doesn't, let me know and I will move it to some other place. I am working with a ...
2
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1answer
650 views

DDR4 differential pair routing guideline

I have a question about the DDR4 trace routing on the server main board. For clock and DQS signals, are they both considered differential signals? I checked the Intel PDG; it shows that two specs ...
0
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1answer
168 views

PIC32MZ DA Separate DDR grounding

I am puzzling over the purpose of ferrite beads and grounding on the PIC32MZ DA starter kit. On page 34 of the User Guide it shows L2 and L3, and a separate Ground and power net. It would appear ...
3
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1answer
144 views

How might an LPDDR2 PHY be designed?

I was reading the LPDDR2 spec today out of curiosity. While browsing the spec I became curious about "how might one hypothetically design a minimal working LPDDR2 PHY on paper/for simulation, perhaps ...
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2answers
2k views

What's the standard procedure of DDR4 training?

I have a question about DDR4 training sequence, and hope someone can give me some information. As I know, there will be training sequence at system boot. (In my system, it's called 1D/2D training, ...
2
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1answer
70 views

Electrical principle of row hammer glitch

There is a fairly new and exploitable bug happening in some DDR3 DRAMs called the "row hammer" in which it's possible to bit flip memory cells. I understand how the exploit works, but not the ...
2
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2answers
280 views

Understanding DDRn SDRAM

So I am basically trying to grasp/confirm my grasp of SDRAM and DDR. So basically I understand that there is going to be some chips each with up to 8 banks (so kinda like 8 chips internally?). For ...
2
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2answers
140 views

LPDDR2 clock long term jitter issue

I have a problem with LPDDR2 clock period cumulative error measurement tERR(11-50per) but shorter length measurement are OK with some margin. I'm looking at some cause or tips to understand or fix ...
0
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1answer
76 views

Choose “safe” section of DDR memory in ZC702 board

I can not fully understand what section of the available external memory is safe to assign for a VDMA on the ZC702 board. I need to dedicate 4MB of memory for the three frames (640*480* 4bytes * 3 ...
1
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1answer
824 views

LPDDR2 reference design?

I've been trying to interface LPDDR2 ram with my SOC but got confused as to how to connect the CA lines. Does anyone have any reference designs of LPDDR2 for me to go off of?
1
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1answer
415 views

lpddr2 interface differences between different memory controllers?

The way LPDDR2 connections are done with CA bus is different between these two processors. I thought since LPDDR2 is a JEDEC standard, these schematics should be interfacing with the same lines from ...
0
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2answers
114 views

Combining decoupling capacitors for sensitive power requirements in LPDDR

I've been looking through a bunch of designs I found online on LPDDR2 interfacing. What's always confused me is the parallel decoupling capacitors. Why have so many vs just combining that to what you ...
6
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2answers
967 views

Weird 240 ohm resistor on zq line to DDR

I've been looking at schematics that interface ddr ram and noticed a weird notation for their zq pull down resistor. What is with the dot at the top as well as the 1%? Haven't seen this before.
5
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1answer
572 views

What is the difference between LPDDR2-S2 vs S4?

Looking at page 18 of the JEDEC spec on LPDDR2 LPDDR2-S2 also uses a double data rate architecture on the DQ pins to achieve high speed operation. The double data rate architecture is essentially a ...
2
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1answer
373 views

What is the more frequent error in DDR Memory?

this is about DDR memory data corruption and not about STUCK address or data lines. If we have a good DDR with no memory stuck issues and we perform lots of writes and reads which type of error is ...
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1answer
93 views

Does a DDR RAM device exist which would allow RAM to be removed and preserved? [closed]

Hello I would like to know if there any device which could preserve content of RAM once removed from a host system and this special device could be connected perhaps by way of USB to another machine ...
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1answer
932 views

Moving a large dataset from the PS to PL on a zynq device?

I am at the moment trying to interface with DRAM on my Xilinx Zynq device such that I am capable of moving a large amount of data from the processing system (PS) side to the programmable logic (PL). ...
2
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1answer
725 views

What is traffic generator (while using Xilinx Memory Interface Generator)

I am trying to use the Memory controller Block in my Xilinx Spartan 6 FPGA to set up an interface with LPDDR memory. I read the MCB User guide, and I am quite clear about how it works, and how I would ...