Questions tagged [ddr]
The ddr tag has no usage guidance.
136
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DDRX Memory : What does DRAM prefetch mean? Also, why is the I/O bus clock half of the transfer rate?
While looking at the chart below, I had a question about DRAM prefetch & I/O Bus clock.
The characteristic of DDR is that it transfers 2 sets of data every cycle.
Therefore, for older versions of ...
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1
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82
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What are the options to interface Altera or Xilinx FPGA with a microprocessor or microcontroller?
I am trying to design a system which has some sensors connected to an FPGA and want to transfer the sensor data from the FPGA to a microprocessor like NXP IMX. I am new to FPGA and would like to know ...
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Mark Horowitz Computing's energy problem - methodology
I have a question about the Mark Horowitz paper: Computing’s Energy Problem
(and what we can do about it). In the paper, the author breaks down the sources of energy loss in modern computing systems.
...
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Why is there a tRRD in DDR3? There does not seem to be a resource conflict between different banks
In DDR3, bank activation is specific to the Bank, for different banks, they all have their own sense amp and do not seem to affect each other, so why would there be tRRD?
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DAC DDR Interface with Vivado and Zynq7000
i need to connect a dual-channel DAC (AD9117) to a Zynq 7000 FPGA. The DAC has a DDR Interface, on which the Data for Channel 1 is clocked on the rising edge and the data for channel 2 on the falling ...
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Calculating DDR4 DRAM Timing Parameters
If DDR4 runs at 1600Mhz, then how to calculate value of a parameter if its value is given as Max(4nCK, 5ns)?
I am assuming it means value of the parameter is ...
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2
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Is there any chance to embed two DDR IP cores into FPGA so that I can implement dual-channel memory architecture?
What I want is to implement a dual-channel memory architecture on a FPGA development board and verify that it is really faster than single channel.
At first I was thinking of configuring on-board DDR ...
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Why is the DDR termination voltage half the supply voltage? [closed]
Why is the DDR termination voltage (VTT) one-half the VDD voltage?
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382
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Why is the burst order of DDR3 DRAM not sequential?
Based on the JEDEC DDR3 documentation as shown below, when we are reading with burst length of 8 and starting column address of 010 (0x2), the burst order will be <...
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Does JTAG use DDRAM?
I have a microcontroller with external DDRAM. When I debug with JTAG I can see that there is code placed in the DDRAM region. However I never see the initialization of DDRAM code is run. I wonder does ...
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What is meant by Vil(ac) and Vih(ac) in signals?
The VIH(dc) & VIL(dc) is used to determine logic low or logic high of the signal. When I go through document of DDR, there is another term like VIH(ac) and VIL(ac). What is mean by it and its uses?...
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What's the purpose of the DDR4 1X, 2X and 4X refresh modes?
The DDR4 specification defines 1x, 2x and 4x refresh modes as follows:
The default Refresh rate mode is fixed 1x mode where Refresh commands
should be issued with the normal rate, i.e., tREFI1 = ...
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What is mean by VREF Training in DDR4?
While going through DDR3 and DDR4, there is a term called vref. Where in DDR3 it is outside the DDR and for DDR4 it is inside the chip. Why we need training for it. What is the use of it.
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Any tips for routing SODIMM DDR?
I was trying to look online for any tips for wiring SODIMM RAM (LPDDR4), as I was trying to make a modular, replaceable microprocessor board, and I just wanted to ask if there were any extremely ...
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Length matching on DDR3 dataline in simulation for STM32MP1
I'm using HyperLynx to emulate my STM32MP157AAA3 small form factor system board with DDR3-1066 memory.
When I use DDRx batch simulation:
I confirmed that my ODT model is configured correctly. Use 48 ...
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DDR Trace Length in Motherboards
I was trying to understand DDR, Trace-length, and signal integrity.
Most of the datasheets, For example, iMX8M Mini (Doc: IMX8MMHDG) clearly specifies what are the requirements for the each signal in ...
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Why did GDDR5X implement QDR?
DDR makes complete sense to me: it matches up the transition rate between the data signals and clock, so that twice the data can be sent over a bus without increasing the overall design bandwidth. The ...
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Why was full page bursting removed when we moved to DDR
I'm interfacing with SDRAM on an FPGA and full page bursts are a godsend for streaming data. It's seems to be much, much more handy then a fixed burst size. I know it was removed when we moved to DDR. ...
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How do I find out what pins of an Intel FPGA can be used to connect to different pin groups in EMIF?
If I want to connect my Intel FPGA using EMIF to a high speed DDR Memory e.g Cyclone IV E to DDR3 memory or Max 10 to DDR2 memory, how do I find out what pins can be used for the data, strobe, clock, ...
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Can I use LPDDR3 memory that is larger than my processor supports?
I am working on a thing that uses a STM32MP157C. Its datasheet says:
The STM32MP157C/F devices embed a controller for external SDRAM which support the following devices
• LPDDR2 or LPDDR3, 16- or 32-...
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How much skew correction can typically be applied to DQS during DDR4 link training?
My understanding of the DDR4 calibration process is that DQS is derived from a common clock with a PLL, then passed through a DLL to apply deskew such that DQS and CK edges arrive in sync.
Is there ...
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DDR interfacing with rockers3399 processor
I am using rockers 3399 processor in one of my applications. if you see page no 9 'External Memory or Storage device' section you can see the below things
*Support 2 channels, each channel is 16 or ...
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654
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LPDDR: is pluggable (socketed, not soldered) connection possible for low voltage?
I've already asked the question about plausibility of socketed LPDDR here and got an answer LPDDR on separate replaceable modules / boards - possible? drawbacks?
You could probably extend LPDDR onto ...
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How many DDR memory chips can be connected to Zynq UltraScale+ MPSoC ZCU104
I have a question regarding Zynq UltraScale+ MPSoC: how many DDR RAMs can be connected to the ZU7EV device, including both PS and PL banks ?
Here is the link for TRM.
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Additive latency for DRAM READ and WRITE commands [closed]
In TN-47-10 – DDR2 Posted CAS# Additive Latency Technical Note , what does it exactly mean by Additive latency (AL = 1) is only used for READ commands and will not affect WRITE command timing ?
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LPDDR on separate replaceable modules / boards - possible? drawbacks?
I've read that LPDDR is more efficient in active states and times more energy efficient than DDR in inactive states, e.g. in Performance vs power in off-chip DDR SDRAM, there is a mentioning of ...
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maximum memory supported by processor - why often stated less than 1TB?
I want to understand technical details of limitations of maximum memory size a system / processor can support. Below what I was able to find via web search to date Wiki:
Modern 64-bit processors such ...
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DDR4 Routing Consideration
I'm designing a new PC based on Intel Tiger Lake UP3.
In Intel Design Guide, I saw that there recommendation for DDR4 signals is to have two BO segments (BO1 and BO2).
each BO has different impedance ...
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DDR3 logic levels - AC or DC?
In a DDR3 datasheet, I found different voltage levels (AC and DC.) I already know about DC logic levels but I don't know about AC logic levels.
What is the difference between the two?
Do the AC values ...
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Timing Diagram - HyperBus - HyperFlash - HyperRAM - RWDS - CLK - DQ
I'm trying to design an interface between an application processor and a HyperFlash memory from Cypress. Therefore, I'm trying to understand the timing diagram for RWDS and DQs relative to the CLK ...
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Is data width of an external DDR memory the same as the pins used to transfer data?
I'm trying to configure a Memory Interface Generator IP in Vivado. Somehow, the Block Automation doesn't work and I've to do it myself.
The board I'm using is the Arty A7 development board. It has a ...
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How long can a DDR memory row be activated?
I need to test buffers output DC current of DDR-3 memory. I want to write to the memory only hFF's (or h00's) and then fetch it into output buffer. Then I whant to run an infinity burst. Is there any ...
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Mismatch of requirements from JEDEC with recommendations Intel(Altera)
I am studying the workings of DDR memory, in particular the recommendations for PCB layout.
One of the intel documents (Table 1–24; Page 70) has the following wording: "Propagation delay of clock ...
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Xilinx primitives for DDR3 memory controller
I have finished simulating a Micron DDR3 controller,
the DDR3 schematics and verilog code are located at https://github.com/promach/DDR
However, I have concern on implementing it on the Spartan-...
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The concept of DDR rank
I have an understanding of DDR rank which I think is incorrect. If someone could join the dots then there would be more clarity.
Here is what I know
A DDR rank is a 64bit interface consisting of x8 ...
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DDR5 Standard: Changelog
I would like to upgrade a software simulator from DDR4 to DDR5. I was looking for a document that describes in detail the changes of the DDR5 standard but I couldn't.
Is there any source that explains ...
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Highspeed Signals on outer layers of pcb
in many application notes for processors in a BGA package I see a declaration that you could fully fanout the bga using only 4-6 layers and almost no HDI technology like microvias, burried vias even ...
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tRAS definition for DDR memory
In Figure 3 of https://www.systemverilog.io/understanding-ddr4-timing-parameters#refresh , why tRAS is defined as the max timing between two REFRESH commands ? This ...
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My understanding of computer hardware architecture
Forgive my above crude diagram.
Assume the above is the hardware architecture for a computer/mobile phone or any device which hold a microprocessor.
Please let me know whether my understanding is ...
user220456
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What components of a DRAM (specifically LPDDR) memory do the power rails VDD1, VDD2 and VDDQ supply the power to?
I'm working on a project that tries to understand the power consumption of LPDDR memory under different operating modes such as active, idle, self-refresh, deep-power-down mode. With my experimental ...
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C code for DDR Access in Xilinx SoC devices
In my design, I want to write to DDR and then I want to fetch the data from DDR memory and then pass them to FPGA to be processed, after that, the data will be written back to DDR memory.I am using ...
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Calculating RAM memory capacity from schematic symbol
Is it possible to calculate the memory capacity of a RAM given its schematic symbol?
I made a first guess from an example but seems to be incorrect:
If the address bus is 15-bit width, there are a ...
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SystemVerilog usage of always_ff and fork join
The module is data central to setup the addr/data/command for set_cmd_pins() method, which is to translate these commands to pin-level signals which are a pair of methods to setup the DQS and DQ pin ...
user263276
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Is ECC feature in DDR realized with using Hamming code technique?
The fundamental formula for a Hamming coding is as below:
2^k≥n+k+1
Where k = # of parity bits and n = data bits
In a DDR system with ECC feature, every data byte will generate an additional ECC bit ...
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Why do DDR RAMs have both xDQ and xDM signals?
DDR2 RAMs have these control signals
RAS, CAS - address strobes
UDQ, LDQ - byte strobes
WE - write enable
UDM, LDM - write mask
Why do we need UDM and LDM? Can't you write a byte by asserting WE and ...
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what is the most difficult part of creating a DDR2 or DDR3 memory controller inside an FPGA?
In this day and age we can just use the memory IP provided to us by the FPGA vendor be it a soft IP or hard IP. This makes it almost trivial to communicate with high speed memory devices like DDR2 and ...
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DDR: Is the real maximum speed half of what is advertised in datasheets?
Let's take a single 8-bit 200MHz DDR chip. All datasheets state that bandwidth is "up to" 400MB/s.
Because it's dual, data is read/written on both edges so yes, theoretical, it's 400MB/s.
...
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ddr: Is there any significant delta between the different strobes?
In a DDR memory, during a read, output data from the DDR is aligned on the strobe. There is one strobe per 8-bit:
UDQS/LDQS for a 16-bit-wide DDR
DQS[0-3] for a 32-bit-wide DDR
Is there any ...
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No terminations on point to point DDR3?
Are terminations required for DDR3 in point to point designs? I saw a reference design that doesn't include any termination to VTT for a controller/single DRAM design (pt to pt). DQS, DM and DQ use ...
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DDR4 Refresh VPP Power Consumption
My question may seem stupid but for a REFRESH operation on a single-rank DDR4 with multiple DRAM devices, how to properly estimate the DRAM power consumption ?
I tried to use Micron Power Calculator ...
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